CN109446125A - DDR reads and writes moderator and method - Google Patents
DDR reads and writes moderator and method Download PDFInfo
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F13/14—Handling requests for interconnection or transfer
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Abstract
The invention discloses a kind of DDR read-write moderator and method, DDR read-write moderator mainly includes to read converting unit, write converting unit, fair arbitration unit, order split cells, flow control protection location, handshake logic unit, route control unit, the first cell fifo, the second cell fifo, third cell fifo.The present invention can be achieved multichannel and read and write user's concurrent access；It writes user and reads the conversion of user interface to moderator interface, by the application segment processing of user；It reads user and writes the data buffer storage management of user；Fair arbitration is realized to multi-user；The command stream and data flow that the application dismantling for reading and writing user can be performed at DDR controller；DDR flow control protection mechanism；User reads data routing.
Description
Technical field
The present invention relates to DDR more particularly to DDR read-write moderator and referee methods.
Background technique
DDR memory has been widely used at present in each product solution.Currently, being integrated with DDR control in many CPU
Device processed, operating system and application program determine the scheduling process to DDR controller.However, higher for requirement of real-time
Special digital circuit design, FPGA or asic chip are easy to control to the scheduling problem of DDR unlike to software systems
System.In the field FPGA, Xilinx and Intel both provide mature and free DDR controller IP, but these IP are both for one
A user's.In system design, it is understood that there may be multiple modules need simultaneously to access to DDR controller.Generally use arbitration
Device solves multiple users to the right to use assignment problem of DDR controller.More easy moderator, usually will entirely access
Period is fully allocated to a certain user, and the processes such as shake hands, wait during which waste many times, eventually lead to the access of DDR
Efficiency does not increase.The access behavioral characteristic of different user is different: the access data volume having is big, if moderator once allows it institute
Have that data access is complete, then the application of other users cannot may be responded slowly, lead to system mistake；Some writes amount of user data
It is small, it has initiated after writing application, has write data and do not come slowly, or write the data bandwidth of user and do not catch up with the speed of DDR controller；Have
Reading user, the rate that data are read in processing do not have that DDR controller is fast, in order to avoid cache overflow, needs to wait for user and handled reading
Continue to access DDR controller after data.This is all the reason for causing DDR controller access efficiency not high.It is provided by the present invention
DDR reads and writes referee method, can preferably solve the above problems.
Summary of the invention
The purpose of the present invention is to provide a kind of DDR to read and write referee method, is mainly used for programmable logic system or ASIC
In field, when multi-user's concurrent access DDR memory, the access efficiency of DDR is improved.
Used technical solution is the present invention for the above-mentioned purpose:
A kind of DDR read-write moderator is provided, comprising:
It is multiple to write converting unit, for the write operation for writing a certain length data of user's application to be subdivided into multiple small batches
Write apply and submit to order split cells；
Multiple reading converting units, for the read operation for reading a certain length data of user's application to be subdivided into multiple small batches
Reading application and submit to order split cells；
Order split cells, for being further split into the identifiable finger of DDR controller for the reading and writing order of small batch
It enables, and reading and writing order is stored in the first cell fifo, data will be write and be stored in the second cell fifo；
Fair arbitration unit for each reading user and writing user and being numbered, and decides its priority, and
Routing table is generated to be stored in third cell fifo；
Flow control protection location, for monitoring the first cell fifo, whether the second cell fifo has enough allowances, if it is not, then
Pause command split cells splits the order of present lot；
Handshake logic unit, for by reading and writing order and writing data respectively from the first cell fifo and the second cell fifo
Middle reading is sent to DDR controller according to the requirement of shaking hands of DDR controller；
Route control unit, for obtaining routing table from third cell fifo, in DDR controller returned data, according to
Routing table is routed.
Above-mentioned technical proposal is connect, when reading converting unit and writing converting unit subdivision small batch, batch size is arranged to DDR
ROW length 1/2 or 1/4.
Above-mentioned technical proposal is connect, converting unit is read and is also used to calculate the non-returned data of DDR controller and based thereon determines whether
Continue to submit and read application, specially records itself altogether to the reading data amount check of DDR controller application, and record DDR control
Device returned to altogether how many and reads data, and the difference of the two is the data that DDR controller does not return, and DDR controller is not returned
Remaining data volume in data, the second cell fifo, maximum number in batches are added, and if greater than the second cell fifo depth
L then reads converting unit and reading is no longer submitted to apply.
Above-mentioned technical proposal is connect, remaining data volume in the data that do not return when DDR controller, the second cell fifo, most
Number is added greater than L-4 in batches greatly, then reads converting unit and reading is no longer submitted to apply.
Above-mentioned technical proposal is connect, converting unit is write and is also used to judge whether there are enough data empty in the second cell fifo
Between, if then continuing that present lot is submitted to write application.
DDR according to claim 1 reads and writes moderator, which is characterized in that flow control protection location is specifically used for the
The pre- full state of one cell fifo and the second cell fifo is monitored, and when the first cell fifo is pre- full, reading and writing order is both needed to
It waits；When the second cell fifo is pre- full, write order pause, read command continues to split.
The present invention also provides a kind of DDR to read and write referee method, comprising the following steps:
Multiple reading users and the reading and writing operation for writing user are subdivided into the reading and writing application of multiple small batches；
The reading and writing order of small batch is further split into the identifiable instruction of DDR controller, and reading and writing order is deposited
Enter the first cell fifo, data will be write and be stored in the second cell fifo；
It to each reading user and writes user and is numbered, and its priority is decided, and generate routing table and be stored in
In third cell fifo；
Monitor the first cell fifo, whether the second cell fifo has enough allowances, if it is not, then suspending the order of present lot
It splits；
It by reading and writing order and writes data and is read from the first cell fifo and the second cell fifo respectively, controlled according to DDR
The requirement of shaking hands of device is sent to DDR controller；
Routing table is obtained from third cell fifo, and routing choosing is carried out according to routing table in DDR controller returned data
It selects.
Above-mentioned technical proposal is connect, when segmenting small batch, batch size is arranged to the 1/2 or 1/4 of the ROW length of DDR.
Above-mentioned technical proposal is connect, the non-returned data of DDR controller is calculated and based thereon determines whether to continue to submit to read application, tool
Body is record altogether to the reading data amount check of DDR controller application, and records DDR controller and returned to how many readings altogether
According to the difference of the two is the data that DDR controller does not return, residue in the data that DDR controller is not returned, the second cell fifo
Data volume, maximum number in batches be added, and if be greater than L-4, read converting unit and no longer submit reading application, L second
The depth of cell fifo.
Above-mentioned technical proposal is connect, it is next that user is effectively write by application for adjudication when user's application is read in response, in advance will
It is write data and imports the second cell fifo.
Beneficial effects of the present invention: the single user read-write interface of DDR controller is extended to and supports multi-user simultaneously by the present invention
It sends out the reading interface of access and writes interface.It is each read user and write user enjoy it is impartial by service opportunity, that is, when avoiding one party long
Between monopolize DDR bus the case where.And in Multi-Client Concurrency Access, still ensure that (batch accesses higher DDR service efficiency
When, efficiency can reach 80% or more).
Further, the user oriented read-write interface of the present invention, relative to the read-write interface of DDR control, operating process is more
Easy and easily realization.Abundant excavation to DDR room and time resource, not only improves system performance, moreover it is possible to reduce design cost.
Detailed description of the invention
Below in conjunction with drawings and the embodiments, the invention will be further described, in attached drawing:
Fig. 1 is DDR of embodiment of the present invention read-write moderator structural schematic diagram.
Fig. 2 is the external interface for writing converting unit.
Fig. 3 is the external interface for reading converting unit.
Fig. 4 is order application interface sequence explanation.
Fig. 5 is to write data stream interface timing explanation.
Fig. 6 is fair arbitration example.
Fig. 7 is DDR of embodiment of the present invention read-write arbitration process figure.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that described herein, specific examples are only used to explain the present invention, not
For limiting the present invention.
The structure of DDR read-write moderator of the invention is as shown in Figure 1, main comprising reading converting unit, writing converting unit, public affairs
Flat arbitration unit, order split cells, flow control protection location, handshake logic unit, route control unit, FIFO1, FIFO2,
FIFO3。
It is multiple to write converting unit, for the write operation for writing a certain length data of user's application to be subdivided into multiple small batches
Write apply and submit to order split cells；
Multiple reading converting units, for the read operation for reading a certain length data of user's application to be subdivided into multiple small batches
Reading application and submit to order split cells；
Order split cells, for being further split into the identifiable finger of DDR controller for the reading and writing order of small batch
It enables, and reading and writing order is stored in FIFO1, data will be write and be stored in the second cell fifo；
Fair arbitration unit for each reading user and writing user and being numbered, and decides its priority, and
Routing table is generated to be stored in FIFO3；
Flow control protection location, for monitoring whether FIFO1, FIFO2 have enough allowances, if it is not, then pause command splits list
Member splits the order of present lot；
Handshake logic unit, for by reading and writing order and writing data and being read from FIFO1 and FIFO2 respectively, according to DDR
The requirement of shaking hands of controller is sent to DDR controller；
Route control unit, for from FIFO3 obtain routing table, in DDR controller returned data, according to routing table into
Row Route Selection.
The external interface of converting unit is write, as shown in Fig. 2.Writing converting unit includes that write order control module and is write in batches
Fifo module, the write operation of data with arbitrary length can once be applied for by writing user, and control module is thin by this application in batches for write order
Be divided into multiple small batches writes application, submits to fair arbitration unit.The data for writing user, which are first buffered in, to be write in fifo module, when
After the response application of DDR moderator, this is write into the data forwarding in fifo module to moderator.
The external interface of converting unit is read, as shown in Fig. 3.Reading converting unit includes read command control module and reading in batches
Fifo module, the read operation of data with arbitrary length can once be applied for by reading user, and control module is thin by this application in batches for read command
It is divided into the reading application of multiple small batches, submits to fair arbitration unit.The reading data of route control unit output, are first buffered in reading
In fifo module, read to read to take away in fifo module from this by data when user itself is ready.
It is impartial by service opportunity to guarantee that multiple read-write users enjoy for fair arbitration unit.Its another feature is, in sound
It is next that user is effectively write by application for adjudication when should read user's application, data importing can be write in advance writes data FIFO,
Further increase the throughput of moderator.
The read write command of small batch is further split into the identifiable instruction of DDR controller by order split cells.
FIFO1 caches the write order (including address) of DDR controller, and FIFO2 caching DDR controller writes data.Arbitrated logic needs
By the judgement of flow control protection location, guarantee the two FIFO be it is safe, otherwise suspend order to present lot and split, etc.
It is continued to execute after having enough allowances to FIFO1 and FIFO2.Handshake logic is realized timing required by DDR controller, will be ordered
It flows and writes data flow and exported from FIFO.
Fair arbitration unit exports a routing table, is stored in FIFO3, uses for route test logic.
It reads converting unit and writes the user clock of converting unit, it can be independently of arbitration unit (and subsequent other lists
Member), the bit wide of user data is also variable.It reads converting unit and writes FIFO inside converting unit (see attached drawing 2 and attached drawing
3) it, is on the one hand used for data cached stream, on the other hand realizes clock domain conversion and data bit width conversion.
Read conversion and write the interface between converting unit and user, be all made of cmd_addr, cmd_len, cmd_req,
These signals of cmd_rdy are shaken hands.Cmd_addr indicates the initial address requested access to；Cmd_len indicates that this is requested access to
Total length；When cmd_req is high, application access is indicated；When cmd_rdy is high, indicate that application is responded.Cmd_req is drawn
Gao Hou needs to be always maintained at high state until cmd_rdy is got higher.It, can be by cmd_ if user still writes application later
Req continues to draw high, if not writing application later, it is (raw in next bat that cmd_rdy is drawn high to need to drag down cmd_req immediately
Effect).Attached drawing 4 reflects the sequential relationship between these signals.T1 moment, application are responded, and next beat persistently sends Shen
Please (cmd_req maintains high level)；At the t1 moment, application is responded, but not continuation application later (cmd_req is dragged down).It shakes hands
Logic writes control stream to DDR controller, is also realized using this interface.
The coffret for writing user data, is shaken hands using data, data_valid, data_rdy.Wherein, data table
Show data to be written, data_valid indicates that the data request of sender is written to recipient, and data_rdy indicates recipient
It is ready, just indicate that data are successfully written to when only data_valid and data_rdy are simultaneously high.The timing of this 3 signals is closed
As shown in Fig. 5, D0~D4 is successively successfully written, and is not repeated for system.Handshake logic writes transmission data to DDR controller,
Also it is realized using this interface.
As a preferred option, to meet attached timing interface shown in fig. 5, the sender (such as user) of data can be adopted
With the pre-read mechanism of FIFO, i.e. data are always ready in advance.When the reading of FIFO enables effective, next reading data from
It is taken in FIFO.It negating to obtain valid with the empty of FIFO, the reading that FIFO is generated while recipient sends out rdy is enabled,
Then next reading data can be ready in next beat.If next beat of data is not ready (FIFO empty), empty is inevitable
For height, corresponding valid is low.Even if data are also invalid at this point, the rdy that recipient provides is height.
As a preferred option, to meet attached timing interface shown in fig. 5, recipient's (for example writing converting unit) can be
Pre- full (almost full) signal of FIFO is negated as rdy.When there is enough spatial caches in FIFO, rdy Gao Daibiao
It can be written into data.Writing for FIFO is enabled, is obtained by valid and rdy phase with operation.In order to improve timing, can to
As a result bat (also bat is played in synchronization to data) is beaten via Flipper-Flop, due to using the pre- full signal of FIFO to do this logic, so not
FIFO really expires after playing bat with worry.For example, pre- whole family limit is arranged to 510 or less and is just pacified very much by the FIFO of 512 depth
Entirely.
It reads conversion and writes converting unit, can all use the thought of batch operation.It is so-called in batches, exactly user is actually subjected to
The data sectional of access becomes N number of batch and submits to fair arbitration unit.For example, there are two user A and B, A be divided into A1,
A2 ..., An sections, B be divided into B1, B2 ..., Bm sections.After arbitration unit is submitted in these applications, what is finally serviced is suitable
Sequence be likely to become A1, B1, A2, B2 ....This method benefit is exactly, what A and B were regarded as being serviced simultaneously on the whole.
If all data for allowing B to wait A have all accessed, it would be possible that B can be because service be responded not in time and is reported an error.
The determination of batch size, and be worthy of careful study.Studies have shown that the continuous of DDR memory or continuously writing (burst behaviour
Make, address is continuous), the access efficiency of DDR can be greatly improved.If read-write staggeredly carries out, even if address is continuously, also to drop
It is inefficient.In terms of this point, length in batches is to be the bigger the better.But if too big, other problems will lead to.1. read user and
The caching expense for writing user is bigger.2., will necessarily be elongated for the service time of some user due in batches excessive, and other users
Therefore ' sky etc. ' efficiency of arbitration may be caused to reduce instead.
As a preferred option, batch size is arranged to the 1/2 or 1/4 of the ROW length of DDR, effect is ideal.
The actual access length of user, the not necessarily integral multiple of batch size, therefore the needs judgement of batch processing logic is currently
No is the last one batch.If it is, the access length of this batch need to be adjusted.For example, reading user applies for 3589 numbers of access
According to the length of batch operation is 256.So, the application of user will be divided into 15 batches and carry out, before 14 batch length be
256, the last one length is 4.
It writes user and applies for after accessing DDR that data flow of writing that may be subsequent temporarily can not be ready.It, can even if ready quickly
The data rate that user can be write can not match the rate of DDR controller.To solve this problem, it writes converting unit and is judging FIFO
In have enough data (be more than or equal to current fragment size) after, then issue present lot to fair arbitration unit write Shen
Please.To avoid moderator that from need to individually waiting this user, the time saved can provide service for other users.
When reading DDR data, at the time of returning back read data at the time of the opposite reading instruction being previously sent, there are larger delays
(generally having tens clock cycle).So for read conversion for, to predict in advance cache user read data FIFO whether
It may overflow.For example, it is assumed that the depth of FIFO is 512, remaining 360 data in current FIFO, (due to the original of delay
Cause) there are also 32 reading data not to return for DDR controller, and reading user at this time still has the application for reading data, batch size is
128.It in this case, may if reading converting unit continues the reading application for submitting this 128 data to DDR controller
Lead to the spilling of FIFO.Because of 360+32+128 > 512, if reading user's access evidence not from FIFO at this time, and subsequent DDR
FIFO will necessarily be written in the data of return, eventually lead to spilling.
As a preferred option, it reads the method that converting unit calculates the non-returned data of DDR controller: recording itself with cnt1
Altogether to the reading data amount check of DDR controller application, how many were returned altogether with cnt2 record DDR controller and reads data,
Cnt1 subtracts the data cnt_diff of cnt2 not returned to as DDR.At this time by data remaining in cnt_diff, FIFO
Amount, maximum number in batches are added, and if it is greater than the depth L of FIFO, reading converting unit cannot continue to submit to DDR moderator at this time
Read application.When actual operation, it is also necessary to guarantee certain allowance, it is safer using L-4 as comparison threshold.
Fair arbitration unit to each reading user and is write user and is numbered.As a preferred option, fair arbitration unit
One user of every response records this number, the priority adjustment for arbitration next time.Attached drawing 6, which describes, arbitrates 4 users
Process.When usr_id is 0, the highest priority of usr1, usr2 takes second place；When usr_id is 1, the priority of usr2 is most
Height, usr3 take second place；……；When usr_id is 3, the highest priority of usr0, usr1 takes second place.Arbitrated logic can only provide simultaneously
The rdy signal of one user indicates that the request of active user passes through, what usr_id was updated to be passed through just now in next cycle
User ID.At the t1 moment, 4 users have application, but usr_id is 0 at this time, then the application of user1 first passes through, followed by
user2,user3,user0.At the t6 moment, although usr_id is that 1, user2 does not apply, therefore the priority of usr3 wants high
In user1, so the application of user3 passes through, usr_id becomes 3 later.
Order split cells further splits the user command that application passes through.Read command stream and write order stream are stored in
In FIFO1, data flow is stored into FIFO2.Flow control protection location is realized to the pre- full status monitoring of FIFO1 and FIFO2, is
Arbitration unit provides Rule of judgment.When FIFO1 is pre- full, either read command or write order requires to wait.Work as FIFO2
When pre- full, write order can suspend, and not influence the dismantling of read command.This effect has benefited from arbitrated logic to reading user and writes user
Parallel arbitration mechanism.As a preferred option, it is 32 that FIFO1 caching depth, which is 64, FIFO2 caching depth, the two FIFO
(resource without Block RAM or M9K etc) is built with logical resource.The pre- whole family limit of FIFO1 is set as the pre- whole family of 60, FIFO2
Limit is set as 28.
The routing table of arbitrated logic output, is made of the reading data amount check of user_id and this user application, is stored in
In FIFO3.When DDR controller returned data, it is counted, the data category currently returned can be learnt in conjunction with routing table
In which user, to realize Route Selection.The update of routing table meets the rule of " first in first out ", is suitble to be realized with FIFO.
To reduce routing delay, and consider timing, FIFO enables pre-read mechanism.The user_id information that FIFO is exported, realization pair
The decoding of each user valid only needs the delay of a timeticks that can meet design here.Writing for FIFO3 is enabled by secondary
Logic is cut out to provide.The reading of FIFO3 is enabled, needs to judge whether the data returned in DDR controller correspond to current user_id most
The latter is read data and is obtained.
The scheme of above-mentioned each unit and use is associated, i.e. the totality side of the DDR read-write moderator of composition this patent
Method, as shown in fig. 7, DDR read-write referee method of the invention mainly comprises the steps that
S1., reading user is subdivided into the reading and writing application of multiple small batches with the reading and writing operation for writing user；
S2. the reading and writing order of small batch is further split into the identifiable instruction of DDR controller, and by reading and writing order
It is stored in FIFO1, data deposit FIFO2 will be write；
S3. it to each reading user and writes user and is numbered, and its priority is decided, and generate routing table storage
In FIFO3；
S4. whether monitoring FIFO1 and FIFO2 unit has enough allowances, if it is not, the order for then suspending present lot is split；
S5. it by reading and writing order and data is write is read from FIFO1 and FIFO2 unit respectively, according to holding for DDR controller
Hand requires to be sent to DDR controller；
S6. routing table being obtained from FIFO3 unit, routing choosing is carried out according to routing table in DDR controller returned data
It selects.
The write operation of data with arbitrary length can once be applied for by writing user, write converting unit by this application be subdivided into it is multiple small
Batch writes application, submits to fair arbitration unit.The data for writing user are first buffered in FIFO, when DDR moderator responds Shen
Please after, by the data forwarding in FIFO to moderator.
The read operation of data with arbitrary length can once be applied for by reading user, this application is subdivided into multiple small by reading converting unit
The reading application of batch, submits to fair arbitration unit.The reading data of routing unit output, are first buffered in FIFO, read user certainly
Data are taken away from FIFO when body is ready.It is impartial by service opportunity to guarantee that multiple read-write users enjoy for fair arbitration unit.
Its another feature is, next effectively to write user by application for adjudication when user's application is read in response, can be write in advance
Data FIFO is write in data importing, further increases the throughput of moderator.Order split cells, by the read write command of small batch,
It is further split into the identifiable instruction of DDR controller.FIFO1 caches the write order (including address) of DDR controller, FIFO2
Caching DDR controller writes data.Arbitrated logic needs the judgement by flow control protection location, guarantees that the two FIFO are safety
, otherwise suspend the order to present lot and split, is continued to execute after FIFO1 and FIFO2 there are enough allowances.It shakes hands and patrols
Volume, it realizes timing required by DDR controller, by command stream and writes data flow from FIFO and export.The output of fair arbitration unit
One routing table, is stored in FIFO3, uses for route test logic.
FIFO1 is mainly used for storing the order of DDR controller；FIFO2, which is mainly used for storing DDR controller, writes data；
FIFO3 is mainly used for storage and reads user's routing table；Flow control protective module is used to detect the pre- full state of FIFO1 and FIFO2, as a result
It is transmitted to fair arbitration module；Routing module control is mainly used for obtaining routing table from FIFO3, by the reading data of DDR controller
Each reading conversion module is transmitted to by User ID；Handshake logic function: by the order of DDR controller and data are write respectively from FIFO1
It is read in FIFO2, being sent to DDR controller according to the requirement of shaking hands of DDR controller, (concrete mode depends on DDR controller
Specification).
Following functions can be achieved in the present invention: multichannel reads and writes user's concurrent access；It writes user and reads user interface to moderator
The conversion of interface, by the application segment processing of user；Realize the data buffer storage management read user and write user；Multi-user is realized
Fair arbitration；The command stream and data flow that the application dismantling for reading and writing user can be performed at DDR controller；DDR flow control protects machine
System；User reads data routing.
To sum up, the single user read-write interface of DDR controller is extended to and the reading of Multi-Client Concurrency Access is supported to connect by the present invention
Mouthful and write interface.It is each to read user and write user to enjoy impartial by service opportunity, that is, avoid one party from monopolizing DDR bus for a long time
The case where.And in Multi-Client Concurrency Access, still ensure that (when batch accesses, efficiency can reach higher DDR service efficiency
80% or more).Further, the user oriented read-write interface of the present invention, relative to the read-write interface of DDR control, operating process
Easier and easy realization.Abundant excavation to DDR room and time resource, not only improves system performance, moreover it is possible to which reduction is designed to
This.
It should be understood that for those of ordinary skills, it can be modified or changed according to the above description,
And all these modifications and variations should all belong to the protection domain of appended claims of the present invention.
Claims (10)
1. a kind of DDR reads and writes moderator characterized by comprising
It is multiple to write converting unit, for the write operation for writing a certain length data of user's application to be subdivided into writing for multiple small batches
Apply and submits to order split cells；
Multiple reading converting units, for the read operation for reading a certain length data of user's application to be subdivided into the reading of multiple small batches
Apply and submits to order split cells；
Order split cells, for being further split into the identifiable instruction of DDR controller for the reading and writing order of small batch, and
Reading and writing order is stored in the first cell fifo, data will be write and be stored in the second cell fifo；
Fair arbitration unit for each reading user and writing user and being numbered, and is decided its priority, and generate
Routing table is stored in third cell fifo；
Flow control protection location, for monitoring the first cell fifo, whether the second cell fifo has enough allowances, if it is not, then suspending
Order split cells splits the order of present lot；
Handshake logic unit, for by reading and writing order and writing data and being read from the first cell fifo and the second cell fifo respectively
Out, DDR controller is sent to according to the requirement of shaking hands of DDR controller；
Route control unit, for obtaining routing table from third cell fifo, in DDR controller returned data, according to routing
Table is routed.
2. DDR according to claim 1 reads and writes moderator, which is characterized in that read converting unit and write converting unit subdivision
When small batch, batch size is arranged to the 1/2 or 1/4 of the ROW length of DDR.
3. DDR according to claim 1 reads and writes moderator, which is characterized in that read converting unit and be also used to calculate DDR control
The non-returned data of device simultaneously based thereon determines whether to continue to submit to read application, specially records itself and have altogether to DDR controller application
Reading data amount check, and record DDR controller returned altogether it is how many read data, the difference of the two is that DDR controller does not return
Data, remaining data volume, maximum number in batches are added in the data that DDR controller is not returned, the second cell fifo, such as
Fruit and depth L greater than the second cell fifo then read converting unit and reading are no longer submitted to apply.
4. DDR according to claim 3 reads and writes moderator, which is characterized in that the data that do not return when DDR controller, the
Remaining data volume, maximum number in batches are added and are greater than L-4 in two cell fifos, then read converting unit and reading is no longer submitted to apply.
5. DDR according to claim 1 reads and writes moderator, which is characterized in that write converting unit and be also used to judge second
Whether enough data space is had in cell fifo, if then continuing that present lot is submitted to write application.
6. DDR according to claim 1 reads and writes moderator, which is characterized in that flow control protection location is specifically used for first
The pre- full state of cell fifo and the second cell fifo is monitored, and when the first cell fifo is pre- full, reading and writing order is required to
It waits；When the second cell fifo is pre- full, write order pause, read command continues to split.
7. a kind of DDR reads and writes referee method, which comprises the following steps:
Multiple reading users and the reading and writing operation for writing user are subdivided into the reading and writing application of multiple small batches；
The reading and writing order of small batch is further split into the identifiable instruction of DDR controller, and by reading and writing order deposit the
One cell fifo will write data and be stored in the second cell fifo；
It to each reading user and writes user and is numbered, and its priority is decided, and generate routing table and be stored in third
In cell fifo；
Monitor the first cell fifo, whether the second cell fifo has enough allowances, if it is not, the order for then suspending present lot is torn open
Point；
It by reading and writing order and writes data and is read from the first cell fifo and the second cell fifo respectively, according to DDR controller
Requirement of shaking hands is sent to DDR controller；
Routing table is obtained from third cell fifo to be routed in DDR controller returned data according to routing table.
8. DDR according to claim 7 reads and writes referee method, which is characterized in that when subdivision small batch, batch size is set
It is set to the 1/2 or 1/4 of the ROW length of DDR.
9. DDR according to claim 7 reads and writes referee method, which is characterized in that calculate the non-returned data of DDR controller simultaneously
It based thereon determines whether to continue to submit to read application, specially record is altogether to the reading data amount check of DDR controller application, and records
DDR controller returned to altogether how many and reads data, and the difference of the two is the data that DDR controller does not return, not by DDR controller
Remaining data volume, maximum number in batches are added in the data of return, the second cell fifo, and if greater than L-4, reading to convert
Unit no longer submits reading to apply, L is the depth of the second cell fifo.
10. DDR according to claim 9 reads and writes referee method, which is characterized in that next when user's application is read in response
It is a that user is effectively write by application for adjudication, data are write in advance imports the second cell fifo.
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