CN112948293A - DDR arbiter and DDR controller chip of multi-user interface - Google Patents

DDR arbiter and DDR controller chip of multi-user interface Download PDF

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Publication number
CN112948293A
CN112948293A CN202110218517.8A CN202110218517A CN112948293A CN 112948293 A CN112948293 A CN 112948293A CN 202110218517 A CN202110218517 A CN 202110218517A CN 112948293 A CN112948293 A CN 112948293A
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ddr
user
module
arbiter
bus interface
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贾学强
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Inspur Electronic Information Industry Co Ltd
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Inspur Electronic Information Industry Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller

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Abstract

The application discloses DDR arbiter and DDR controller chip of multi user interface, this DDR arbiter of multi user interface includes: a user interface parameter module: the system is used for defining the number of the user bus interfaces and the parameters of each user bus interface through system parameters; user bus interface module: the method is used for realizing each user bus interface based on system parameter instantiation; a queue buffer module: the DDR controller is used for caching the access commands sent by the user bus interfaces and sequentially sending the access commands to the DDR controller according to an arbitration result; an arbitration logic module: the arbitration module is used for arbitrating the processing sequence of each access command stored in the queue cache module to generate an arbitration result. The method and the device flexibly define the parameters of each user bus interface through the system parameters, have higher design universality and are beneficial to reducing repeated design among different user bus interfaces. In addition, only a small amount of modification aiming at relevant system parameters is needed to realize new chip design, and the design efficiency is greatly improved.

Description

DDR arbiter and DDR controller chip of multi-user interface
Technical Field
The present disclosure relates to the field of storage technologies, and in particular, to a DDR arbiter for multiple user interfaces and a DDR controller chip.
Background
In order to solve the requirement of multiple users accessing DDR (Double Data Rate), arbitration is usually performed before entering the DDR controller, and the respective access authority and sequence of multiple users are determined by the arbiter, so as to complete the access of multiple user interfaces to DDR one by one.
At present, a common method for accessing multiple user interfaces is that a DDR arbiter writes commands for accessing DDR of each user interface into a cache, and then performs command processing sequence sorting in a targeted manner by combining with the timing characteristics of DDR reading and writing, and sequentially completes DDR access according to the sorting result. However, the method is not highly versatile in design, requires repeated labor for different user interfaces, and is inefficient in design.
In view of the above, it is an important need for those skilled in the art to provide a solution to the above technical problems.
Disclosure of Invention
The DDR arbiter and the DDR controller chip of the multi-user interface are provided, so that the design universality and efficiency of DDR are effectively improved.
To solve the above technical problem, in one aspect, the present application discloses a DDR arbiter for multiple user interfaces, including:
a user interface parameter module: the system is used for defining the number of the user bus interfaces and the parameters of each user bus interface through system parameters;
user bus interface module: the system is used for instantiating each user bus interface based on the system parameters;
a queue buffer module: the DDR controller is used for caching the access commands sent by the user bus interfaces and sequentially sending the access commands to the DDR controller according to an arbitration result;
an arbitration logic module: the arbitration module is used for arbitrating the processing sequence of each access command stored in the queue cache module to generate the arbitration result.
Optionally, the parameter of each user bus interface includes a relationship between a user clock domain and a DDR controller clock domain;
when the user bus interface module generates the user bus interface with the asynchronous user clock domain and the asynchronous DDR controller clock domain, the asynchronous processing from the user clock domain to the DDR controller clock domain is realized based on the asynchronous processing circuit.
Optionally, the user interface parameter module defines the system parameters in a vh file; and the user bus interface module instantiates each user bus interface by calling the vh file.
Optionally, the queue buffer module includes a command buffer queue and a data buffer queue; the command buffer queue is used for buffering each access command, and the data buffer queue is used for storing data requested to be written or read by each access command.
Optionally, the queue buffer module is further configured to:
and receiving return data of the DDR controller aiming at the read command, and sending the return data to the corresponding user bus interface.
Optionally, the arbitration logic module is specifically configured to, in arbitration:
and setting priority and an expiration time limit for each access command in the queue cache module so as to arbitrate each access command based on the priority and the expiration time limit.
Optionally, the arbitration policy comprises:
a high priority and a low timeout period are set for access commands of a user bus interface associated with system operation.
Optionally, the arbitration policy comprises:
and (3) decomposing the access command of the image and video user bus interface into a plurality of access commands, and setting each access length as one DDR line.
Optionally, each user bus interface is implemented based on an AXI bus.
In another aspect, the present application further discloses a DDR controller chip, which includes a DDR controller and a DDR arbiter of any one of the multi-user interfaces described above.
The DDR arbiter and the DDR controller chip of the multi-user interface provided by the application have the following beneficial effects: the method and the device flexibly define the parameters of each user bus interface through the system parameters, have higher design universality and are beneficial to reducing repeated design among different user bus interfaces. In addition, only a small amount of modification aiming at relevant system parameters is needed to realize new chip design, and the design efficiency is greatly improved.
Drawings
In order to more clearly illustrate the technical solutions in the prior art and the embodiments of the present application, the drawings that are needed to be used in the description of the prior art and the embodiments of the present application will be briefly described below. Of course, the following description of the drawings related to the embodiments of the present application is only a part of the embodiments of the present application, and it will be obvious to those skilled in the art that other drawings can be obtained from the provided drawings without any creative effort, and the obtained other drawings also belong to the protection scope of the present application.
Fig. 1 is a schematic structural diagram of a DDR arbiter for multiple user interfaces according to an embodiment of the present application;
FIG. 2 is a flow chart of arbitration of the arbitration logic module for the read command according to the embodiment of the present application;
fig. 3 is a flowchart illustrating an arbitration logic module arbitrating for a write command according to an embodiment of the present application.
Detailed Description
The core of the application is to provide a DDR arbiter and a DDR controller chip of a multi-user interface so as to effectively improve the design universality and efficiency of DDR.
In order to more clearly and completely describe the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, an embodiment of the present application discloses a DDR arbiter for multiple user interfaces, which mainly includes:
user interface parameter module 101: the system is used for defining the number of the user bus interfaces and the parameters of each user bus interface through system parameters;
user bus interface module 102: the system is used for instantiating each user bus interface based on the system parameters;
the queue buffer module 103: the DDR controller is used for caching the access commands sent by the user bus interfaces and sequentially sending the access commands to the DDR controller according to an arbitration result;
arbitration logic 104: for arbitrating the processing sequence of each access command stored in the queue cache module 103 to generate the arbitration result.
In particular, the chip will generate a large amount of cache data including pictures, video, system cache, etc. while in operation. Such data generally employs DDR as a storage medium. In these data transmissions of different nature and for different purposes, each data transmission may represent a user. In practical applications, it is often required to complete the access to the memory by a plurality of different users in the same chip.
In order to solve the requirement of multiple users for accessing the DDR, arbitration is usually performed before entering the DDR controller, and the respective access authority and sequence of multiple users are determined by the arbiter, so as to complete the access of the multiple user interfaces to the DDR one by one.
The DDR arbiter for a multi-user interface provided by the present application specifically includes four modules: a user interface parameter module 101, a user bus interface module 102, a queue buffer module 103, and an arbitration logic module 104. The user interface parameter module 101 flexibly defines the number of the user bus interfaces and the parameters of each user bus interface through the system parameters, so that the user bus interface module 102 can instantiate each user bus interface correspondingly.
The parameters of each user bus interface further specifically include the relationship between the user clock domain of the interface and the clock domain of the DDR controller: synchronous or asynchronous.
When the user bus interface module 102 instantiates and generates a user bus interface in which the user clock domain is asynchronous with the DDR controller clock domain, the asynchronous processing from the user clock domain to the DDR controller clock domain is specifically realized based on the asynchronous processing circuit. And for the user bus interface with the synchronous user clock domain and the DDR controller clock domain, an asynchronous processing circuit is not needed.
In one embodiment, the user interface parameter module 101 may specifically define the system parameter in a vh file, so that the user bus interface module 102 instantiates each user bus interface by calling the vh file.
Specifically, the vh file may be included in the design by the' include instruction. For example, the vh file may be defined as user _ intf _ definitions.
`include"user_intf_defines.vh"。
Therefore, parameters in the vh file can be flexibly modified according to different design targets, so that the design is quickly completed, and the development time is saved.
The queue buffer module 103 may specifically adopt a FIFO (First Input First Output, First in First out) to store the access command sent by each user bus interface, including parameters such as a corresponding access address, bit width, length, and the like, and send the access command to the arbitration logic module 104 in sequence. After receiving the arbitration result sent by the arbitration logic module 104, the access commands can be sent to the DDR controller one by one in sequence for processing.
If the access command is a write request, the content sent to the DDR controller specifically includes a corresponding write command and write data. If the access command is a read request, the content sent to the DDR controller specifically includes a corresponding read command. And the queue buffer module 103 is further configured to: and receiving return data of the DDR controller aiming at the read command, and sending the return data to the corresponding user bus interface.
And after receiving the arbitration result, the queue cache module 103 may feed back the learned read-write task process to the user, thereby completing communication with the user.
Therefore, the DDR arbiter of the multi-user interface disclosed in the embodiment of the present application flexibly defines the parameters of each user bus interface through the system parameters, has higher design versatility, and is helpful for reducing the repeated design among different user bus interfaces. In addition, only a small amount of modification aiming at relevant system parameters is needed to realize new chip design, and the design efficiency is greatly improved.
As a specific embodiment, based on the above, the DDR arbiter of the multi-user interface shown in fig. 1, the queue buffer module 103 includes a command buffer queue and a data buffer queue; the command buffer queue is used for buffering each access command, and the data buffer queue is used for storing data requested to be written or read by each access command.
As a specific embodiment, on the basis of the above, the DDR arbiter of the multi-user interface shown in fig. 1, each user bus interface is implemented based on the AXI bus.
As a specific embodiment, on the basis of the above content, the arbitration logic module 104 is specifically configured to:
priority and an expiry time limit are set for each access command in the queue cache module 103, so that each access command is arbitrated based on the priority and the expiry time limit.
As a specific embodiment, on the basis of the above content, the DDR arbiter of the multi-user interface disclosed in the embodiment of the present application includes: a high priority and a low timeout period are set for access commands of a user bus interface associated with system operation.
In one embodiment, the arbitration logic 104, in performing arbitration, may specifically refer to fig. 2, and mainly includes:
s201: a new access command request is received in a read operation.
S202: judging whether the access command is overtime; if not, the process proceeds to S203, and if so, the process proceeds to step 204.
S203: judging whether the access command and the currently executed access command are in the same line access; if not, the process goes to S205; if yes, the process proceeds to S206.
S204: judging whether the access command is a read command; if yes, go to S205; if not, entering a write command arbitration process.
S205: judging whether the access command has higher priority; if yes, entering S206; if not, the process proceeds to S207.
S206: and giving DDR access right to the access command.
S207: and giving a polling wait authority to the access command so that the access command acquires DDR access authority in a first-in first-out order through polling arbitration.
Specifically, in the process, the process is mainly divided into 5 levels:
1. read-write arbitration, reducing read-write switching; 2. performing overtime arbitration, wherein if the overtime command obtains the highest priority, the DDR access authority is directly obtained; 3. arbitrating the access authority of the same row, and if the access command and the currently executed read operation are the access operation of the same row, acquiring DDR access authority; 4. arbitrating the high-priority access authority, and when other conditions are the same, obtaining the DDR access authority by the user with the higher-priority access authority; 5. and polling arbitration, namely entering a polling waiting command, and finally obtaining the DDR access authority according to the entering sequence.
In another embodiment, the arbitration logic 104, during the arbitration process, may refer to fig. 3 specifically, and mainly includes:
s301: a new access command request is received in a write operation.
S302: judging whether the access command is overtime; if not, the process proceeds to S303, and if so, the process proceeds to 304.
S303: judging whether the access command and the currently executed access command are in the same line access; if not, the process goes to S305; if yes, the process proceeds to S306.
S304: judging whether the access command is a write command; if yes, go to S305; if not, entering a read command arbitration process.
S305: judging whether the access command has higher priority; if yes, entering S306; if not, the process proceeds to S307.
S306: and giving DDR access right to the access command.
S307: and giving a polling wait authority to the access command so that the access command acquires DDR access authority in a first-in first-out order through polling arbitration.
As a specific embodiment, on the basis of the above content, the DDR arbiter of the multi-user interface disclosed in the embodiment of the present application includes: and (3) decomposing the access command of the image and video user bus interface into a plurality of access commands, and setting each access length as one DDR line.
Specifically, the arbitration policy adopted in this embodiment, on one hand, can take into account the characteristics of the DDR device, reduce the time from activation (Active) to Precharge (Precharge), reduce the read/write command switching, and can use tCCD _ S (the delay time between column addresses in different Bank groups) to replace tCCD _ L (the delay time between column addresses in the same Bank Group).
On the other hand, the present embodiment can design multiple arbitration strategies according to different properties of different users.
For example, the burst access data size of the user bus interfaces such as images and videos is large, and the access addresses are continuous, so that the embodiment can disassemble the user bus interfaces into a plurality of access commands, so as to avoid the problems of excessive access delay and abnormal functions of other users caused by excessively long occupied bandwidth time. And each access length can be set to be one row of DDR, so that not only is the bandwidth occupied by other users for a long time considered, but also row switching is reduced, and the DDR access efficiency can be further improved.
And for a user bus interface operated by the shoulder system, the burst access data volume is small, the access commands are more, and the access delay is sensitive. The present embodiment can therefore give higher priority and smaller timeout periods for such a user bus interface.
Therefore, by the aid of the set of reasonable and efficient arbitration strategies, the targeted strategies can be worked out according to different user characteristics, and DDR access efficiency under the condition of multiple users is effectively improved.
The application also discloses a DDR controller chip, which comprises the DDR controller and the DDR arbiter of any one of the multi-user interfaces.
For the detailed content of the DDR controller chip, reference may be made to the detailed description of the DDR arbiter related to the multi-user interface, and details thereof are not repeated here.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the equipment disclosed by the embodiment, the description is relatively simple because the equipment corresponds to the method disclosed by the embodiment, and the relevant parts can be referred to the method part for description.
It is further noted that, throughout this document, relational terms such as "first" and "second" are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Furthermore, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The technical solutions provided by the present application are described in detail above. The principles and embodiments of the present application are explained herein using specific examples, which are provided only to help understand the method and the core idea of the present application. It should be noted that, for those skilled in the art, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall into the protection scope of the present application.

Claims (10)

1. A DDR arbiter for a multi-user interface, comprising:
a user interface parameter module: the system is used for defining the number of the user bus interfaces and the parameters of each user bus interface through system parameters;
user bus interface module: the system is used for instantiating each user bus interface based on the system parameters;
a queue buffer module: the DDR controller is used for caching the access commands sent by the user bus interfaces and sequentially sending the access commands to the DDR controller according to an arbitration result;
an arbitration logic module: the arbitration module is used for arbitrating the processing sequence of each access command stored in the queue cache module to generate the arbitration result.
2. The DDR arbiter of claim 1, wherein the parameters of each customer bus interface comprise a relationship between a customer clock domain and a DDR controller clock domain;
when the user bus interface module generates the user bus interface with the asynchronous user clock domain and the asynchronous DDR controller clock domain, the asynchronous processing from the user clock domain to the DDR controller clock domain is realized based on the asynchronous processing circuit.
3. The DDR arbiter of claim 1, wherein the user interface parameter module defines the system parameter in a.vh file; and the user bus interface module instantiates each user bus interface by calling the vh file.
4. The DDR arbiter of claim 1, wherein the queue cache module comprises a command cache queue and a data cache queue; the command buffer queue is used for buffering each access command, and the data buffer queue is used for storing data requested to be written or read by each access command.
5. The DDR arbiter of claim 1, wherein the queue cache module is further configured to:
and receiving return data of the DDR controller aiming at the read command, and sending the return data to the corresponding user bus interface.
6. The DDR arbiter of claim 1, wherein the arbitration logic is further configured to, when arbitrating:
and setting priority and an expiration time limit for each access command in the queue cache module so as to arbitrate each access command based on the priority and the expiration time limit.
7. The DDR arbiter of claim 6, wherein the arbitration policy comprises:
a high priority and a low timeout period are set for access commands of a user bus interface associated with system operation.
8. The DDR arbiter of claim 6, wherein the arbitration policy comprises:
and (3) decomposing the access command of the image and video user bus interface into a plurality of access commands, and setting each access length as one DDR line.
9. The DDR arbiter of any one of claims 1 to 8, wherein each user bus interface is implemented based on an AXI bus.
10. A DDR controller chip comprising a DDR controller and a DDR arbiter for a multi-user interface as claimed in any one of claims 1 to 9.
CN202110218517.8A 2021-02-26 2021-02-26 DDR arbiter and DDR controller chip of multi-user interface Pending CN112948293A (en)

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CN113849867A (en) * 2021-08-31 2021-12-28 浪潮电子信息产业股份有限公司 Encryption chip
CN114281722A (en) * 2021-12-29 2022-04-05 合肥市芯海电子科技有限公司 Embedded control circuit with double bus interfaces, chip and electronic equipment
CN114741341A (en) * 2022-03-01 2022-07-12 西安电子科技大学 Method, system and storage medium for realizing Crossbar structure arbitration
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