CN114281722A

CN114281722A - Embedded control circuit with double bus interfaces, chip and electronic equipment

Info

Publication number: CN114281722A
Application number: CN202111647232.2A
Authority: CN
Inventors: 王世好
Original assignee: Hefei Chipsea Electronics Technology Co Ltd
Current assignee: Hefei Chipsea Electronics Technology Co Ltd
Priority date: 2021-12-29
Filing date: 2021-12-29
Publication date: 2022-04-05
Anticipated expiration: 2041-12-29
Also published as: CN114281722B; WO2023124942A1

Abstract

The utility model provides an embedded control circuit, chip and electronic equipment of two bus interfaces, embedded control circuit includes: one or more peripheral modules; the processor is connected with one or more peripheral modules; a first bus interface circuit connected to one or more peripheral modules; the second bus interface circuit is connected with one or more peripheral modules; a bus interface selection circuit configured to communicate with the host processor and operatively connect either the first bus interface circuit or the second bus interface circuit to the host processor. With the present disclosure, peripherals may be accessed through at least two bus interfaces.

Description

Embedded control circuit with double bus interfaces, chip and electronic equipment

Technical Field

The present disclosure relates to the field of electronic circuit technologies, and in particular, to an embedded control circuit with dual bus interfaces, a chip, and an electronic device.

Background

In electronic devices such as personal computers, an Embedded Controller (EC) manages at least a part of peripheral devices (peripheral devices). The processor of the electronic device (simply referred to as the host processor) and the processor of the embedded controller need to access these peripherals. In the related art, no effective solution is provided at present how to access the peripheral more efficiently, conveniently and reliably by the host processor and the processor of the embedded controller.

Disclosure of Invention

In view of this, the embodiments of the present disclosure provide an embedded control circuit with dual bus interfaces, a chip and an electronic device, so as to implement peripheral access.

According to an aspect of the present disclosure, there is provided an embedded control circuit including: one or more peripheral modules; the processor is connected with one or more peripheral modules; a first bus interface circuit connected to one or more peripheral modules; the second bus interface circuit is connected with one or more peripheral modules; a bus interface selection circuit configured to communicate with the host processor and operatively connect either the first bus interface circuit or the second bus interface circuit to the host processor.

In some embodiments, the bus interface selection circuit is configured to connect the first bus interface circuit or the second bus interface circuit to the host processor based on the initialization configuration.

In some embodiments, one or more peripheral modules, comprise: one or more first peripheral modules, each of the one or more first peripheral modules including a first interface and a second interface; wherein, embedded control circuit still includes: the first bus is connected among the first interface of each first peripheral module, the first bus interface circuit and the second bus interface circuit; the second bus is connected between the second interface of each first peripheral module and the processor; wherein the first bus interface circuit and the second bus interface circuit are configured to access one or more first peripheral modules via a first bus; a processor configured to access one or more first peripheral modules over a second bus.

In some embodiments, at least one first peripheral module, comprises: an arbitration logic circuit configured to: disconnecting the second interface of the first peripheral module from the second bus when the first peripheral module is accessed by the host processor; and/or disconnecting the first interface of the first peripheral module from the first bus when the first peripheral module is accessed by the processor.

In some embodiments, the arbitration logic is further configured to: when the first peripheral module is released by the host processor, connecting a second interface of the first peripheral module with a second bus; and/or connecting the first interface of the first peripheral module with the second bus when the first peripheral module is released by the processor.

In some embodiments, the one or more peripheral modules comprise: one or more second peripheral modules; wherein, embedded control circuit still includes: circuitry; the third bus is connected between the one or more second peripheral modules and the circuit system, and is connected between the one or more second peripheral modules and the processor; wherein the circuitry is configured to communicate with the host processor via the first bus interface circuit or the second bus interface circuit, to access the one or more second peripheral modules via the third bus based on a command of the host processor; a processor configured to access one or more second peripheral modules through a third bus.

In some embodiments, the first bus interface circuit and/or the second bus interface circuit is configured to: determining whether the host processor accesses the first peripheral module or the second peripheral module based on the accessed target address; in the event that the host processor accesses one or more first peripheral modules, accessing the one or more first peripheral modules over the first bus; in the event that the host processor accesses one or more second peripheral modules, the access commands of the host processor are forwarded to the circuitry.

In some embodiments, the circuitry is configured to: determining whether the host processor accesses one or more second peripheral modules based on the accessed target address; in the case where the host processor accesses the one or more second peripheral modules, the one or more second peripheral modules are accessed through the third bus based on a command of the host processor.

In some embodiments, the embedded control circuit further comprises: and the fourth bus is connected between the processor and the circuit system.

In some embodiments, the processor is configured to: sending interrupt information of one or more second peripheral modules to the circuit system through a fourth bus; circuitry is configured to: and sending the interrupt information to the host processor through the first bus interface circuit or the second bus interface circuit.

In some embodiments, the circuitry is configured to: one or more second peripheral modules are accessed based on the preconfigured permissions.

In some embodiments, the embedded control circuit further comprises: an interrupt signal line connected between the processor and the circuitry; circuitry is configured to: in the case where a register of the second peripheral module, which is accessed by the host processor, is configured to be access-disabled, an interrupt signal is transmitted to the processor through the interrupt signal line.

In some embodiments, at least one first peripheral module configured to: determining whether the host processor accesses a first peripheral module based on the accessed target address; in the case where the host processor accesses the first peripheral module, responding to the host processor's access.

According to another aspect of the present disclosure, a chip is provided, which includes the embedded control circuit of the embodiments of the present disclosure.

According to still another aspect of the present disclosure, there is provided an electronic device including: an embedded control circuit of an embodiment of the disclosure or a chip of an embodiment of the disclosure.

According to one or more technical schemes provided by the embodiment of the disclosure, the embedded control circuit comprises one or more peripheral modules, and a processor connected with the one or more peripheral modules; the first bus interface circuit and the second bus interface circuit are connected with one or more peripheral modules; the bus interface selection circuit may be in communication with the host processor and may be operable to connect either the first bus interface circuit or the second bus interface circuit to the host processor. The peripheral module is accessible via at least two bus interfaces.

Drawings

Further details, features and advantages of the disclosure are disclosed in the following description of exemplary embodiments, taken in conjunction with the accompanying drawings, in which:

FIG. 1 shows a schematic block diagram of a shared interface based embedded control circuit of an exemplary embodiment of the present disclosure;

FIG. 2 shows a schematic block diagram of a peripheral module 130 of an exemplary embodiment of the present disclosure;

fig. 3 shows a schematic block diagram of an embedded control circuit based on an eSPI bus and a shared interface according to an exemplary embodiment of the present disclosure;

FIG. 4 shows a schematic block diagram of an embedded control circuit for direct memory access in an exemplary embodiment of the present disclosure;

FIG. 5 illustrates a flow chart of a peripheral access method of direct memory access of an exemplary embodiment of the present disclosure;

FIG. 6 shows a schematic block diagram of circuitry 440 of an exemplary embodiment of the present disclosure;

fig. 7 shows a schematic block diagram of an embedded control circuit using an eSPI bus and direct memory access of an exemplary embodiment of the present disclosure;

fig. 8 shows a schematic block diagram of circuitry 740 of an exemplary embodiment of the present disclosure;

FIG. 9 shows a schematic block diagram of an embedded control circuit based on direct memory access and shared interfaces of an exemplary embodiment of the present disclosure;

FIG. 10 is a flowchart illustrating a peripheral access method based on direct memory access and a shared interface according to an exemplary embodiment of the present disclosure;

fig. 11 shows a schematic block diagram of a direct memory access and shared interface based embedded control circuit using an eSPI bus of an exemplary embodiment of the present disclosure;

FIG. 12 shows a schematic block diagram of an embedded control circuit of a dual bus interface of an exemplary embodiment of the present disclosure;

fig. 13 shows a schematic block diagram of an embedded control circuit of an LPC-eSPI dual bus interface of an exemplary embodiment of the present disclosure.

Detailed Description

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure are shown in the drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the disclosure are for illustration purposes only and are not intended to limit the scope of the disclosure.

It should be understood that the various steps recited in the method embodiments of the present disclosure may be performed in a different order, and/or performed in parallel. Moreover, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the present disclosure is not limited in this respect.

The term "include" and variations thereof as used herein are open-ended, i.e., "including but not limited to". The term "based on" is "based, at least in part, on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Relevant definitions for other terms will be given in the following description. It should be noted that the terms "first", "second", and the like in the present disclosure are only used for distinguishing different devices, modules or units, and are not used for limiting the order or interdependence relationship of the functions performed by the devices, modules or units.

It is noted that references to "a", "an", and "the" modifications in this disclosure are intended to be illustrative rather than limiting, and that those skilled in the art will recognize that "one or more" may be used unless the context clearly dictates otherwise.

The embodiment of the disclosure relates to the improvement of the technical scheme of integrating a peripheral module in an embedded controller and accessing the peripheral module by a host processor and a processor of the embedded controller.

Some embodiments of the present disclosure relate to an embedded control circuit based on a shared interface, in which a peripheral module is integrated, the peripheral module includes two interfaces, a host processor accesses the peripheral module through one interface of a bus interface circuit and the peripheral module, and a processor of the embedded control circuit accesses the peripheral module through the other interface. In some embodiments, at least one peripheral module includes an interface unit for connecting peripherals. In some embodiments, the interface unit corresponding to the at least one peripheral module for connecting a peripheral is connected to the processor independently of the peripheral module.

Some embodiments of the present disclosure relate to an embedded control circuit for direct memory access, in which a peripheral module is integrated, a circuit system is disposed in the embedded control circuit, a host processor accesses the peripheral module through a bus interface circuit and the circuit system, and a processor of the embedded control circuit can access the peripheral module through a line between the processor and the peripheral module. In these embodiments, when the peripheral module is integrated in the embedded control circuit, the address of the peripheral module is opened to the host processor, and the host processor accesses the peripheral module by using the address of the peripheral module, so that the bus interface circuit is not modified, and the peripheral module is conveniently integrated in the embedded control circuit.

Some embodiments of the present disclosure relate to an embedded control circuit for shared interface and direct memory access, in which a peripheral module is integrated. Some of the peripheral modules are peripheral modules including two interfaces, the host processor can access the peripheral modules through one of the interfaces of the peripheral modules through the bus interface circuit, and the processor of the embedded control circuit can access the peripheral modules through the other interface of the peripheral modules. The other peripheral modules are peripheral modules which are accessed by a direct memory through a circuit system, the host processor accesses the peripheral modules through the bus interface circuit and the circuit system, and the processor of the embedded control circuit can access the peripheral modules.

Some embodiments of the present disclosure relate to bus interface circuits for embedded control circuits, which may include interface circuits for at least two bus protocols, with a bus interface selection circuit selecting one of the interface circuits for at least two bus protocols to communicate with a host processor.

It should be understood that references to "first bus", "second bus", "third bus", and "fourth bus", etc. in this disclosure, in some embodiments, merely distinguish transmission lines between different devices, which may employ different buses, or may share at least some of the lines and interfaces by way of a bus matrix, etc. The present disclosure is not limited thereto.

In the following description of the present disclosure, embodiments of the present disclosure may be arbitrarily combined. Exemplary embodiments of the present disclosure are described below.

The embodiment of the disclosure provides an embedded control circuit based on a shared interface.

Fig. 1 shows a schematic block diagram of an embedded control circuit based on a shared interface according to an exemplary embodiment of the disclosure, and as shown in fig. 1, the embedded control circuit 100 includes: a bus interface circuit 110 for communicating with a host processor, a processor 120, a peripheral module 130, a first bus 140, and a second bus 150. A plurality of peripheral modules 130, designated as peripheral modules 130-1 through 130-n, are shown in FIG. 1. The first bus 140 is connected between the first interface of the peripheral modules 130 and the bus interface circuit 110, and the second bus 150 is connected between the second interface of each peripheral module 130 and the processor 120. The bus interface circuit 110 accesses the peripheral module 130 through the first bus 140. The processor 120 accesses the peripheral module 130 through the second bus 150. Because the host processor and the processor 120 respectively use different buses, the access to the peripheral modules is not interfered with each other, the bus bandwidth can be increased, and the access speed can be increased. For example, the host processor may access the peripheral module 130-1 via the first bus 140, while the processor 120 may access the peripheral module 130-n via the second bus 150.

In this embodiment, various types of bus interfaces may be used to communicate with the host processor, including but not limited to a Low Pin Count (LPC) bus, a Serial Peripheral Interface (SPI) bus, an Enhanced SPI bus, and the like. The bus interface circuit 110 includes a bus interface or a plurality of bus interfaces. The bus interface circuit 110 is operable to use one of a plurality of bus interfaces for communication. This embodiment is not limited to this. In this embodiment, the bus interface circuit 110 and the host processor may communicate according to a bus protocol. As an example, an eSPI bus may be used between embedded control circuit 100 and a host processor, embedded control circuit 100 being a slave device in the eSPI bus (eSPIslave), the host processor being a master device in the eSPI bus (espimamaster), and bus interface 110 being an eSPI slave. This embodiment is not limited to this.

In the present embodiment, the first Bus 140 may include any Bus compatible with the Bus Interface circuit 110, and examples of the first Bus 140 may include a local Bus (localbus), an Advanced eXtensible Interface (AXI) Bus, an Advanced Peripheral Bus (APB), and the like, which is not limited in this embodiment.

In this embodiment, the second Bus 150 may include any Bus compatible with the processor 120, and examples of the second Bus 150 may include a local Bus (localbus), an Advanced eXtensible Interface (AXI) Bus, an Advanced Peripheral Bus (APB), and the like, which is not limited in this embodiment.

In this implementation, the I/O interface corresponding to each peripheral module 130 is defined on the bus interface circuit 110. In this disclosure, an interface may also be referred to as a port, collectively referred to as an interface in the description of this disclosure.

In the present embodiment, the peripheral module 130 may include a part circuit module of various peripheral devices, examples of which include a mouse, a keyboard, a USB, a PD/TYPE-C, a breathing light, an atmosphere light, and the like. This embodiment is not limited to this.

In some embodiments, the peripheral module 130 may include an interface unit for connecting peripherals. As an embodiment, the peripheral module 130 including an interface unit for connecting a peripheral acquires data from the peripheral connected to the interface unit thereof and/or provides data to the peripheral connected thereto, and communication between the peripheral module 130 and the host processor may not pass through the processor 120. In the present embodiment, the processor 120 may read and/or write to the peripheral module 130 through the second bus 150, for example, configure parameters of the peripheral module 130. The host processor may read and/or write to the peripheral module 130 through the bus interface circuit 110 and the first bus 140, for example, write data to the peripheral module 130 to be transmitted through a peripheral connected thereto, or read data from a peripheral connected thereto from the peripheral module 130, or configure parameters of the peripheral module 130, or the like. Examples of the peripheral module 130 including an interface unit for connecting a peripheral include a serial interface module (e.g., a UART serial port, etc.) including an interface unit for connecting a serial communication physical interface (e.g., a UART connector). The serial interface module and the serial communication physical interface can adopt serial communication interface standards such as RS-232C, RS-422, RS-423, RS-485 and the like.

In some embodiments, the peripheral module 130 is connected to the processor 120 independently of the peripheral module 130, and the corresponding interface unit for connecting peripherals is connected to the processor. The processor 120 may provide data from the peripheral module 130 to the interface unit corresponding to the peripheral module 130, or provide data from the interface unit to the peripheral module 130 corresponding to the interface unit. The host processor can provide data to the peripheral module 130, and the data provided by the host processor to the peripheral module 130 can be provided to the interface unit corresponding to the peripheral module 130 through the processor 120; the processor 120 may provide the data of the interface unit to the peripheral module 130 corresponding to the interface unit, and the host processor may obtain the data from the peripheral module 130. In general, the processor 120 may be connected to an interface unit independent from the peripheral module 130 through a fast bus or the like. Examples of the interface unit for connecting peripherals, which is connected to the processor 120 independently of the peripheral module 130, include a keyboard interface unit. As an example, a keyboard controller located on the keyboard detects the pressing and releasing of the keys, sends a keyboard code to the keyboard interface unit, the processor 120 detects that the keyboard interface unit receives the keyboard code, and the processor 120 provides the keyboard code to the peripheral module 130 corresponding to the keyboard interface unit.

In some embodiments, a portion of the peripheral modules 130 includes an interface unit for connecting peripherals, the portion of the peripheral modules 130 obtaining data from peripherals connected to the interface unit and/or providing data to peripherals connected thereto, communication between the peripheral modules 130 and the host processor may not pass through the processor 120. The interface unit for connecting peripheral devices corresponding to part of the peripheral modules 130 is connected to the processor 120 independently of the peripheral modules 130. The processor 120 may provide data from the peripheral module 130 to the interface unit corresponding to the peripheral module 130, or provide data from the interface unit to the peripheral module 130 corresponding to the interface unit. The host processor can provide data to the peripheral module 130, and the data provided by the host processor to the peripheral module 130 can be provided to the interface unit corresponding to the peripheral module 130 through the processor 120; the processor 120 may provide the data of the interface unit to the peripheral module 130 corresponding to the interface unit, and the host processor may obtain the data from the peripheral module 130.

As an example, the peripheral module 130 includes a keyboard module and a serial interface module, wherein an interface unit (referred to as a keyboard interface unit) of the keyboard module is independent from the keyboard module, the keyboard interface unit is connected with the processor 120, and the serial interface module includes an interface unit for connecting a serial communication physical interface.

In this example, the serial interface module receives data sent by the host processor through the bus interface circuit 110, and sends the data through the serial communication physical interface; the data is received by the serial communication physical interface, the data received by the serial communication physical interface of the serial interface module is sent to the host processor through the bus interface circuit 110, and the data transmission is not processed by the processor 120. The serial interface module may be configured by the processor 120 via the second bus 150, or alternatively, the host processor may configure the serial interface module via the bus interface circuit 110 and the first bus 140.

In this example, processor 120 may provide data from the keyboard module to the keyboard interface unit or from the keyboard interface unit to the keyboard module. The host processor may provide data to the keyboard module, and the data provided by the host processor to the keyboard module may be provided to the keyboard interface unit via the processor 120; the processor 120 may provide the keyboard interface unit data to the keyboard module 130, and the host processor may retrieve the data from the keyboard module 130. The keyboard code is retrieved from the keyboard interface unit, for example, by the processor 120, provided to the keyboard module, and the host processor reads the keyboard code from the keyboard module via the bus interface circuit 110.

In some embodiments, the bus interface circuit 110 is configured to receive a write command from the host processor and write data to a register of the peripheral module 130 corresponding to the write command via the first bus 140. In some embodiments, the bus interface circuit 110 is configured to receive a read command from the host processor and read data from a register of the peripheral module 130 corresponding to the read command via the first bus 140.

In some embodiments, the processor 120 is configured to read data from registers of the peripheral module 130 over the second bus 150. In some embodiments, the processor 120 is configured to write data to the registers of the peripheral module 130 through the second bus 150.

In some embodiments, the peripheral modules 130 communicate with the peripherals via the processor 120, the processor 120 being configured to receive inputs from the peripherals and to write data to registers of the peripheral module 130 corresponding to the peripherals via the second bus 150 based on the received inputs.

In some embodiments, as shown in FIG. 2, peripheral module 130 may include one or more registers 131, the one or more registers 131 being read and/or written to by processor 120 (via second bus 150) and the host processor (via bus interface circuit 110 and first bus 140). The processor 120 reads and/or writes one or more registers 131 of the peripheral module 130 through the second interface of the peripheral module 130. The bus interface circuit 110 reads and/or writes one or more registers 131 of the peripheral module 130 through a first interface of the peripheral module 130. The peripheral module 130 may set one or more registers 131 based on its functionality, examples of registers 131 of the peripheral module 130 may include: a configuration register, a status register, a control register, a read data register, or a write data register, etc.

In some embodiments, as shown in FIG. 2, the peripheral module 130 may include one or more functional circuits 132 that, in conjunction with the peripherals, implement the functions of the peripherals. Examples of the peripheral module 130 include a serial interface module for connecting a serial communication physical interface, and a functional circuit of the serial interface module includes a level shift circuit that performs level shift based on a serial communication interface standard. Another example of the peripheral module 130 includes a light unit control module for connecting one or more light units (e.g., light emitting diodes), and the functional circuit of the light unit control module may include a controller for controlling the one or more light units to emit light.

In some embodiments, as shown in fig. 2, the peripheral module 130 includes: an arbitration logic 133 is coupled to the first bus 140 and the second bus 150. The arbitration logic 133 is used to arbitrate access requests from the processor 120 and the host processor (via the bus interface circuit 110).

In one embodiment, as shown in fig. 2, the arbitration logic 133 is configured to be coupled to the arbitration control register 134 to provide an arbitration policy to the arbitration logic 133. In one embodiment, the processor 120 is further coupled to the arbitration control register 134 to write the arbitration policy to the arbitration control register 134. The arbitration control register 134 is located outside the peripheral module 130 as an example, and the embodiment is not limited thereto.

In one embodiment, the arbitration logic 133 disconnects the second interface of the peripheral module 130 from the second bus 150 when the peripheral module 130 is accessed by the host processor. In one embodiment, the arbitration logic 133 disconnects the first interface of the peripheral module 130 from the first bus 140 when the peripheral module 130 is accessed by the processor 120. Arbitration is avoided for each host processor and processor 120 access, and the efficiency and potential functional problems of a single bus due to complex arbitration logic are avoided.

In one embodiment, the arbitration logic 133 connects the second interface of the peripheral module to the second bus 150 when the peripheral module 130 is released by the host processor. In one embodiment, the arbitration logic 133 couples the first interface of the peripheral module 130 to the second bus 150 when the peripheral module 130 is released by the processor 120.

The peripheral module 130 communicates at least a portion of the information with the processor 120 and/or the host processor (via the bus interface circuit 110) via an interrupt.

In some embodiments, as shown in fig. 2, the peripheral module 130 further includes: a first interrupt unit 135. The first interrupt unit 135 may be used to send write-related interrupt information. This embodiment is not limited to this.

As an embodiment, the first interrupt unit 135 is configured to: after the register 131 of the peripheral module 130 is written with data by the processor 120, the first interrupt information is sent to the bus interface circuit 110. The bus interface circuit 110 transmits the first interrupt information to the host processor and may read and/or write the register 131 of the peripheral module 130 in response to a command of the host processor. And/or sending the second interrupt information to the processor 120 after the register 131 of the peripheral module 130 is written with data by the host processor. The processor 120 may read and/or write the register 131 of the peripheral module 130 in response to the second interrupt information.

As another implementation, the first interrupt unit 135 is configured to: after the register 131 of the peripheral module 130 is written with data by the peripheral connected thereto, first interrupt information is transmitted to the bus interface circuit 110. The bus interface circuit 110 transmits the first interrupt information to the host processor and may read and/or write the register 131 of the peripheral module 130 in response to a command of the host processor. In some cases, the peripheral module 130 sends data to its connected peripherals after the registers 131 of the peripheral module 130 are written to by the host processor.

In some embodiments, as shown in fig. 2, the at least one peripheral module 130 further comprises: a second interrupt unit 136. The first interrupt unit 135 may be used to send read-related interrupt information. This embodiment is not limited to this.

In one embodiment, the second interrupt unit 136 is configured to send the third interrupt information to the host processor after the data written by the host processor in the register 131 of the peripheral module 130 is read by the processor 120. And/or, after the data written by the processor 120 in the register 131 of the peripheral module 130 is read by the host processor, the fourth interrupt information is sent to the processor 120.

In some embodiments, processor 120 is configured to: detecting whether the register of the peripheral module 130 is written with data by the host processor; in case it is detected that the registers of the peripheral modules 130 are written with data by the host processor, data are read from the registers of the respective peripheral modules 130 over the second bus 150. In some cases, the processor 120 may transmit the read data to a peripheral interface unit connected thereto and corresponding to the peripheral module.

In some embodiments, the bus interface circuit 110 is further configured to set the first flag bit of the register of the corresponding peripheral module 130 to read after reading data from the register of the peripheral module 130. In some embodiments, the processor 120 is further configured to query the first flag bit of the register of the peripheral module 130, and determine whether the data in the register of the corresponding peripheral module 130 is read by the host processor based on the first flag bit.

The embedded control circuit based on the shared structure according to the exemplary embodiment of the present disclosure is described below by taking an eSPI bus as an example, and the host processor and the embedded control circuit communicate with each other through the eSPI bus.

Fig. 3 shows a schematic block diagram of an embedded control circuit based on an eSPI bus and a shared interface according to an exemplary embodiment of the disclosure, and as shown in fig. 3, the embedded control circuit 300 includes: an eSPI slave 310 for communicating with a host processor, a processor 320, a peripheral module 330, a first bus 340, and a second bus 350. In FIG. 3, a plurality of peripheral modules 330 are shown, respectively a keyboard module 330-1, a mouse module 330-2, a serial port module 330-3, and other peripherals 330-n. The first bus 340 is connected between the first interfaces of the keyboard module 330-1, the mouse module 330-2, the serial port module 330-3, and other peripherals 330-n and the eSPI slave module 310, and the second bus 350 is connected between the second interface of the peripheral module 330 and the processor 320. The eSPI slave 310 accesses the peripheral module 330 through the first bus 340. The processor 320 accesses the peripheral module 330 through the second bus 350.

The embedded control circuit 300 manages the peripherals through the eSPI interface between the host processor and the embedded control circuit 300 and the IO interface on the embedded control circuit 300 and accessible by the host processor (this interface is defined on the eSPI slave, an address accessible to the host processor).

In this embodiment, the keyboard module 330-1, the mouse module 330-2, the serial port module 330-3, and the other peripherals 330-n have 2 interfaces respectively connected to the first bus 340 (e.g., local bus 1) and the second bus 350 (e.g., local bus 2). The first bus 340 and the second bus 350 arbitrate the read/write operations to the registers via the access arbitration logic, the arbitration policy (selection priority) is selected by an arbitration control register, and the arbitration control is coupled to an arbitration control register external to the module, which is configured by the processor 320.

In the present embodiment, as shown in fig. 3, the connection is made using a bus matrix 352. The processor 320 is connected to a bus matrix 352, a second bus 350 is connected to the bus matrix 352 (via a bridge 351), the second bus 350 is connected to a second interface of the peripheral module 330, and the processor 320 accesses the peripheral module 330 via the bus matrix 352 and the second bus 352. The peripheral module 330 corresponds to and is independent of the peripheral module 330 and the interface unit (e.g., keyboard interface unit) connected to the processor 320 is connected to the bus matrix 352 through a bus such as a fast bus, and the processor 320 and the interface unit communicate with each other through the bus matrix 352 and the associated bus.

Taking a serial port as an example, the register of the serial port module 330-3 has 2 interfaces, one interface is connected to the host processor through the first bus 340, so that the host processor can configure or operate the serial port through the interface, and the other interface is connected to the processor 320 through the second bus 350, so that the processor 320 of the embedded control circuit 300 can configure and access the serial port through the interface. When the host processor and the processor 320 configure or operate the registers of the serial port through two different interfaces at the same time, the access arbitration mechanism gives the host processor or the processor 320 higher access priority according to the configuration.

An exemplary serial port operation is described below. Serial module 330-3 obtains data from and/or provides data to peripherals connected to its interface unit, and communication between serial module 330-3 and the host processor may not pass through processor 120. The host processor reads and/or writes the serial port module 330-3, for example, writes data to be transmitted through the connected peripheral to the serial port module 330-3, or reads data from the connected peripheral from the serial port module 330-3, or configures parameters of the serial port module 330-3.

An exemplary keyboard operation is described below. The keyboard interface unit corresponding to keyboard module 330-1 is connected to processor 320 independently of keyboard module 330-1. When a computer operator presses a certain key of the keyboard, the processor 320 obtains a keyboard code corresponding to the key action of the keyboard through the keyboard interface unit, and writes the keyboard code into a register in the keyboard module 330-1 through the bus matrix 352, the bridge 351 and the second bus 350. The keyboard module 330-1 generates interrupts from the module 310 through the eSPI and reports them to the host processor. The host processor receives the interrupt, initiates a read operation, reads the keyboard code value in the register of keyboard module 330-1, sets the flag bit that the code value has been read, and clears the corresponding register. Keyboard module 330-1 generates an interrupt that informs processor 320 that the keyboard value has been read by the host processor. If no interrupt is required, processor 320 may query the Status flag bit of keyboard module 330-1 to determine whether the keyboard code value is read by the host processor.

The embodiment of the disclosure provides an embedded control circuit for direct memory access.

Fig. 4 shows a schematic block diagram of an embedded control circuit for direct memory access according to an exemplary embodiment of the present disclosure, and as shown in fig. 4, the embedded control circuit 400 includes: a bus interface circuit 410 for communicating with a host processor, a processor 420, one or more peripheral modules 430, circuitry 440, a first bus 450, and a second bus 460. In this embodiment, the embedded control circuitry may include one or more peripheral modules 430, illustratively shown in FIG. 4 as peripheral modules 430-1 through 430-n.

As shown in fig. 4, circuitry 440 is coupled to bus interface circuit 410. The first bus 450 is connected between the peripheral modules 430 and the circuitry 440; a second bus 460 is connected between the peripheral modules 430 and the processor 420. Wherein the circuitry 440 communicates with the host processor via the bus interface circuit 410 and accesses the peripheral module 430 via the first bus 450 based on commands from the host processor. The processor 420 is configured to access the peripheral modules 430 through the second bus 460. In this embodiment, the I/O interface of the peripheral module 430 may not be defined at the bus interface circuit 410, and the circuitry 440 is configured to access the peripheral module 430 via the first bus 450 based on commands from the host processor, so that the integration (e.g., addition) of the peripheral module 430 in the embedded control circuit may not modify the bus interface circuit.

In this embodiment, the circuitry 440 accessing the peripheral module 430 may employ Direct Memory Access (DMA) commands.

In this embodiment, various types of bus interfaces may be employed to communicate with the host processor, including but not limited to an LPC bus, an SPI bus, an eSIP bus, and the like. The bus interface circuit 410 includes a bus interface or a plurality of bus interfaces. The bus interface circuit 410 is operable to use one of a plurality of bus interfaces for communication. This embodiment is not limited to this. In this embodiment, the bus interface circuit 410 and the host processor may communicate according to a bus protocol. As an example, an eSPI bus may be used between embedded control circuit 400 and a host processor, embedded control circuit 400 being a slave device (eSPIslave) in the eSPI bus, the host processor being a master device (eSPImaster) in the eSPI bus, and bus interface circuit 410 being an eSPI slave module. This embodiment is not limited to this.

In the present embodiment, the first bus 450 may include any bus compatible with the peripheral modules 430 and the circuit system 440, and examples of the first bus 450 may include a local bus, an AXI bus, an APB, an AHB, and the like, which is not limited in this embodiment. In this embodiment, the circuitry 440 may act as a master (master) for the first bus 450 and the peripheral modules 430 may act as slaves (slave) for the first bus 450. The peripheral modules 430 may respond to various bus commands from the circuitry 440.

In the present embodiment, the second bus 460 may include any bus compatible with the peripheral modules 430 and the processor 420, and examples of the second bus 460 may include a local bus, an AXI bus, an APB, an AHB, and the like, which is not limited in this embodiment. In this embodiment, the processor 420 may serve as a master (master) of the second bus 460, and the peripheral module 430 may serve as a slave (slave) of the second bus 460. The peripheral modules 430 may respond to various bus commands from the processor 420.

In some embodiments, the embedded control circuit 400 may use a bus matrix, through which the circuitry 440, the processor 420, and the peripheral modules 430 may access in parallel, thereby improving access efficiency and reducing power consumption.

In this embodiment, the circuitry 440 is capable of communicating with the host processor via the bus interface circuit 410, accessing the peripheral module 430 via the first bus 450 based on commands from the host processor, and the processor 420 is capable of accessing the peripheral module 430 via the second bus 460. Fig. 5 is a flowchart illustrating a peripheral access method of direct memory access according to an exemplary embodiment of the present disclosure, and as shown in fig. 5, the peripheral access method includes steps S501 and S502. In step S501, the peripheral module 430 is accessed through the first bus 450 based on a command of the host processor by the circuitry 440 communicating with the host processor through the bus interface circuit 410. In step S502, the peripheral module 430 is accessed by the processor 420 through the second bus 460.

In some embodiments, in step S502, the processor 420 writes data to the register of the peripheral module 430 through the second bus 460. In some embodiments, in step S502, data is read from the registers of the peripheral module 430 by the processor 420 through the second bus 460.

In some embodiments, circuitry 440 is configured to: a write command from the host processor is received through the bus interface circuit 410 and data is written to the register of the peripheral module 430 corresponding to the write command through the first bus 450 based on the write command. In step S501, a write command from the host processor is received by the circuitry 440 via the bus interface circuit 410, and data is written to the register of the peripheral module 430 corresponding to the write command via the first bus 450 based on the write command.

In some embodiments, circuitry 440 is configured to: a read command from the host processor is received via the bus interface circuit 410, and data is read from the register of the peripheral module 430 corresponding to the read command via the first bus 450 based on the read command. In step S501, a read command from the host processor is received by the circuitry 440 via the bus interface circuit 410, and data is read from a register of the peripheral module 430 corresponding to the read command via the first bus 450 based on the read command.

In some embodiments, as shown in fig. 4, the embedded control circuit 400 further includes: a third bus 470 is coupled between processor 420 and circuitry 440. Information may be transmitted between circuitry 440 and processor 420 via third bus 470, examples of which may include configuration of circuitry 440 by processor 420, interrupt information of peripheral module 430 sent by processor 420 to the host processor, and so on, and the present implementation is not limited thereto. In one embodiment, processor 420 may act as a master (master) for third bus 470 and circuitry 440 may act as a slave (slave) for third bus 470. Circuitry 440 may be responsive to various bus commands from processor 420.

In some embodiments, as shown in fig. 4, the embedded control circuit 400 further comprises: an interrupt signal line 480 is connected between the processor 420 and the circuitry 440. Interrupt signal line 480 may be configured to transmit any interrupt signals between processor 420 and circuitry 440, although this embodiment is not limited in this respect. As an embodiment, circuitry 440 is configured to transmit an interrupt signal to processor 420 via interrupt signal line 480.

In some embodiments, the circuitry 440 is configured to access the peripheral module 430 based on preconfigured permissions. In this embodiment, each target address may be configured to allow reading and writing, or allow reading and inhibit writing, or allow writing and inhibit reading, which is not limited in this embodiment. In one embodiment, the processor 420 configures the circuitry 440 access to the peripheral modules 430 via the third bus 470. The circuitry 440 is configured to access the peripheral module 430 based on the privilege information configured by the processor 420.

In some embodiments, circuitry 440 is configured to access peripheral module 430 based on preconfigured permissions and transmit an interrupt signal to processor 420 over interrupt signal line 480 to notify processor 420 that the host processor requests access to the registers to which access is prohibited, in the event that the registers of peripheral module 430 to which the host processor accesses are configured to be prohibited from access.

An example of writing data to the peripheral module 430 under the authority control is explained as follows, as an embodiment. Bus interface circuit 410 receives write commands from the host processor and sends the write commands to circuitry 440. Circuitry 440 receives the write command and parses the write command into the target address and the data to be written. The circuit system 440 determines whether the target address is a write-enabled address, and if the target address is a write-enabled address, the circuit system 440 writes the data to the register of the peripheral module 430 corresponding to the target address through the first bus 450. In some examples, where the target address is a write-inhibit address, circuitry 440 transmits an interrupt signal to processor 420 over interrupt signal line 480 to notify processor 420 that the host processor requests access to the write-inhibit register.

An example of reading data from the peripheral module 430 under the authority control is explained as follows as an embodiment. Bus interface circuit 410 receives a read command from the host processor and sends the read command to circuitry 440. Circuitry 440 receives the read command and resolves the target address from the read command. Circuitry 440 determines whether the target address is an address that allows reading. In the case where the target address is an address allowing reading, the circuitry 440 reads data from the register of the peripheral module 430 corresponding to the target address through the first bus 450. After reading the data, the circuit system 440 generates a bus command corresponding to the read command, and transmits the bus command to the bus interface circuit 410. Bus interface circuit 410 sends the bus command to the host processor to cause the host processor to receive the bus command to obtain the read data. In some examples, where the target address is a read-inhibited address, circuitry 440 transmits an interrupt signal to processor 420 over interrupt signal line 480 to notify processor 420 that the host processor requests access to a read-inhibited register.

In some embodiments, the processor 420 sends interrupt information for the peripheral module 430 to the circuitry 440 via the third bus 470. Further, circuitry 440 sends the interrupt information to the host processor via bus interface circuit 410.

An example of the processor 420 sending interrupt information of the peripheral module 430 to the host processor is described below as an embodiment. The processor 420 detects interrupt information of the peripheral module 430. Processor 420 sends the detected interrupt information to circuitry 440 via third bus 470. The circuit system 440 generates a bus command corresponding to the interrupt information, and transmits the generated bus command to the bus interface circuit 410. Bus interface circuit 410 sends the bus command to the host processor to cause the host processor to receive the bus command to obtain interrupt information. As an example, the host processor, upon acquiring the interrupt information, responds to the embedded control circuitry based on the interrupt information. In some examples, the host processor initiates a process to write data to the register of the peripheral module 430 to which the interrupt information corresponds based on the interrupt information. In some examples, the host processor initiates a process to read data from a register of the peripheral module 430 corresponding to the interrupt information based on the interrupt information.

Fig. 6 shows a schematic block diagram of circuitry 440 of an exemplary embodiment of the present disclosure, as shown in fig. 6, circuitry 440 includes: a receiving circuit 441 configured to receive the bus command transmitted by the bus interface circuit 410; an analyzing circuit 442, connected to the receiving circuit 441, configured to analyze the received bus command to obtain a target address; the first controller 443 is connected to the parsing circuit 442 and configured to access the register of the peripheral module 430 corresponding to the target address. In this embodiment, the parsing circuit 442 parses the bus command according to a bus interface protocol used by the bus interface circuit 410.

In some embodiments, the bus command comprises a write command, and the parsing circuit 442 parses the bus command to obtain the target data, where the target address is the address to be written. The first controller 443 is configured to: and writing the target data into the register of the peripheral module 430 corresponding to the target address.

An example of writing data to the peripheral module 430 is described below as an embodiment. Bus interface circuit 410 receives write commands from the host processor and sends the write commands to receive circuit 441. The receiving circuit 441 receives a write command and sends the write command to the parsing circuit 442. The parsing circuit 442 parses the target address and the data to be written from the write command. The first controller 443 writes the data into the register of the peripheral module 430 corresponding to the target address through the first bus 450.

In some embodiments, the bus command includes a read command, and the parsing circuit 422 parses the bus command to obtain a target address as the address to be read.

In some embodiments, as shown in fig. 6, the circuit system 440 further includes a buffer module 444 connected between the receiving circuit 441 and the parsing circuit 442 for buffering the received bus command for the parsing circuit 442 to parse the bus command.

An example of writing data to the peripheral module 430 is described below as an embodiment. Bus interface circuit 410 receives write commands from the host processor and sends the write commands to receive circuit 441. The receiving circuit 441 receives the write command, and the receiving circuit 441 buffers the write command to the buffer module 444. The parsing circuit 442 obtains the write command from the buffer module 444, and the parsing circuit 442 parses the write command to obtain the target address and the data to be written. The first controller 443 writes the data into the register of the peripheral module 430 corresponding to the target address through the first bus 450.

In some embodiments, as shown in fig. 6, circuitry 440 further includes: generating circuitry 445 configured to generate a bus command; a transmitting circuit 446, connected to the generating circuit 445, configured to transmit the bus command generated by the generating circuit 445 to the bus interface circuit 410, so that the generated bus command is received by the host processor.

In some embodiments, the first controller 443 is further configured to transmit data read from the target address to the generating circuit 445, to generate a corresponding bus command by the generating circuit 445, and to transmit the generated bus command to the bus interface circuit 410 by the transmitting circuit 446.

An example of reading data from the peripheral module 430 is described below as an embodiment. Bus interface circuit 410 receives a read command from the host processor and sends the read command to receive circuit 441. Receiving circuit 441 receives a read command and sends the read command to parsing circuit 442. The parsing circuit 442 parses the target address from the read command. The first controller 443 reads data from the register of the peripheral module 430 corresponding to the target address through the first bus 450. The first controller 443 transmits the read data to the generation circuit 445. The generating circuit 445 generates a bus command corresponding to the read command, and transmits the bus command to the transmitting circuit 446. The transmission circuit 446 transmits the bus command to the bus interface circuit 410. Bus interface circuit 410 sends the bus command to the host processor to cause the host processor to receive the bus command to obtain the read data.

In some embodiments, as shown in fig. 6, circuitry 440 further includes: a second controller 447 configured to receive information transmitted by the processor 420 through the third bus 470.

In some embodiments, the second controller 447 is further configured to receive interrupt information sent by the processor 420 via the third bus 470, send the interrupt information to the generating circuit 445 to generate a corresponding bus command by the generating circuit 445, and send the generated bus command to the bus interface circuit 410 by the sending circuit 446 to send the interrupt information to the host processor via the bus interface circuit 410.

An example of the processor 420 sending interrupt information of the peripheral module 430 to the host processor is described below as an embodiment. The processor 420 detects interrupt information of the peripheral module 430. Processor 420 sends the detected interrupt information to generation circuitry 445 via third bus 470. The generating circuit 445 generates a bus command corresponding to the interrupt information. The transmission circuit 446 transmits the bus command generated by the generation circuit 445 to the bus interface circuit 410. Bus interface circuit 410 sends the bus command to the host processor to cause the host processor to receive the bus command to obtain interrupt information. As an example, the host processor, upon acquiring the interrupt information, responds to the embedded control circuitry based on the interrupt information. In some examples, the host processor initiates a process to write data to the register of the peripheral module 430 to which the interrupt information corresponds based on the interrupt information. In some examples, the host processor initiates a process to read data from the register of the peripheral module 430 corresponding to the interrupt information based on the interrupt information.

In some embodiments, circuitry 440 also includes: the safety control module 448 is connected to the first controller 443 and the second controller 447. The security control module 448 is configured to provide rights information. The first controller 443, further configured to determine the right to access the target address based on the rights information in the security control module 448. The second controller 447 is further configured to receive the authority information sent by the processor 420 through the third bus 470, and write the authority information into the security control module 448. In this embodiment, each target address may be configured to allow reading and writing, or allow reading and inhibit writing, or allow writing and inhibit reading, which is not limited in this embodiment.

An example of writing data to the peripheral module 430 under the authority control is explained as follows, as an embodiment. Bus interface circuit 410 receives write commands from the host processor and sends the write commands to receive circuit 441. The receiving circuit 441 receives the write command and sends the write command to the parsing circuit 442, and as an example, the receiving circuit 441 may buffer the write command to the buffer module 444 and the parsing circuit 442 may obtain the write command from the buffer module 444. The parsing circuit 442 parses the target address and the data to be written from the write command. The first controller 443 determines whether or not the destination address is a write-permitted address, and if the destination address is a write-permitted address, the first controller 443 writes the data into the register of the peripheral module 430 corresponding to the destination address via the first bus 450. In some examples, the first controller 443 may access the security control module 448, obtain the rights information from the security control module 448, and determine whether the target address is an address that allows writing based on the rights information. In some examples, where the target address is a write-inhibit address, the first controller 443 transmits an interrupt signal to the processor 420 through the interrupt signal line 480 to make the processor 420 aware that the host processor requests to write data to the write-inhibit address.

An example of reading data from the peripheral module 430 under the authority control is explained as follows as an embodiment. Bus interface circuit 410 receives a read command from the host processor and sends the read command to receive circuit 441. Receiving circuitry 441 receives the read command and sends the read command to parsing circuitry 442, and in some examples, receiving circuitry 441 buffers the read command to buffer module 444 and parsing circuitry 442 retrieves the read command from buffer module 444. The parsing circuit 442 parses the target address from the read command. The first controller 443 determines whether the target address is an address allowing reading, and in some examples, the first controller 443 accesses the security control module 448, acquires the rights information from the security control module 448, and determines whether the target address is an address allowing reading based on the rights information. In the case where the target address is an address allowing reading, the first controller 443 reads data from a register of the peripheral module 430 corresponding to the target address through the first bus 450. The first controller 443 transmits the read data to the generation circuit 445. The generating circuit 445 generates a bus command corresponding to the read command, and transmits the bus command to the transmitting circuit 446. The transmission circuit 446 transmits the bus command to the bus interface circuit 410. Bus interface circuit 410 sends the bus command to the host processor to cause the host processor to receive the bus command to obtain the read data. In some examples, where the target address is a read-inhibit address, the first controller 443 transmits an interrupt signal to the processor 420 through the interrupt signal line 480 to make the processor 420 aware of the address at which the host processor requests a read-inhibit.

The embedded control circuit for direct memory access according to the exemplary embodiment of the present disclosure is described below with an eSPI bus as an example, and the host processor and the embedded control circuit communicate with each other through the eSPI bus.

Fig. 7 shows a schematic block diagram of an embedded control circuit using an eSPI bus and direct memory access according to an exemplary embodiment of the present disclosure, and as shown in fig. 7, an embedded control circuit 700 includes: an eSPI slave module 710 for communicating with a host processor, a processor 720, one or more peripheral modules 730, circuitry 740. In this embodiment, the embedded control circuitry may include one or more peripheral modules 730, illustratively shown in FIG. 7 as peripheral modules 730-1 through 730-n.

As shown in fig. 7, circuitry 740 connects to the eSPI slave 710, and the eSPI slave 710 communicates with the host processor using the eSPI protocol. The eSPI slave 710, the processor 720, and the peripheral module 730 are connected by a bus matrix 750, which in this embodiment is an AHB bus. The bus between eSPI slave 710, processor 720, and peripheral modules 730 in this embodiment may include data lines, control lines, and address lines.

In this embodiment, circuitry 740 accesses peripheral modules 730 through bus matrix 750. On the AHB bus between the circuitry 740 and the peripheral modules 730, the circuitry 740 functions as a master (master) of the AHB bus, the peripheral modules 730 function as slaves of the AHB bus, and the peripheral modules 730 respond to various bus commands of the circuitry 740.

In this embodiment, the processor 720 accesses the peripheral modules 730 through the bus matrix 750. On the AHB bus between processor 720 and peripheral modules 730, processor 720 serves as a master (master) of the AHB bus, peripheral modules 730 serve as slaves (slave) of the AHB bus, and peripheral modules 730 respond to various bus commands of processor 720.

In this embodiment, processor 720 accesses circuitry 740 through bus matrix 750. On the AHB bus between processor 720 and circuitry 740, processor 720 acts as a master (master) for the AHB bus, circuitry 740 acts as a slave (slave) for the AHB bus, and circuitry 740 responds to various bus commands by processor 720. In one embodiment, processor 720 accesses circuitry 740 via bus matrix 750 to configure the access rights of circuitry 740 to peripheral modules 730. In another embodiment, processor 720 accesses circuitry 740 through bus matrix 750 to send interrupt information for peripheral module 730 to the host processor.

In this embodiment, an interrupt signal line 760 is coupled between processor 720 and circuitry 740. Circuitry 740 is capable of sending an interrupt signal to circuitry 740 via interrupt signal line 760.

Fig. 8 shows a schematic block diagram of circuitry 740 of an exemplary embodiment of the disclosure, as shown in fig. 8, circuitry 740 comprising: an eSPI command receiving module 741 configured to receive a bus command transmitted by the eSPI slave module 710; a command buffer module 744 connected to the eSPI command receiving module 741, configured to buffer the received eSPI command; an eSPI command parsing module 742, connected to the eSPI command receiving module 741, configured to parse the received eSPI command to obtain a target address; the AHBmaster interface 743 is connected to the eSPI command parsing module 742, and is configured to access a register of the peripheral module 730 corresponding to the target address.

The eSPI command includes a write command, and the eSPI command parsing module 742 parses the eSPI command to obtain target data, where the target address is an address to be written. The AHBmaster interface 743 is configured to: and writing the target data into the register of the peripheral module 730 corresponding to the target address.

An example of writing data to the peripheral module 730 is described below as an embodiment. The eSPI slave module 710 receives a write command of the host processor and transmits the write command to the eSPI command receiving module 741. The eSPI command receiving module 741 receives the write command and writes the write command to the command buffer module 744. The eSPI command parsing circuit 742 obtains the write command from the command buffer module 744, and parses the write command to obtain the target address and the data to be written. The AHBmaster interface 743 writes the data to the register of the peripheral module 730 corresponding to the target address through the bus matrix 750.

As shown in fig. 8, circuitry 740 further includes: an eSPI command generation module 745 configured to generate an eSPI command; the eSPI command sending module 746, connected to the eSPI command generating module 745, is configured to send the eSPI command generated by the eSPI command generating module 745 to the eSPI slave module 710 so that the generated eSPI command is received by the host processor.

The eSPI command includes a read command. The AHB master interface 743 is further configured to: after the data is read, the data read from the target address is sent to the eSPI command generation module 745 so that the eSPI command generation module 745 generates a corresponding eSPI command, and the eSPI command sending module 746 sends the generated eSPI command to the eSPI slave module 710.

An example of reading data from the peripheral module 730 is described below as an embodiment. After the AHB master interface 743 reads data from the target address, the AHB master interface 743 sends the read data to the eSPI command generation module 745. The eSPI command generating module 745 generates an eSPI command corresponding to the read command, and sends the eSPI command to the eSPI command sending module 746. The eSPI command send module 746 sends the eSPI command to the eSPI slave module 710. The eSPI slave module 710 sends the eSPI command to the host processor to cause the host processor to receive the eSPI command to obtain the read data.

As shown in fig. 8, circuitry 740 further includes: AHB slave interface 747 is configured to receive information sent by processor 720 via bus matrix 750. AHB slave interface 747 is configured to receive interrupt information sent by processor 720 through bus matrix 750, send the interrupt information to eSPI command generation module 745 to generate a corresponding eSPI command by eSPI command generation module 745, and send the generated eSPI command to eSPI slave module 710 by eSPI command send module 746 to send the interrupt information to the host processor through eSPI slave module 710.

An example of the processor 720 sending interrupt information for the peripheral module 730 to the host processor is described below as an embodiment. The processor 720 detects the interrupt information of the peripheral module 730. Processor 720 sends the detected interrupt information to eSPI command generation module 745 over the bus matrix. The eSPI command generation module 745 generates an eSPI command corresponding to the interrupt information. The eSPI command sending module 746 sends the eSPI command generated by the eSPI command generating module 745 to the eSPI slave module 710. The eSPI slave module 710 sends the eSPI command to the host processor to cause the host processor to receive the eSPI command to obtain interrupt information. As an example, the host processor, upon acquiring the interrupt information, responds to the embedded control circuitry based on the interrupt information. In some examples, the host processor initiates a process to write data to the register of the peripheral module 730 corresponding to the interrupt information based on the interrupt information. In some examples, the host processor initiates a process to read data from the register of the peripheral module 730 corresponding to the interrupt information based on the interrupt information.

In some embodiments, circuitry 740 further comprises: the security control module 748 is connected to the AHB master interface 743 and the AHB slave interface 747. The security control module 748 is configured to provide rights information. The AHB master interface 743, is further configured to determine the right to access the target address based on the rights information in the security control module 748. AHB slave interface 747 is further configured to receive the permission information sent by processor 720 through bus matrix 750, and write the permission information to security control module 748. In this embodiment, each target address may be configured to allow reading and writing, or allow reading and inhibit writing, or allow writing and inhibit reading, which is not limited in this embodiment.

As an embodiment, an example of writing data to the peripheral module 730 under the authority control is explained as follows. The eSPI slave module 710 receives a write command of the host processor and sends the write command to the eSPI command receiving module 741. The eSPI command receiving module 741 receives the write command, which is buffered in the command buffer module 744. The eSPI command parsing module 742 obtains the write command from the command buffer module 744, and parses the write command to obtain the target address and the data to be written. The AHB master interface 743 has access to the security control module 748, acquires the authority information from the security control module 448, and determines whether the target address is an address to which writing is permitted based on the authority information. When the target address is an address to which writing is permitted, the AHB master interface 743 writes the data to the register of the peripheral module 730 corresponding to the target address via the bus matrix 750. In the case where the target address is a write-inhibited address, the AHB master interface 743 transmits an interrupt signal to the processor 720 through the interrupt signal line 760 so that the processor 720 knows that the host processor requests writing of data to the write-inhibited address.

An example of reading data from the peripheral module 730 under the authority control is explained as follows as an embodiment. The eSPI slave module 710 receives a read command of the host processor and sends the read command to the eSPI command receiving module 741. The eSPI command receiving module 741 receives the read command and buffers the read command in the command buffer module 744. The eSPI command parsing module 742 obtains the read command from the command buffer module 744 and parses the read command to obtain the target address. The AHB master interface 743 accesses the security control module 748, acquires the authority information from the security control module 748, and determines whether the target address is an address permitted to be read based on the authority information. In the case where the target address is an address allowing reading, the AHB master interface 743 reads data from the register of the peripheral module 730 corresponding to the target address through the bus matrix 750. The AHB master interface 743 sends the read data to the eSPI command generation module 745. The eSPI command generating module 745 generates an eSPI command corresponding to the read command, and sends the eSPI command to the eSPI command sending module 746. The eSPI command send module 746 sends the eSPI command to the eSPI slave module 710. The eSPI slave module 710 sends the eSPI command to the host processor to cause the host processor to receive the eSPI command to obtain the read data. In the case where the target address is a read-inhibited address, the AHB master interface 743 transmits an interrupt signal to the processor 720 through the interrupt signal line 760 so that the processor 720 knows the address at which the host processor requests the read inhibition.

As shown in fig. 7 and 8, circuitry 740 further includes: interrupt control 749 is coupled to interrupt signal line 760 for transmitting interrupt signals to processor 720 via interrupt signal line 760 in response to commands from AHB master interface 743 and/or AHB slave interface 747.

As an example, an example of reading data from a peripheral module based on the eSPI is explained as follows. Processor 720 detects an interrupt to peripheral module 730. In the event that an interrupt associated with peripheral module 730 and the host processor is detected, processor 720 writes interrupt information, including an interrupt status and an interrupt ID, to the shared registers of eSPI slave module 710 via AHB slave interface 747. The eSPI slave module 710 receives this write information and alerts by pulling down the IO pin or a dedicated Alert signal. The host processor receives the alarm signal and inquires the reason of the alarm event through a GET _ STATUS command. The eSPI slave module 710 receives the GET _ STATUS command and issues the interrupt information in the shared register to the host processor via the eSPI packet. The host processor determines the cause of the alarm based on the interrupt information, and the host processor initiates a GET _ PC or GET _ NP command to read the data. The command is received by eSPI slave 710, converted to a DMA operation by circuitry 740, and read back the data from the registers of the corresponding peripheral module 730, and uploaded to the host processor by eSPI slave 710 via an eSPI packet.

For example, for the keyboard, when the operator presses the keyboard, the keyboard scan module detects and holds the key code of the pressed key, and initiates an interrupt to the processor 720, the processor 720 queries that the interrupt ID comes from the keyboard scan module, and the interrupt reason (or interrupt status) is that the operator has a key operation, the processor 720 writes the interrupt ID and the interrupt status into the shared register of the eSPI slave module 710 through the AHB slave interface 747, and the eSPI slave module 710 receives the written information and alarms by pulling down the IO pin or a dedicated Alert signal. After receiving the alarm signal, the host processor queries the reason of the alarm event through a GET _ STATUS command, and after receiving the GET _ STATUS command, the eSPI slave module 710 sends the interrupt ID and the interrupt STATUS in the shared register to the host processor through an eSPI packet. When the reason that the operator presses the keyboard is known, the host processor initiates a GET _ PC/NP command to read the key code of the key pressed by the operator, and after the eSPI slave module 710 receives the command, the circuit system 740 converts the command into a DMA operation, reads back the key code held by the keyboard scanning module, and sends an eSPI packet from the module 710 through the eSPI to upload to the host processor.

As an example, writing data to the outbound module 730 based on eSPI is described below. The host processor sends a write command. The eSPI slave module 710 receives the write command, and the circuitry 740 obtains the write address and the data from the write command and writes the data to the register of the peripheral module 730 corresponding to the write address.

For example, for an atmosphere lamp, when the host processor wants to send lamp effect data to the atmosphere lamp for display, the host processor first initiates a data write operation to initiate a write data packet, the eSPI slave module 710 receives the packet, the circuitry 740 unpacks the write command to a register of the atmosphere lamp and converts the command into a DMA operation to write the data sent from the host processor into a designated address of the atmosphere lamp, and the atmosphere lamp changes the display state accordingly to complete the display effect required by the host processor. For example, the atmosphere lamp may be interrupted during operation, such as when there is no data to display (the data buffer is empty), or when the atmosphere lamp displays an error. When the mood light generates an interrupt, as with the keyboard, an interrupt is initiated to processor 720, processor 720 in turn alerts the host processor through eSPI slave module 710, the host processor queries for the cause of the alert, and reads the relevant data.

The embodiment of the disclosure provides an embedded control circuit based on direct memory access and a shared interface.

Fig. 9 shows a schematic block diagram of an embedded control circuit based on a direct memory access and shared interface according to an exemplary embodiment of the disclosure, and as shown in fig. 9, the embedded control circuit 900 includes: bus interface circuitry 910 for communicating with a host processor, a processor 920, one or more first peripheral modules 931, one or more second peripheral modules 932, circuitry 940; a first bus 951, a second bus 952, and a third bus 961. Wherein the plurality of first peripheral modules 931 are labeled 931-1 to 931-n in fig. 9 and the plurality of second peripheral modules 931 are labeled 932-1 to 932-m in fig. 9. It should be understood that the present embodiment does not limit the number of the first peripheral module 931 and the second peripheral module 932, and the embedded control circuit 900 may include any number of the first peripheral module 931 and the second peripheral module 932.

In some embodiments, the embedded control circuit 900 further comprises: a fourth bus 962 is coupled between the processor 920 and the circuitry 940 for transferring information between the processor 920 and the circuitry 940.

In some embodiments, the embedded control circuit 900 further comprises: and an interrupt signal line connected between the processor 920 and the circuitry 940. The interrupt signal line may be configured to transmit any interrupt signal between processor 920 and circuitry 940, which is not limited by the present embodiment. As an embodiment, circuitry 940 is configured to transmit an interrupt signal to processor 920 over interrupt signal line 980. Reference is made to fig. 4 and the description thereof, which will not be described in detail in this embodiment.

Each of the first peripheral modules 931 includes a first interface and a second interface. A first bus 951 is coupled between the first interface of each of the first peripheral modules 931 and the bus interface circuit 910. A second bus 952 is connected between the second interface of each first peripheral module 931 and the processor 920. The bus interface circuit 910 is provided with an I/O interface corresponding to each of the first peripheral modules 931. A bus interface circuit 910 configured to access the first peripheral module 931 through the first bus 951. The processor 920 is configured to access a first peripheral module 931 through a second bus 952.

A third bus 961 is connected between the second peripheral module 932 and the circuitry 940. The third bus 961 is also connected between the second peripheral module 932 and the processor 920. Circuitry 940 configured to communicate with the host processor via the bus interface circuit 910 to access the second peripheral module 932 via the third bus 961 based on commands from the host processor. In this embodiment, the circuit system 940 serves as a master of the third bus 961, the second peripheral module 932 serves as a slave of the third bus 961, and the second peripheral module 932 may respond to various bus commands of the circuit system 940. The processor 920 accesses the second peripheral module 932 via the third bus 961. In this embodiment, the processor 920 may act as a master of the third bus 961, the second peripheral module 932 may act as a slave of the third bus 961, and the second peripheral module 932 may respond to various bus commands of the processor 920.

In some embodiments, at least some of the first bus 951, the second bus 952, the third bus 961, and the fourth bus 962 may employ a bus matrix through which at least some of the bus interface circuit 910, the processor 920, the first peripheral module 931, the second peripheral module 932, and the circuitry 940 may be accessed.

In this embodiment, the first peripheral module 931 can refer to the descriptions of fig. 1, fig. 2 and fig. 3 in the present disclosure, and is not described herein again. In this embodiment, the circuit 940 and the second peripheral module 932 can refer to the descriptions of fig. 4, fig. 6, fig. 7, and fig. 8, which are described above in this disclosure, and are not described herein again.

In this embodiment, the host processor may access the first peripheral module 931 through the bus interface circuit 910 and the first bus 951. The host processor may also access a second peripheral module 932 via the bus interface circuit 910, circuitry 940, and a third bus 961. An embodiment in which the embedded control circuit 900 distinguishes accesses of the host processor to the first peripheral module 931 and the second peripheral module 932 is described below.

In some embodiments, the bus interface circuit 910 is configured to: determining whether the host processor accesses the first peripheral module 931 or the second peripheral module 932 based on the accessed target address, in the case where the host processor accesses the first peripheral module 931, accessing the first peripheral module 931 through the first bus 951; in the event that the host processor accesses the second peripheral module 932, the host processor's access command is forwarded to circuitry 940. The circuitry 940 accesses the second peripheral module 932 via the third bus 961 based on an access command of the host processor.

In some embodiments, the circuitry is configured 940 to: determining whether the host processor access is a second peripheral module 932 based on the accessed target address; in the case where the host processor accesses the second peripheral module 932, the second peripheral module 932 is accessed through the third bus 961 based on a command of the host processor.

In some embodiments, each first peripheral module 931 is configured to: determining whether the host processor accesses itself based on the accessed target address; in the case of a host processor access to itself, the host processor access is responded to.

Fig. 10 is a flowchart illustrating a peripheral access method based on a direct memory access and shared interface according to an exemplary embodiment of the present disclosure, applied to the embedded control circuit 900 shown in fig. 9. The peripheral access method includes steps S1001 to S1004. It should be understood that although step numbers are marked in fig. 10, the present embodiment does not limit the sequence of step S1001 to step S1004.

In step S1001, the first peripheral module 931 is accessed through the first bus 951 by the bus interface circuit 910. In this embodiment, the bus interface circuit 910 accesses the first peripheral module 931 through the first bus 951 including reading and/or writing registers of the first peripheral module 931. In this embodiment, the first bus 951 is connected between the bus interface circuit 910 and the first interface of the first peripheral module 931, and the bus interface circuit 910 accesses the register of the first peripheral module 931 through the first bus 951 and the first interface of the first peripheral module 931.

In step S1001, the bus interface circuit 910 receives a write command from the host processor, and writes data to a register of the first peripheral module 931 corresponding to the write command via the first bus 951. The bus interface circuit 910 may also receive a read command from the host processor, and read data from a register of the first peripheral module 931 corresponding to the read command through the first bus 951.

In step S1002, the second peripheral module 932 is accessed through the third bus 961 based on a command of the host processor by the circuitry 940 communicating with the host processor through the bus interface circuit 910.

In step S1002, the circuitry 940 receives a write command from the host processor through the bus interface circuit 910, and writes data to the register of the second peripheral module 932 corresponding to the write command through the third bus 961 based on the write command. The circuitry 940 may also receive a read command from the host processor via the bus interface circuit 910, and read data from the register of the second peripheral module 932 corresponding to the read command via the third bus 961 based on the read command.

In some embodiments, the circuitry 940 accesses the second peripheral module 932 based on preconfigured permissions. In this embodiment, each target address may be configured to allow reading and writing, or allow reading and inhibit writing, or allow writing and inhibit reading, which is not limited in this embodiment. In one embodiment, the processor 920 configures the circuitry 940 for access to the second peripheral module 932 via a fourth bus 962 coupled between the processor 920 and the circuitry 940. Circuitry 940 accesses second peripheral module 932 based on the permission information configured by processor 920.

An example of writing data under the authority control to the second peripheral module 932 under the authority control is explained as follows, as an embodiment. Bus interface circuit 910 receives write commands from the host processor and sends the write commands to circuitry 940. Circuitry 940 receives the write command and parses the write command to obtain the target address and the data to be written. The circuit system 940 determines whether the target address is a write-enabled address, and if the target address is a write-enabled address, the circuit system 940 writes the data into the register of the second peripheral module 932 corresponding to the target address through the third bus 961. In some examples, where the target address is a write-inhibit address, circuitry 940 transmits an interrupt signal to processor 920 through an interrupt signal line between circuitry 940 and processor 920 to notify processor 920 that the host processor requests access to the write-inhibit register.

An example of reading data from the second peripheral module 932 under the authority control is described below as an embodiment. Bus interface circuit 910 receives a read command from the host processor and sends the read command to circuitry 940. Circuitry 940 receives the read command and parses the target address from the read command. Circuitry 940 determines whether the target address is an address that allows reading. In the case where the target address is an address allowing reading, the circuit system 940 reads data from a register of the second peripheral module 932 corresponding to the target address through the third bus 961. After reading the data, the circuit system 940 generates a bus command corresponding to the read command, and transmits the bus command to the bus interface circuit 910. Bus interface circuit 910 sends the bus command to the host processor to cause the host processor to receive the bus command to obtain the read data. In some examples, where the target address is a read-inhibit address, circuitry 940 transmits an interrupt signal to processor 920 through an interrupt signal line between circuitry 940 and processor 920 to notify processor 920 that the host processor requests access to a read-inhibit register.

In step S1003, the first peripheral module 931 is accessed by the processor 920 through the second bus 952. In this embodiment, the processor 920 reads data from registers of the first peripheral module 931 through the second bus 952. The processor 920 may also write data to registers of the first peripheral module 931 through the second bus 952.

In step S1004, the second peripheral module 932 is accessed by the processor 920 through the third bus 961. In some examples, accessing, by the processor 920, the second peripheral module 932 via the third bus 961 may include: the registers of the second peripheral module 932 are read and/or written to by the processor 920 via a third bus 961 access.

In some embodiments, the interrupt information for the second peripheral module 932 is sent by the processor 920 to the circuitry 940 over a bus between it and the circuitry 940. Interrupt information is sent by circuitry 940 to the host processor through bus interface circuit 910.

An example of the processor 920 sending the interrupt information of the second peripheral module 932 to the host processor is described below as an embodiment. The processor 920 detects interrupt information of the second peripheral module 932. Processor 920 sends the detected interrupt information to circuitry 940 via a bus between it and circuitry 940. The circuit system 940 generates a bus command corresponding to the interrupt information, and transmits the generated bus command to the bus interface circuit 910. Bus interface circuit 910 sends the bus command to the host processor to cause the host processor to receive the bus command to obtain the interrupt information. As an example, the host processor, upon acquiring the interrupt information, responds to the embedded control circuitry based on the interrupt information. In some examples, the host processor initiates a process to write data to a register of the second peripheral module 932 corresponding to the interrupt information based on the interrupt information. In some examples, the host processor initiates a process to read data from a register of the second peripheral module 932 corresponding to the interrupt information based on the interrupt information.

The embedded control circuit of the direct memory access and shared interface of the exemplary embodiments of the present disclosure is described below using an eSPI bus as an example, and the host processor and the embedded control circuit communicate with each other through the eSPI bus.

Fig. 11 shows a schematic block diagram of a direct memory access and shared interface-based embedded control circuit using an eSPI bus according to an exemplary embodiment of the present disclosure, and as shown in fig. 11, the embedded control circuit 1100 includes: an eSPI slave module 1110 for communicating with a host processor, a processor 1120, one or more first peripheral modules 1131, one or more second peripheral modules 1132, circuitry 1140 and a bus matrix 1150. The plurality of first peripheral modules 1131 are labeled 1131-1 to 1131-n in fig. 11, and the plurality of second peripheral modules 1132 are labeled 1132-1 to 1132-m in fig. 11. In this embodiment, a bus matrix is used, and the embodiment will be described with reference to fig. 11.

Each of the first peripheral modules 1131 includes a first interface and a second interface. (localbus) is connected between the first interface of each first peripheral module 1131 and the eSPI slave module 1110. The second interface of each first peripheral module 1131 is connected to an APB bus, the processor 1120 is connected to the bus matrix 1150, and the APB bus is connected to the bus matrix via a first bridge and a first fast bus, so as to connect the second interface of each first peripheral module 1131 to the processor 1120. An eSPI slave module 1110 configured to access the first peripheral module 1131 over the local bus. The processor 1120 is configured to access the first peripheral module 1131 via the bus matrix, the first fast bus, the first bridge, and the APB bus.

The circuitry 1140 is connected to a DMA bus, which is connected to the bus matrix 1150, the second peripheral module 1132 is connected to a second fast bus, which is connected to the bus matrix, and the second peripheral module 1132 is connected to the circuitry 1140 via the DMA bus, the bus matrix 1150 and the second fast bus. The processor 1120 is coupled to the bus matrix, and a second peripheral module 1132 is coupled to the processor 1120 via the bus matrix 1150 and a second fast bus. Circuitry 1140 configured to communicate with the host processor through the eSPI slave 1110 accesses the second peripheral module 1132 through the DMA bus, the bus matrix 1150, and the second fast bus based on commands from the host processor. In this embodiment, the circuit system 1140 acts as a master device, the second peripheral module 1132 acts as a slave device, and the second peripheral module 1132 may respond to various bus commands of the circuit system 1140. The processor 1120 accesses the second peripheral module 1132 through the bus matrix 1150 and the second fast bus. In this embodiment, the processor 1120 may serve as a master device, the second peripheral module 1132 may serve as a slave device, and the second peripheral module 1132 may respond to various bus commands of the processor 1120.

In this embodiment, some of the second peripheral modules 1132 may be directly connected to the second fast bus, for example, the second peripheral module 1132-1 shown in fig. 11, and examples of the second peripheral module 1132 may include a PD/TypeC interface and the like. Some of the second peripheral modules 1132 may be connected to the second fast bus through a second bridge, for example, the second peripheral modules 1132-2 to 1132-m shown in fig. 11, and examples of the second peripheral modules 1132-2 to 1132-m include an atmosphere lamp control module, a breath lamp control module, and the like. It should be understood that the embodiment is not limited to whether the second peripheral module 1132 is connected to the second fast bus via a bridge.

In this embodiment, the first peripheral module 1131 may refer to the descriptions of fig. 1, fig. 2, and fig. 3 in the present disclosure, which are not described herein again. In this embodiment, the circuit system 1140 and the second peripheral module 1132 may refer to the descriptions of fig. 4, fig. 6, fig. 7, and fig. 8, which are described in the present disclosure, and are not repeated herein.

In this embodiment, the host processor can access the first peripheral module 1131 through the eSPI slave module 1110 and the local bus. The host processor can also access a second peripheral module 1132 through the eSPI slave 1110, circuitry 1140, the DMA bus, the bus matrix 1150, and a second fast bus. An embodiment in which the embedded control circuit 1100 distinguishes accesses by the host processor to the first peripheral module 1131 and the second peripheral module 1132 is described below.

In some embodiments, eSPI slave module 1110 is configured to: determining whether the host processor accesses the first peripheral module 1131 or the second peripheral module 1132 based on the accessed target address, and in the case where the host processor accesses the first peripheral module 1131, accessing the first peripheral module 1131 through the local bus; in the event that the host processor accesses the second peripheral module 1132, the host processor's access command is forwarded to circuitry 1140. Circuitry 1140 accesses a second peripheral module 1132 via the DMA bus, bus matrix 1150, and second fast bus based on an access command from the host processor.

In some embodiments, circuitry is configured to 1140: determining whether the host processor accesses the second peripheral module 1132 based on the accessed target address; in the case where the host processor accesses the second peripheral module 1132, the second peripheral module 1132 is accessed through the DMA bus, the bus matrix 1150, and the second fast bus based on a command of the host processor.

In some embodiments, each first peripheral module 1131 is configured to: determining whether the host processor accesses itself based on the accessed target address; in the case of a host processor access to itself, the host processor access is responded to.

The embodiment of the disclosure provides an embedded control circuit with double bus interfaces.

Fig. 12 shows a schematic block diagram of an embedded control circuit of a dual bus interface according to an exemplary embodiment of the present disclosure, and as shown in fig. 12, the embedded control circuit 1200 includes: one or more peripheral modules 1230; a processor 1220 coupled to one or more peripheral modules 1230; a first bus interface circuit 1211 coupled to one or more peripheral modules 1230; a second bus interface circuit 1212 coupled to one or more peripheral modules 1230; bus interface selection circuitry 1213 is configured to communicate with the host processor and operatively couple either first bus interface circuitry 1211 or second bus interface circuitry 1212 to the host processor.

In this embodiment, first bus interface circuit 1211 or second bus interface circuit 1212 may communicate with a host processor using various types of bus interfaces, including but not limited to an LPC bus, an SPI bus, an eSPI bus, and the like. Illustratively, first bus interface circuit 1211 can be an LPC circuit and second bus interface circuit 1212 can be an eSPI circuit, whereby embedded control circuit 1200 can communicate with a host processor over an LPC bus protocol or an eSPI bus protocol. It should be appreciated that any combination of two bus protocols may be utilized for first bus interface 1211 and second bus interface 1212, and this embodiment is not limited thereto.

In some embodiments, bus interface selection circuitry 1213 is configured to connect either first bus interface circuitry 1211 or second bus interface circuitry 1212 to the host processor based on the initialization configuration. Through the initial configuration, the embedded control circuit 1200 is configured to communicate with the host processor through one of the first bus interface circuit 1211 and the second bus interface circuit 1212. Bus interface selection circuit 1213 connects one of first bus interface circuit 1211 and second bus interface circuit 1212 to the host processor based on the initialized configuration, thereby communicating with the host processor through the configured bus interface circuit.

In some embodiments, peripheral module 1230 includes: the one or more first peripheral modules, each of the one or more first peripheral modules including a first interface and a second interface. The first interface of each first peripheral module is connected with the first bus interface circuit and the second bus interface circuit through a first bus; and the second interface of each first peripheral module is connected with the processor through a second bus. A first bus interface circuit 1211 and a second bus interface circuit 1212 configured to access one or more first peripheral modules via a first bus. A processor 1220 configured to access one or more first peripheral modules over the second bus.

In this embodiment, the first peripheral module can refer to the descriptions of fig. 1, fig. 2, and fig. 3 in the disclosure, which are not described herein again.

In some embodiments, peripheral module 1230 includes: one or more second peripheral modules. The embedded control circuit further comprises: circuitry is provided. One or more second peripheral modules are connected with the circuit system through a third bus. One or more second peripheral modules are coupled to the processor 1120 via a third bus. Circuitry configured to communicate with the host processor via the first bus interface circuit 1211 or the second bus interface circuit 1212, to access one or more second peripheral modules via the third bus based on commands of the host processor; a processor 1220 configured to access one or more second peripheral modules through the third bus.

In this embodiment, the circuit system and the second peripheral module can refer to the descriptions of fig. 4, fig. 6, fig. 7, and fig. 8, which are described in the present disclosure, and are not repeated herein.

In some embodiments, peripheral modules 1230 include one or more first peripheral modules and one or more second peripheral modules. In this embodiment, the host processor can access the first peripheral module through the first bus interface circuit 1211 or the second bus interface circuit 1212 and the first bus. The host processor may also access the second peripheral module through the first bus interface circuit 1211 or the second bus interface circuit 1212, the circuitry, and the third bus. An embodiment in which the embedded control circuit 1200 distinguishes accesses by the host processor to the first peripheral module and the second peripheral module is described below.

As an embodiment, first bus interface circuit 1211 and/or second bus interface circuit 1212 are configured to: determining whether the host processor accesses the first peripheral module or the second peripheral module based on the accessed target address; in the event that the host processor accesses one or more first peripheral modules, accessing the one or more first peripheral modules over the first bus; in the event that the host processor accesses one or more second peripheral modules, the access commands of the host processor are forwarded to the circuitry. The circuit system accesses the second peripheral module via the third bus.

As one embodiment, the circuitry is configured to: determining whether the host processor accesses one or more second peripheral modules based on the accessed target address; in the case where the host processor accesses the one or more second peripheral modules, the one or more second peripheral modules are accessed through the third bus based on a command of the host processor.

The embedded control circuit of the exemplary embodiment of the present disclosure is described below with respect to LPC and eSPI buses as examples, and the host processor communicates with the embedded control circuit via the eSPI or LPC bus.

Fig. 13 shows a schematic block diagram of an embedded control circuit of an LPC-eSPI dual bus interface according to an exemplary embodiment of the present disclosure, and as shown in fig. 13, an embedded control circuit 1300 includes: a peripheral module; a processor 1320 connected to the peripheral module; an LPC slave module 1311 connected to one or more peripheral modules; an eSPI slave module 1312 connected to one or more peripheral modules; an LPC-eSPI interface selector 1313 configured to communicate with the host processor and operatively connect either LPC slave 1311 or eSPI slave 1312 to the host processor; circuitry 1340. Wherein, the peripheral module includes: one or more first peripheral modules 1331 and one or more second peripheral modules 1332, labeled in fig. 13 as first peripheral modules 1331-1 through 1331-n and second peripheral modules 1332-1 through 1332-m.

In some embodiments, LPC-eSPI interface selector 1313 is configured to connect LPC slave 1311 or eSPI slave 1312 to the host processor based on the initialization configuration. Initially configured, the embedded control circuit 1300 is configured to communicate with the host processor through one of the LPC slave 1311 and the eSPI slave 1312. LPC-eSPI interface selector 1313 connects one of LPC slave 1311 and eSPI slave 1312 to the host processor based on the initialization configuration, thereby communicating with the host processor through the configured bus interface circuit.

In the present embodiment, each of the first peripheral modules 1331 includes a first interface and a second interface. The first interface of each first peripheral module 1331 is connected to the LPC slave module 1311 and the eSPI slave module 1312 through a local bus (localbus). The second interface of each first peripheral module 1331 is connected to the processor through an APB bus, a first bridge, a first fast bus, and a bus matrix 1350. LPC slave 1311 and eSPI slave 1312 access one or more first peripheral modules 1331 via the local bus. The processor 1320 accesses the first peripheral module 1331 through the first fast bus, the first bridge, and the APB bus of the bus matrix 1350.

In this embodiment, the first peripheral module 1331 may refer to the descriptions of fig. 1, fig. 2 and fig. 3 in the foregoing description, which are not repeated herein.

In this embodiment, the second peripheral module 1332 is connected to the circuitry 1340 via a DMA bus, the bus matrix 1350 and a second fast bus. The second peripheral module 1332 is coupled to the processor 1320 via a bus matrix 1350 and a second fast bus. Circuitry 1340 communicates with the host processor via LPC slave 1311 or eSPI slave 1312, and processor 1320 accesses second peripheral module 1332 via DMA bus, bus matrix, and second fast bus based on host processor commands via bus matrix 1350, second fast bus.

In some embodiments, the processor 1320 may also access circuitry 1340 through a bus matrix 1350, a first bridge, an APB bus. Information may be transferred between the processor 1320 and the circuitry 1340 via the bus matrix 1350, the first bridge, and the APB bus, for example, the processor 1320 may transfer permission information to access the second peripheral module 1332 to the circuitry 1340 over the lines.

In this embodiment, the circuit system 1340 and the second peripheral module 1332 can refer to the descriptions of fig. 4, fig. 6, fig. 7, and fig. 8, which are described in the present disclosure, and are not repeated herein.

In this embodiment, the host processor may access the first peripheral module 1331 through either the LPC slave 1311 or the eSPI slave 1312 and the local bus. The host processor may also access the second peripheral module 1332 through an LPC slave 1311 or eSPI slave 1312, circuitry 1340, and a DMA bus, bus matrix 1350, and a second fast bus. An embodiment in which the embedded control circuit 1300 distinguishes accesses by the host processor to the first peripheral module 1331 and the second peripheral module 1332 is described below.

As an embodiment, LPC slave 1311 and/or eSPI slave 1312 is configured to: determining whether the host processor accessed the first peripheral module 1331 or the second peripheral module 1332 based on the accessed target address; in the case of a host processor accessing one or more first peripheral modules 1331, accessing one or more first peripheral modules 1331 via the first bus; in the event that the host processor accesses one or more second peripheral modules 1332, the host processor's access commands are forwarded to circuitry 1340. The circuitry 1340 accesses the second peripheral module 1332 via the DMA bus, the bus matrix 1350, and the second fast bus.

As an embodiment, circuitry 1340 is configured to: determining whether the host processor accesses one or more second peripheral modules based on the accessed target address 1332; in the case where the host processor accesses the one or more second peripheral modules 1332, the one or more second peripheral modules 1332 are accessed via the DMA bus, the bus matrix 1350, and the second fast bus based on commands from the host processor.

As an embodiment, each first peripheral module 1331 is configured to: determining whether the host processor accesses itself based on the accessed target address; in the case of a host processor access to itself, the host processor access is responded to.

The exemplary implementation of the present disclosure also provides a chip, which may include the embedded control circuit described above in the present disclosure.

Aspects of the present disclosure may be integrated into an electronic device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a Global Positioning System (GPS) device; a mobile phone; a cellular telephone; a smart phone; session Initiation Protocol (SIP) phones; a tablet computer; a tablet phone; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; personal Digital Assistants (PDAs); a monitor; a computer monitor; a television set; a tuner; a radio; satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; digital Video Disc (DVD) players; a portable digital video player; a motor vehicle; a vehicle component; an avionics system; an unmanned aerial vehicle; and multi-rotor aircraft.

The above description is only exemplary of the present disclosure and should not be taken as limiting the disclosure, and any modifications, equivalents, and simple improvements made in the spirit of the present disclosure should be included in the scope of the present disclosure.

Claims

1. An embedded control circuit, comprising:

one or more peripheral modules;

a processor connected with the one or more peripheral modules;

a first bus interface circuit coupled to the one or more peripheral modules;

the second bus interface circuit is connected with the one or more peripheral modules;

a bus interface selection circuit configured to communicate with a host processor and operatively connect the first bus interface circuit or the second bus interface circuit to the host processor.

2. The embedded control circuit of claim 1, wherein the bus interface selection circuit is configured to connect the first bus interface circuit or the second bus interface circuit to the host processor based on an initialization configuration.

3. The embedded control circuit of claim 1, wherein the one or more peripheral modules comprise: one or more first peripheral modules, each of the one or more first peripheral modules comprising a first interface and a second interface;

wherein, the embedded control circuit further comprises: a first bus connected between the first interface of each first peripheral module and the first bus interface circuit and the second bus interface circuit; the second bus is connected between the second interface of each first peripheral module and the processor;

wherein the first bus interface circuit and the second bus interface circuit are configured to access the one or more first peripheral modules via the first bus; the processor configured to access the one or more first peripheral modules over the second bus.

4. The embedded control circuit of claim 3, wherein at least one of the first peripheral modules comprises: arbitration logic circuitry configured to:

disconnecting the second interface of the first peripheral module from the second bus when the first peripheral module is accessed by the host processor; and/or

Disconnecting the first interface of the first peripheral module from the first bus when the first peripheral module is accessed by the processor.

5. The embedded control circuit of claim 4, wherein the arbitration logic circuit is further configured to:

connecting a second interface of the first peripheral module with the second bus when the first peripheral module is released by the host processor; and/or

And when the first peripheral module is released by the processor, connecting the first interface of the first peripheral module with the second bus.

6. The embedded control circuit of any one of claims 1-5, wherein the one or more peripheral modules comprise: one or more second peripheral modules;

wherein, the embedded control circuit further comprises:

circuitry;

a third bus connected between the one or more second peripheral modules and the circuitry and connected between the one or more second peripheral modules and the processor;

wherein the circuitry is configured to communicate with the host processor via the first bus interface circuit or the second bus interface circuit, to access the one or more second peripheral modules via the third bus based on a command of the host processor; the processor configured to access the one or more second peripheral modules over the third bus.

7. The embedded control circuit of claim 6, wherein the first bus interface circuit and/or the second bus interface circuit is configured to:

determining whether the first peripheral module or the second peripheral module is accessed by the host processor based on the accessed target address;

accessing the one or more first peripheral modules over the first bus if the host processor accesses the one or more first peripheral modules;

forwarding an access command of the host processor to the circuitry if the host processor accesses the one or more second peripheral modules.

8. The embedded control circuit of claim 6, wherein the circuitry is configured to:

determining whether the host processor accesses the one or more second peripheral modules based on the accessed target address;

in a case where the host processor accesses the one or more second peripheral modules, the one or more second peripheral modules are accessed through the third bus based on a command of the host processor.

9. The embedded control circuit of claim 6, further comprising: a fourth bus connected between the processor and the circuitry.

10. The embedded control circuit of claim 9, wherein the processor is configured to: sending interrupt information for the one or more second peripheral modules to the circuitry over the fourth bus; the circuitry is configured to: sending the interrupt information to a host processor through the first bus interface circuit or the second bus interface circuit.

11. The embedded control circuit of claim 6, wherein the circuitry is configured to: accessing the one or more second peripheral modules based on preconfigured permissions.

12. The embedded control circuit of claim 11, further comprising: an interrupt signal line connected between the processor and the circuitry; the circuitry is configured to: transmitting an interrupt signal to the processor through the interrupt signal line if a register of a second peripheral module accessed by the host processor is configured to disable access.

13. The embedded control circuit of claim 3 or 6, wherein at least one of the first peripheral modules is configured to:

determining whether the host processor accesses the first peripheral module based on the accessed target address;

responding to the access of the host processor in the case that the host processor accesses the first peripheral module.

14. A chip comprising an embedded control circuit according to any one of claims 1 to 13.

15. An electronic device, comprising: an embedded control circuit according to any one of claims 1 to 13 or a chip according to claim 14.