CN104380274A - Optimized link training and management mechanism - Google Patents

Optimized link training and management mechanism Download PDF

Info

Publication number
CN104380274A
CN104380274A CN201380021347.8A CN201380021347A CN104380274A CN 104380274 A CN104380274 A CN 104380274A CN 201380021347 A CN201380021347 A CN 201380021347A CN 104380274 A CN104380274 A CN 104380274A
Authority
CN
China
Prior art keywords
link
physical
signal
phy
sideband
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201380021347.8A
Other languages
Chinese (zh)
Other versions
CN104380274B (en
Inventor
M·瓦格
D·J·哈里曼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/477,310 external-priority patent/US8437343B1/en
Application filed by Intel Corp filed Critical Intel Corp
Priority to CN201610857743.XA priority Critical patent/CN107092335B/en
Publication of CN104380274A publication Critical patent/CN104380274A/en
Application granted granted Critical
Publication of CN104380274B publication Critical patent/CN104380274B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3253—Power saving in bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13003—Constructional details of switching devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)

Abstract

In one embodiment, a converged protocol stack can be used to unify communications from a first communication protocol to a second communication protocol to provide for data transfer across a physical interconnect. This stack can be incorporated in an apparatus that includes a protocol stack for a first communication protocol including transaction and link layers, and a physical (PHY) unit coupled to the protocol stack to provide communication between the apparatus and a device coupled to the apparatus via a physical link. This PHY unit may include a physical unit circuit according to the second communication protocol. Other embodiments are described and claimed.

Description

The link training optimized and administrative mechanism
Technical field
Embodiment relates to interconnection technique.
background
In order to provide the communication in system between distinct device, use the interconnection mechanism of certain type.Depend on system embodiment, various interconnection is like this possible widely.Often in order to enable two equipment communicate mutually, they share common communication protocol
A kind of is according to Based PC I Express for the typical communication protocol of communication between devices in computer system tMnormative foundation specification version 3.0 (publication on November 18th, 2010) (hereinafter referred to as PCIe tMspecification) peripheral assembly high speed interconnect (the PCI Express of link tM(PCIe tM)) communication protocol.This communication protocol is an example of load/store I/O (IO) interconnection system.Usually perform the communication of described equipment room with very high speed serial according to this agreement.When developing PCIe under the background at desk-top computer tMduring communication protocol, in order to realize the object of maximum performance when not considering power efficiency, develop the various parameters about this agreement.As a result, its many feature cannot be reduced to the lower-wattage solution that can be integrated in mobile system.
Except these power problems about conventional load/store communication protocol, existing link management scheme is usually very complicated and relate to a large amount of state, causes the lengthy process changed between executing state.Be partly due to existing link management mechanism, it is developed to understand the such as multiple different form factors dictate such as connector, different system merging.Such example is according to PCIe tMthe link management of communication protocol.
Embodiment
Embodiment can provide I/O (IO) interconnection technique, and it has low-power, load/store framework, and be particularly useful for the cell phone comprising such as smart phone, flat computer, electronic reader, super tMdeng mobile device in use.
In embodiments, the protocol stack for given communication protocol can use together with the physical location of different communication protocol or at least one physics (PHY) unit different with the physical location for given communication protocol.Physical location comprises logical layer and physics or electrical layer, physics or electrical layer provide the reality of information signal, the communication of physics in interconnection (such as linking the link of two separate semiconductor tube cores), and two separate semiconductor tube cores can be two semiconductor elements in the separate package that single integrated circuit (IC) encapsulates or such as couples via circuit board route, trace etc.In addition, described physical location can perform framing (framing)/solution frame (deframing) of packet, performs link training and initialization, and the packet of process for receiving from physical interconnections or be delivered in physical interconnections.
Although different embodiments may be had, in one embodiment, described protocol stack may have the conventional communication protocol based on personal computer (PC) (such as according to PCI Express tMnormative foundation specification version 3.0 (publication on November 18th, 2010) (hereinafter referred to as PCIe tMspecification) peripheral assembly high speed interconnect (PCI) Express tM(PCIe tM)) communication protocol), the further version of application protocol expansion, or another this quasi-protocol, described physical location is not based on described PCIe simultaneously tMcommunication protocol.For the object realizing low-power operation, this physical location can be specifically designed the substantially immovable PCIe of permission tMupper protocol stack and this low-power physical circuit merge.Like this, for ease of being merged into the portable of low-power operation and in the form factor of other not Based PC, can PCIe being utilized tMthe traditional infrastructure widely of communication protocol.But scope of the present invention is not limited thereto, in one embodiment, this physical location can be by the adaptive physical location of mobile platform (such as according to the M-PHY specification version 1.00.00 of mobile industrial processor interface (MIPI) alliance (it is the group for mobile computing device established standards)---the so-called M-PHY on February 8th, 2011 (on April 28th, 2011 ratify MIPI Board) (being hereafter MIPI specification)).But, other low-power physical location (such as basis is such as being coupled in the individual dice in multi-chip package other low-power specification together) can be used, or the low-power solution of customization.As used herein, term " low-power " means to be in the power consumption levels lower than conventional PC system, and it can be applied to various movement and portable equipment widely.As an example, " low-power " can be that the power consumed is less than conventional PCIe tMthe physical location of physical location.
Like this, by by traditional PCIe tMprotocol stack is polymerized with dissimilar physical location, re-use in a large number for PCIe tMthe traditional components of exploitation can be used to be merged into mobile or other is portable or in low-power platform.
Embodiment can also utilize following understanding: i.e. existing load/store IO technology, especially PCIe tMbe designed with following object: realize maximum performance when power efficiency is not subject matter, and therefore can not be reduced to low power applications.By the part of conventional load/store protocol stack and the physical location of low-power design being combined, embodiment can retain PCIe tMperformance advantage, simultaneously in power, reach best at equipment and platform rank.
Like this, embodiment can be and the ubiquitous PCIe with large traditional infrastructure tMthe software of framework compatibility.In addition, embodiment can also realize direct PHY and re-use mobile design PHY, such as M-PHY.Like this, the method that can utilize the highly efficient power/bit of transmission and become electromagnetic interface/radio frequency interface (EMI/RFI) with open arms realizes low active and idle power, because PHY can not disturb the clock rate operation of associated radio (conventional RF (such as, 1.8,1.9,2.4 kilo-mega cycles per seconds (GHz)) of not interfering typical radio solution to operate with it because of the harmonic wave for the clock rate of PHY or other such radio frequencies).
Embodiment can provide the framework of link training and the administrative mechanism (LTSSM) realizing optimizing to improve further; The current control optimized and retry cushion and administrative mechanism; For changing the framework agreement of link operation pattern; Fast hardware support equipment state is preserved and is recovered; And for having the unified sideband mechanism of the link management supported in optional band.
In embodiments, PCIe tMaffairs and data link layer can be implemented as the part of the protocol stack with limited amendment to take into account different link-speeds and asymmetric link.In addition, link training and the management of correction can be provided, to comprise the support of and dynamic bandwidth scalability unified to multichannel communication, asymmetric link configuration, sideband.Embodiment can provide further to existing Based PC Ie tMand based on non-PCIe tMlogic and such as M-PHY logic and circuit and so on circuit between the support of bridge joint.
This layered approach makes existing software stack (such as, operating system (OS), virtual machine manager and driver) energy gum seamless operation in different Physical layers.The impact of described data link and transaction layer is minimized and can comprises the relevant timer of renewal to upgrade answer frequency, playback timer etc.
Therefore, each embodiment can limit PCIe tMsome dirigibilities provided in system, because this dirigibility is in some cases at PCIe tMsome complicacy can be created in system and other both system.Really so, because these two kinds of agreements both provide realization namely insert the great flexibility namely broadcasting ability.On the contrary, each embodiment can customize the solution of the amount of miniaturized design dirigibility, because when being integrated into middle to fixed system (SOC (system on a chip) (SoC) such as interconnected with another integrated circuit (IC)), there is known and fixing configuration.Because be known realizing in the accurate configuration existed, when both the equipment of SoC and connection is all affixed in platform, such as, be welded to the circuit board of this system, namely these equipment broadcast ability without the need to namely inserting, and therefore may not need PCIe tMor the communication protocol of other Based PC intrinsic, distinct device can be seamlessly merged into have namely to insert the larger dirigibility namely broadcast in the system of ability.
As an example, described SoC can serve as the root complex (rootcomplex) implemented in an IC, and to be couple to be the 2nd IC of radio solution, and it can comprise the one or more equipment in multiple Wireless Telecom Equipment.The scope of such equipment can from such as according to bluetooth tMthe low power, short range communication system of specification, such as according to given electrically and the so-called WiFi of EEA Eelectronic Eengineering Association (IEEE) 802.11 standard tMthe local wireless communication of system, to the high power wireless system of such as given cellular communication protocol (such as 3G or 4G communication protocol).
With reference now to Fig. 1, show the high-level block diagram of the protocol stack for communication protocol according to the embodiment of the present invention.As shown in fig. 1, stack 100 can be the combination of semiconductor subassembly (such as IC) interior software, firmware and hardware, for providing described semiconductor equipment and the process of another equipment room data communication that couples with it.In the embodiment in figure 1, show the high-level view starting from high-level software 110, high-level software 110 can be to various types of softwares that fixed platform performs.This high-level software can comprise operating system (OS) software, firmware, application software etc.The data that will transmit via interconnection 140 by each layer transmission of protocol stack, can illustrate usually in Fig. 1, and interconnection 140 can be the given physical interconnections described semiconductor equipment and another assembly coupled.As can be seen, this protocol stack each several part can be conventional PCIe tMthe part of stack 120, and transaction layer 125 and data link layer 128 can be comprised.Usually, transaction layer 125 for generating the transaction layer packet (TLP) based on the packet responded that can be request or be separated by the time, thus allows this link to carry other business, and target device collects the data being used for described response simultaneously.Described transaction layer processes fiduciary current control further.Therefore, transaction layer 125 provides the interface between the treatment circuit of equipment and interconnect architecture, such as data link layer and Physical layer.In this respect, the major responsibility of described transaction layer is the assembling Sum decomposition of packet (that is, transaction layer packet (TLP)) and processes fiduciary current control.
Then, data link layer 128 can sort the TLP that transaction layer generates, and guarantees reliable delivery (comprise process bug check) and the reply process of TLP between two end points.Therefore, link layer 128 serves as the interstage between transaction layer and Physical layer, and is provided for the reliable mechanism being exchanged TLP by link at two inter-modules.The side of described link layer receives the TLP assembled by described transaction layer, application identities accords with, calculate and application error detection of code (such as circulation recover code (CRC)), and the TLP of amendment is submitted to Physical layer transfer to external unit for across physical link.
In data link layer 128 process after, can gum by data packets to PHY unit 130.Usually, PHY unit 130 can comprise low-power PHY134, and it can comprise logical layer and physics (comprising electrically) sublayer.In one embodiment, the Physical layer represented by PHY unit 130 for physically by data packet transmission to external unit.Described Physical layer comprises and prepares the transmission zone of going-out information for transmission and identified before the information of reception is delivered to link layer and prepare its receiver section.To be serialized and the symbol being transferred to external unit is supplied to described transmitter.Serialization symbol from external unit is supplied to described receiver, and received signal is transformed to bit stream by receiver.The serial of described bit stream solution is supplied to logical sub-blocks.
In one embodiment, low-power PHY134 (its can gum be special exploitation or the given low-power PHY by another PHY adaptation of such as M-PHY and so on) can provide and transmit for along interconnection 140 process of packing data.As seen further in Fig. 1, link training and administration and supervision authorities 132 (herein also referred to as link manager) also may reside in PHY unit 130.In embodiments, can comprise can according to such as PCIe for link manager 132 tMthe certain logic of another communication protocol enforcement of agreement and processing example are as above-mentioned PCIe tMthe routine of protocol stack and there is the proprietary logic of physics PHY134 interface of different agreement.
In the embodiment in figure 1, interconnection 140 can be embodied as differential lines pair, and differential lines is to being two pairs of unidirectional lines.In some embodiments, many group differential pairs can be used for increasing bandwidth.It should be noted that according to PCIe tMcommunication protocol, requires that the number of differential pair on each direction is identical.But according to each embodiment, can provide the right of different number in each direction, this allows, and operation is more efficient, power is lower.The stack of this whole polymerization and link 140 can be called mobile quick PCIe tMinterconnection or link.Although high-levelly to illustrate with this in the embodiment in figure 1, be appreciated that scope of the present invention is not limited thereto.That is, be appreciated that the view shown in Fig. 1 just about by the protocol stack from transaction layer of Physical layer and high-level software, and other circuit various of not shown SoC or comprise other semiconductor equipment of this stack.
With reference now to Fig. 2, the block diagram of the SoC according to the embodiment of the present invention is shown.As shown in Figure 2, SoC200 can be the platform for implementing any type in various types of SoC, scope from such as smart phone, personal digital assistant (PDA), flat computer, notebook, super tMdeng and so on relatively little low-power portable equipment to the more senior SoC that can implement in high-level system.
As seen in Figure 2, SoC200 can comprise one or more kernel 210 0-210 n.Therefore in embodiments, may have multinuclear SoC, described kernel can be all the homogeneity kernel with given framework, such as orderly or out-of-order processors.Such as, such as, or can there is heterogeneous kernel, some relatively little low-power kernel, has the kernel of orderly framework; Have the additional kernel of existence, this additional kernel can have larger and more complicated framework, such as unordered framework.Data communication between other assembly that protocol stack realizes the one or more and system in these kernels.As seen, this stack can comprise software 215, its application layer software that can be higher level software (such as OS, firmware) and perform on one or more kernel.In addition, described protocol stack comprises transaction layer 220 and data link layer 230.In embodiments, these affairs and data link layer can have such as PCIe tMthe given communication protocol of agreement.Certainly, can exist in other embodiment such as according to the layer of the different agreement stack of USB (universal serial bus) (USB) protocol stack.And, in some embodiments, can by the multiplexed low-power PHY circuit as herein described of existing replacement protocol stack.
Still with reference to figure 2, this protocol stack can be couple to physical location 240 then, and physical location 240 can comprise multiple physical locations that can provide communication via many interconnection.In one embodiment, the first physical location 250 can be low-power PHY unit, and it can correspond to the M-PHY according to MIPI specification in one embodiment, for providing communication via main interconnection 280.In addition, sideband (SB) PHY unit 244 can be there is.In an illustrated embodiment, this sideband PHY unit can interconnect via sideband and 270 provide communication, and sideband interconnection 270 can be the unified sideband for such as providing some side information with the data rate being slower than the main interconnection 280 being couple to a PHY250.In certain embodiments, each layer of described protocol stack can have the separation sideband being couple to the communication that this SB PHY244 interconnects along this sideband with realization.
In addition, PHY unit 240 may further include the SB link manager 242 that can be used in control SB PHY244.In addition, link training and state supervisor 245 can be there is, and it can be used in the protocol stack with the first communication protocol being fitted to a PHY250 with second communication agreement, and provide the entirety for a PHY250 and interconnection 280 to control.
As further seen, various assembly can be there is in a PHY250.More specifically, transmitter and acceptor circuit (i.e. TX253 and RX254) can be there is.Usually, this circuit can be used for performing serialization operation, separating serial operation and transmit via main interconnection 280 and receive data.Preservation state manager 251 can be there is, and may be used for when it is in low power state preserving the configuration about a PHY250 and other status information.And, scrambler 252 can be there is, for such as performing line coding according to 8b/10b agreement.
As Fig. 2 further seen by, mechanical interface 258 can be there is.This mechanical interface 258 can be given interconnection, for providing the communication from root complex 200, and more specifically via main interconnection 280 arrive/from the communication of a PHY250.In embodiments, this mechanical connection can utilize the pin of the semiconductor equipment of such as ball grid array (BGA) or other surface mount and so on, or passing hole connects plating.
Except these Primary communication mechanism, additional communication interface can utilize low-power serial (LPS) PHY unit 255, low-power serial (LPS) PHY unit 255 couples between kernel 210 and one or more external equipment 260a-c via the separation stack comprising software layer 216, transaction layer 221 and link layer 231, and described external equipment energy gum is the various low data rate peripherals of such as sensor, accelerometer, temperature sensor, GPS (GPS) circuit, compassing circuit, touch screen circuitry, keyboard circuit, mouse circuit etc. and so on.
It should be noted that in embodiments, both sideband interconnection 270 or main interconnection 280 can couple by gum between SoC200 and second half conductor assembly (such as another IC of such as multi-band radio solution and so on).
Again, although the diagram of Fig. 2 is relatively high-level, can change.Such as, multiple low-power PHY can be provided such as to realize the data communication of higher rate via many channels, wherein each channel is associated with independently PHY.With reference now to Fig. 3, the block diagram of physical location is according to another embodiment of the present invention shown.As shown in Figure 3, physical location 300 comprises link training and state supervisor 310.This state supervisor can be described above, and can be logical collection, has the protocol stack of the first communication protocol and the physical location interface with second (such as different) communication protocol for enabling.
Seen by Fig. 3 further, link training and state supervisor 310 can with multiple M-PHY320 0-320 ncommunication.By providing this type of more than one PHY, the data communication of higher rate can be carried out.It should be noted that although the logic that each M-PHY shown in Fig. 3 can comprise some numbers occurs for enabling its individual independent communication, controlling the entirety of the communication of these different M-PHY can via link training and state supervisor 310.And, although be appreciated that multiple M-PHY shown in Fig. 3, in other embodiments, multiple PHY unit of another type can be there are, and other multiple heterogeneous PHY unit can be provided.It should be noted that each M-PHY unit can be used as the part of unique logic link, or be used in group, wherein group is associated with single logical link.Each equipment can consume single logical link usually, but single physical equipment can consume multiple logical links in certain embodiments, such as, for providing proprietary link circuit resource for the difference in functionality of multifunctional module.
With reference now to Fig. 4, what illustrate is the block diagram of the further details of the protocol stack illustrated according to the embodiment of the present invention.As shown in Figure 4, stack 400 comprises various layer, comprising: transaction layer 410, data link layer 420 and Physical layer 430.As mentioned above, PCIe can be used tMthe regular transaction of protocol stack and the revision of data link part or this type of stack configure these different layers, to hold, to have between these layers of this first communication protocol and the Physical layer with another communication protocol mutual, and Physical layer can be the M-PHY according to MIPI specification in the fig. 4 embodiment.
As seen in Figure 4, about the transmission direction from protocol stack 400 transmission information, in the usual combination control of transaction layer and data routing are with the transmission packet assembler 412 forming TLP, receive the arrival information such as from other circuit (such as kernel or other processing logic) of SoC to protocol stack.After being assembled into transmission packet, (transmission packet can be have such as 1 to 4096 byte (or to have less maximum permission size in embodiments, such as, 128 or 256) packet), the packet of assembling is supplied to stream controller 414, stream controller 414 based on enqueuing transport ensuing (one or more) TLP required by number determine whether that enough flow control credit can be used, and control packet is injected in data link layer 420.More specifically, to the packet that error detector and serial device 422 provide these to inject, error detector and serial device 422 can generate TLP sequence number and LCRC in one embodiment.Further, data link layer 420 comprises message transfer mechanism 426 further, message transfer mechanism 426 generates the DLLP being used for link management function then, and being couple to data link transmission controller 425, it is the controller function for current control and data link integrality (ACK/NAK) mechanism; It should be noted that this can be subdivided, to make to use different logical blocks to implement these functions.
As further seen, the packet processed is supplied to retry buffering 424, retry buffering 424 preserves the copy of each TLP until by components respond on described link opposite side, note, in practice, this can utilize the more top (in assembler 412 or above) being buffered in stack to implement, and they can be stored in corresponding entry, are transferred to Physical layer 430 until be selected for via data/message selector switch 428.Usually, above-mentioned affairs and data link layer can according to the PCIe of routine tMprotocol stack circuit operation, wherein some amendment will be further described below.
Contrary to Physical layer 430, to much more amendment of some logic module of this layer (such as according to PCIe tMprotocol stack amendment such) can to occur and for providing the interface of the actual physics part to the physical location with another communication protocol.As can be seen, the packet of arrival can be applied to frame generator 432, it increases physical layer frame symbol and is described packet delta frame, and they are supplied to bandwidth/location mapper 434, byte in its shifted data path to generate the calibration of the requirement being used for external transmission thus to adjust wide data path if desired, and is couple to the training aids and jump sequence device 436 that may be used for performing link training and sequence of jumping then.As can be seen, frame generator 432, training aids/serial device 436 and data/sequence selection device 438 all can be couple to physical layer transmission controller 435, and physical layer transmission controller 435 is the Transceiver section of LTSSM and interrelated logic.Frame 436 is the logics for generating physical layer transmission (such as training set (TS) and the sequence collection that jumps).Like this, the packet of framing can be selected and is supplied to physical circuit, is urged in physical interconnections to perform coding, serialization and the serialization signal the packet corresponding to process.In one embodiment, the mapping of signature between different communication protocol can be performed in frame generator 432.
As can be seen, provide many individual channels or passage can to this physical interconnections.In an illustrated embodiment, each physical channel or passage can comprise the independent PHY unit transmission circuit 445 of himself 0-445 j, its each can be the part of the M-PHY unit according to MIPI specification in one embodiment.As described herein, be different from the PCIe of the number matches of transmitter and receiver tM, transmitter and the receiver of different number can be there is.Therefore as can be seen, each transmission circuit 445 can comprise for according to 8b/10b coding to the scrambler of encoding symbols, serialized for encoded symbol serializer and the driver that signal is driven in physical interconnections.As further seen, each passage or channel can with logical block 440 0-440 jbe associated, it can be according to the logical circuit for the MIPI specification of M-PHY, for the channel management physical communication therefore via correspondence.
It should be noted that these multiple passages can be configured to different Rate operation, and embodiment can comprise this type of passage of different number.In addition, passage and the channel speed of different number can be had in transmission and receive direction.Therefore, although the operation of the respective channel of given logical block 440 control PHY445, be appreciated that physical layer transmission controller 435 may be used for controlling to transmit via the Global Information of physical interconnections.It should be noted that in some cases, some very basic functions are performed by the Different Logic be associated with each passage; For situation channel allocation can given more than single link, multiple LTSSM example can be provided; For the link of training, in each assembly controlling transceiver and receiver-side, there is single LTSSM.This entirety controls to comprise power control, link-speeds control, link width control, initialization etc.
Still with reference to figure 4, the arrival information received via physical interconnections can similarly by the reception mechanism transmission via these layers of Physical layer 430, data link layer 420 and transaction layer 410.In the embodiment illustrated in figure 4, each PHY unit may further include receiving circuit, i.e. receiving circuit 455 0-455 k, it is receiving circuit 455 in an illustrated embodiment 0-455 kcan exist for each passage of physical link.It should be noted that in this embodiment, acceptor circuit 455 is different with the number of transmitter circuit 445.As can be seen, the input that can comprise for receiving information of this physical circuit cushions, carries out separating the deserializer of serial and may be used for the demoder of the symbol that decoding transmits with 8b/10b coding to this information.As further seen, each passage or channel can with logical block 450 0-450 kbe associated, logical block 450 0-450 kcan be the logical circuit according to given specification (such as the MIPI specification of M-PHY), for therefore managing the physical communication via respective channel.
Then decoded symbol can be supplied to the logical gate of Physical layer 430, it can comprise elastic buffer 460 as can be seen, and wherein said elastic buffer holds the clock difference on described link between this assembly and another assembly; It should be noted that its position can be shifted precedent as under 8b/10b demoder in each embodiment, or with passage deskew surge combination, and store arrive decoding symbols.Then, this information can be provided to width/location mapper 462, cushion 464 by being supplied to the passage deskew performing deskews across many passages there, and for hyperchannel situation, buffering 464 can between treatment channel the difference of signal skew again to aim at byte.Then, the information via deskew can be provided to Frame Handler 466, and it can eliminate the frame existed in arrival information.As can be seen, Physical layer reception controller 465 can be couple to and control elastic buffer 460, mapper 462, deskew buffering 464 and Frame Handler 466.
Still with reference to figure 4, the packet of recovery can be supplied to receipt message mechanism 478 and error detector, sequence checking device and link level retry (LLR) requester 475.This circuit to the packet execution error rectifying inspection arrived, such as, can be checked by execution CRC check and operation, execution sequence and be asked to carry out link level retry to the packet of garbled-reception.Under receipt message mechanism 478 and error detector/requester 475 both can be in the control of data link reception controller 480.
Still with reference to figure 4, therefore in unit 475, the packet of process can be supplied to transaction layer 410, and is more specifically supplied to stream controller 485, and it performs current control so that they are supplied to packet interpreter 495 to these packets.Packet interpreter 495 performs the explanation to described packet, and they are transmitted to selected destination, other logical circuit of such as given kernel or this receiver.Although high-levelly to illustrate with this in the embodiment of Fig. 4, be appreciated that scope of the present invention is not limited thereto.
It should be noted that PHY440 can use with by the PCIe for transmitting tMthe identical 8b/10b coding supported.Described 8b/10b encoding scheme provides the special symbol of the data symbol be different from for representing character.These special symbols may be used for PCIe tMvarious link management mechanism described in the Physical layer chapters and sections of specification.The use of M-PHY to additional special symbol is described in MIPI M-PHY specification.Embodiment can provide PCIe tMand the mapping between MIPI M-PHY symbol.
With reference now to table 1, show PCIe according to an embodiment of the invention tMsymbol maps to the exemplary of M-PHY symbol.Therefore, this indicates the mapping of the special symbol of protocol stack according to an embodiment of the invention for being polymerized.
table 1
Described 8b/10b decoding rule with for PCIe tMit is identical that specification defines.The sole exception of 8b/10b rule is when TAIL OF BURST being detected, and this is the particular sequence violating 8b/10b rule.According to each embodiment, Physical layer 430 can gum to the notice of any mistake met with during data link layer 420 is provided in TAIL OF BURST.
In one embodiment, symbol framing and be applied to passage can as PCIe tMdefine in specification, simultaneously data scrambling can with PCIe tMwhat define in specification is identical.But, it should be noted that do not upset the data symbol transmitted in the PREPARE stage according to the communication of MIPI specification.
About link initialization and training, link manager can provide and can comprise configuration and initialization, the support to normal data transmission, the support to State Transferring when recovering from link error of the link of the channel of one or more passage and restarted by the port of low power state by gum as discussed above.
In order to realize this generic operation, the feature that following physical and link are correlated with can be known (such as before initialization) in advance: PHY parameter (such as, comprises the speed of initial link circuit speed and support; And the link width of initial link circuit width and support).
In one embodiment, training can comprise various operation.This generic operation can comprise: with the link-speeds configured and this link of width initialization, every channel bit lock, every channel symbol lock, passage polarity and for the passage of hyperchannel link to passage deskew.Like this, training can find passage polarity, and performs adjustment accordingly.But, it should be noted that link data rates and the degeneration of width negotiation, link-speeds and width can not be comprised according to the link training of the embodiment of the present invention.As mentioned above contrary, once initialization link, two entities know initial link circuit width and speed all in advance, and therefore, it is possible to avoid and the time of consulting to be associated and calculation cost.
PCIe tMordered set can be used in following amendment: TS1 and TS2 ordered set is used for facilitating IP to re-use, but ignores many fields of described training ordered set.And, do not use Fast Training sequence.Electric idle ordered set (EIOS) can be retained re-use to facilitate IP, as jump OS, but the frequency of jump OS can for according to PCIe tMthe friction speed of specification.Be also noted that, data stream ordered set and symbol can with according to PCIe tMspecification identical.
Transmit following event to facilitate link to train and management: (1) exists, its energy gum is used to refer to exists active PHY on the remote port of link; And (2) configuration prepares, it is triggered to have indicated PHY parameter configuration and described PHY with the configuration file beamhouse operation of configuration.In one embodiment, be that category information can according to the embodiment of the present invention via unified sideband signals transmission.
For controlling the object of electric idle condition, PHY has and is used to indicate the TAIL OF BURST sequence that transmitter is just entering into electrical idle state.In one embodiment, described sideband channel may be used for the signal transmission quitting electric free time.It should be noted that this instruction can add that PHY suppresses to break mechanism.The OPENS sequence of symbol can be entered electrical idle state as EIOS transmission with instruction.
In certain embodiments, undefined Fast Training sequence (FTS).On the contrary, PHY can use specific Physical layer sequence for exiting from shutdown/sleep state to being used for addressing bits lock, symbol lock and the passage bursty state to passage deskew.A small amount of FTS can be defined as the symbol sebolic addressing for robustness.The beginning of data stream ordered set can according to PCIe tMspecification, as recovered in link error.
About link data rates, in embodiments, the original data rate of described link initialization can be predetermined data rate.Can be returned to form by experience and occur to change from the data rate of this initial link circuit speed.Embodiment can support asymmetric link data rate, wherein allows data rate on reverse direction different.
In one embodiment, the link width supported can according to PCIe tMthose in specification.In addition, as mentioned above, because described link width is predetermined, embodiment can not support the agreement for consulting link width, and therefore can simplify link training.Certainly, embodiment can provide support for the asymmetric link width on reverse direction.Meanwhile, can be known before training starts in advance for the initial link circuit width of each direction configuration of link and original data rate.
About the physical port of described PHY unit, do not require that xN port forms the ability of xN (wherein N can be 32,16,12,8,4,2 and 1) link and x1 link, and the ability that xN port forms link width arbitrarily between N and 1 is optional.The example of this behavior comprises x16 port, and it only can be configured to unique link, but the width of described link can be configured to the requirement width of x12, x8, x4, x2 and x16 and x1.Like this, seek to use the port that can connect these inter-modules according to the deviser of the protocol stack facilities and equipments of the embodiment of the present invention in the mode allowing two different assemblies to meet above-mentioned requirements.If the port of inter-module with do not meet by the port of assembly describe/mode of desired use that tables of data defines connects, then behavior is undefined.
In addition, an ability port being divided into two or more links is not forbidden.If such support is suitable for given design, then described port can be configured to support specific width at training period.The example of this behavior will be the x16 port that can configure two x8 links, 4 x4 links or 16 x1 links.
When using 8b/10b coding, as PCIe tMunambiguously passage in specification to passage deskew mechanism is the COM symbol of the ordered set received during training sequence or SKP ordered set, because transmit ordered set on all passages of the link of configuration simultaneously.The MK0 symbol transmitted during the synchronizing sequence of HS-BURST may be used for passage-passage deskew.
As above sketch with reference to figure 4, link training and state supervisor can be configured to perform various operation, comprise PCIe tMthe upper strata of protocol stack is fitted to lower floor's PHY unit of different agreement.In addition, this link manager can configure and manage single or multiple passage, and can comprise support every as follows: symmetric links bandwidth, have PCIe tMthe training of the compatibility of the state machine of affairs and data link layer, link, optional symmetric links stopped status and the control to the sideband signals for robust communication.Therefore, embodiment provides and utilizes limited revision for execution PCIe tMaffairs and data link layer are to take into account different link-speeds and asymmetric link.In addition, use the link manager according to the embodiment of the present invention, can realize, to multichannel support, asymmetric link configuration, sideband unification and dynamic bandwidth convergent-divergent, realizing the bridge joint between different communication protocol layer further simultaneously.
With reference now to Fig. 5, show the constitutional diagram 500 for Link Training State Machine, it can be the part of the link manager according to the embodiment of the present invention.As shown in Figure 5, link training can start from detected state 510 by gum.This state occurs when electrification reset, and is applicable to upstream and downstream port.After reset completes, the passage of all configurations can be converted to given state, i.e. HIBERN8 state, and every one end of described link can use sideband channel such as to signal via PRESENCE signal in this state.It should be noted that in this detected state, high impedance signal can be driven on all passages, i.e. DIF-Z signal.
Therefore, when signal sends and receives PRESENCE event, control to be passed to configuration status 520 by detected state 510, and on the passage of all configurations, drive this high impedance.In configuration status 520, PHY parameter can be configured, and once complete on all collocation channels of each end of described link, then can such as use sideband interconnection to indicate configuration ready signal (CFG-RDY) by gum, on all passages, maintain high impedance simultaneously.
Therefore once send via sideband interconnection and receive this configuration preparation instruction, control just to be passed to stopped status 530.Namely in this L0.STALL state, PHY is converted to STALL state, and continues to drive high impedance on all collocation channels.As can be seen, depend on whether data can be used for transmission or receive, control can be passed to active state L1 (state 530), low power state (L1 state 540), dark low power state (L1.OFF state 545) or return configuration status 520.
Therefore, in STALL state, negative drive singal DIF-N can be transmitted on the passage of all configurations.Then, when being guided by starter, BURST sequence can be started.Therefore, after transmission MARKER0 (MK0) symbol, control to be passed to active state 530.
In one embodiment, receiver can detect exiting from STALL state on the passage of all configurations, and according to such as MIPI regulation enforcement bit lock and symbol lock.In the embodiment with hyperchannel link, this MK0 symbol may be used for setting up passage to passage deskew.
On the contrary, when being directed to low power state (i.e. L1 state 540), the passage of all configurations can be converted to SLEEP state.Then, when being directed to darker low power state (i.e. L1.OFF state 545), the passage of all configurations can be converted to HIBERN8 state.Finally, when directed be back to configuration status time, similarly, the Channel-shifted of all configurations is to HIBERN8 state.
Still with reference to figure 5, for alive data transmission, control therefore to be passed to active state 550.Especially, this is that link and transaction layer bring into use data link layer packets (DLLP) and TLP to exchange the state of information.Like this, service load transmission can be there is, and at the end of this type of transmits, TAIL OFBURST symbol can be transmitted.
As can be seen, control to be back to STALL state 530, to returning to form 560 (such as in response to receiver mistake by this active state transmission by gum, or when directed in another manner) or to darker low-power (such as, L2) state 570.
In order to turn back to described stopped status, transmitter can send EIOS sequence on the passage of all configurations, and back is that TAIL of BURST indicates.
If mistake occurs or guides in another manner, control can also be passed to and return to form 560.Herein, being converted to recovery causes the passage of all configurations to enter STALL state in the two directions.In order to realize this, GO TO STALL signal can be sent by gum in sideband interconnection, and the transmitter of this signal can wait-for-response.When this stopping signal has been sent out and has received, as described in the upper GO TOSTALL received of sideband interconnection indicate indicated by, control transmission and get back to STALL state 530.Therefore notice that this returns to form uses sideband to set up described agreement to coordinate to enter into STALL state simultaneously.
About low power state L1 and L1.OFF, operate according to state 540 and 545.Especially, control from STALL state transfer to L1 low power state 540, to make it possible to PHY to be placed in SLEEP state.In this state, negative drive singal, i.e. DIF-N signal can be driven by gum on the passage of all configurations.When directed to exit described state time, control transmission and be back to STALL state, such as, send PRESENCE signal in the mutual attach signal of sideband.
Also as can be seen, when meeting all L1.OFF conditions, darker low state L1.OFF can be entered.In one embodiment, these conditions can comprise the power that complete power gating or pass drop to PHY unit.In this darker low power state, PHY can be placed in HIRERN8 state, and drive high impedance signal on the passage of all configurations.In order to exit this state, be back to STALL state via driving DIF-N on the passage of all configurations to control transmission.
Further as seen in Figure 5, can additivity being there is, namely darker further again low power state (L2) 570, when preparing to turn off power, this low power state darker further again (L2) 570 can be entered from active state by gum.In one embodiment, this state can with PCIe tMthat of specification is identical.
With reference now to table 2, show according to PCIe tMthe LTSSM state of specification with according to the mapping between the corresponding M-PHY state of the embodiment of the present invention.
table 2
As above described in reference diagram 2, embodiment provides the unified sideband mechanism of a kind of energy gum for supporting in link management and optional band.By this way, use side-band circuits and interconnection, link management and control can occur independent of (and the larger power consumption) circuit more at a high speed of the Physical layer for main interconnection.Further by this way, when the part of the PHY unit be associated with main interconnection is de-energized, this sideband channel can be used, realize power consumption and reduce.And, can this be used to unify sideband mechanism by gum before the main interconnection of training, and also can use when main interconnection is broken down.
Again further, unify sideband mechanism via this, single interconnection in each direction can be deposited, such as differential lines pair, thus reduce number of pins and realize increasing new ability.Embodiment can also realize sooner, the clock/power gating of more robust, and this link can be used to eliminate at such as PCIe tMambiguity in the normal protocol of sideband mechanism and so on.
But scope of the present invention is not limited thereto, in different embodiments, sideband interconnection (such as, the sideband interconnection 270 of Fig. 2) signal transmitter system in mongline bidirectional sideband signals, two-wire two-way one way signal collection, weathering zone (such as use be in M-PHY in low powder pulsed width modulated (PWM) pattern can) can be implemented as or be embodied as high speed signal transmit mechanism, such as Physical layer ordered set or DLLP in band.
As an example instead of for restriction object, various Physical layer method can be supported.When using sideband interconnection, first method can be to provide the mongline bidirectional sideband signals of minimum number of pins.In certain embodiments, can on existing sideband this signal multiplexed, such as PERST#, WAKE# or CLKREQ signal.Second method can be the two-way one way signal collection of two-wire, and it can be more simply and in a way more efficient compared to single line method, but cost is additional pins.Can on existing sideband this embodiment of multichannel subdivision, such as, for the PERST# of main process equipment and the CLKREQ# (in this example, maintain existing sense, simplify double mode embodiment) for device Host.The third method can be signal transmitter system in weathering zone, such as M-PHY LS PWM mode, and it decreases number of pins relative to sideband mechanism, and can still support similar low power level.Because this operator scheme and high speed operation mutual exclusion, thus it can with mechanism combination in the high-velocity zone of such as Physical layer ordered set or DLLP and so on.Although this method is not lower powered, it maximises the general character with existing High-speed I/O.When with low speed inband signaling send combine time, this method can provide good low-power solution.
In order to realize in a given system these configuration in one or more, can provide semantic layer, it can be used in the implication determining the information exchanged above Physical layer and strategic layer, and this implication can be used in understanding other action/reaction of equipment/platform class.In one embodiment, these layers may reside in SB PHY unit.
By providing layered approach, embodiment allows can comprise sideband ability (due to simplicity and/or low-power operation, it can be preferred in some embodiments) and interior (it can be preferred for other embodiment, such as, avoid needing additional pins number) both the different Physical layer embodiments of band.
In one embodiment, such as multiple sideband signals can be disposed for via semantic layer the individual data bag that communicates via unified sideband mechanism (or in band mechanism).In one embodiment, table 3 below shows each signal that can exist in one embodiment.In shown table, the logical direction of signal is shown by arrow, wherein upward arrow be defined as to main frame (such as, root complex) direction, and lower arrow is defined as the direction to equipment (such as, peripherals, such as radio solution).
table 3
Equipment existence ↑
Power is good ↓
Power-off ↓
Reference clock is good ↓
Basis reset ↓
Configuration preparation ↑ ↓
Preparation training ↑ ↓
Start to train ↑ ↓
L1pg request ↑ ↓
L1pg refusal ↑ ↓
L1pg mandate ↑ ↓
OBFF CPU is active ↓
OBFF DMA↓
OBFF is idle ↓
Wake up ↑
The response reception of shaking hands ↑ ↓
With reference now to Fig. 6, show the process flow diagram of each state for the sideband mechanism according to the embodiment of the present invention.As shown in Figure 6, these each states can about root complex (such as, host computer control operation).Constitutional diagram 600 can provide via the control of described main frame to each state.As can be seen, operation starts from pre-boot state 610, can transmit in a state in which and there is signal.Note this exist signal can as above about link management operation as described in.Then, control to be passed to boot state 620, various signal can be transmitted in a state in which, be i.e. power good signal, reset signal, reference clock status signal and preparation training signal.It should be noted that all these signals can via the transmission of individual data bag, each wherein in these signals can corresponding to the designator of described packet or field (such as, 1 bit indicator of packet).
Still with reference to figure 6; control next to be passed to active state 630; wherein system can be in active state (such as; S0); corresponding device (such as; upstream device can be active device state (such as, D0) and link can be in active state, shutdown or low power state (such as, L0, L0s or L1).As can be seen, in this state, various signal can be transmitted, comprise OBFF signal, clock request signal, reference clock state, request L0 signal and prepare training signal.
Next, such as, after performing the transmission of above-mentioned signal, control can be passed to low power state 640.As can be seen, in this low power state 640, this system can be in active state, and equipment can be in the low power state (such as, D3 heat) of relatively low delay simultaneously.In addition, described link can be in given low power state (such as, L2 or L3).As seen in these states, the signal transmitted via unified sideband data bag can comprise wake-up signal, reset signal and power good signal.
When described system enters darker low power state, can enter the second low power state 650 (such as, when described system is in S0 state and described equipment be in D3 cold state and described link be in similarly in L2 or L3 state time.As can be seen, can transmit and identical to wake up, reset and power good signal.Also in figure 6 seen by, in darker low power state 660 (such as, system low power state S3) and equipment low power state (such as, D3 is cold) and identical link low power state L2 and L3 can gum there is identical signal.Although show this specific set of side information of transmission, be appreciated that scope of the present invention is not limited thereto.
Embodiment is because herein is provided hierarchy, and having can relative to the ductility of flexibility tension simplicity and low latency.By this way, existing sideband signals and additional sideband signals can be replaced with the signal of fewer number of, and realize the expansion in future of sideband mechanism when not increasing more pins.
With reference now to Fig. 7, show a kind of process flow diagram of the method according to the embodiment of the present invention.As shown in Figure 7, method 700 may be used for transmitting data via the protocol stack of polymerization, and the protocol stack of this polymerization comprises the upper strata of a communication protocol and the lower floor of different communication protocol, such as Physical layer.In shown example, suppose the protocol stack of polymerization as above, namely there is PCIe tMthe Physical layer of the upper affairs of agreement and data link layer and different specification (such as MIPI specification).Certainly, the additional logic making these two communication protocol energy gums be polymerized to single protocol stack can also be there is, such as, above about logic and the circuit of Fig. 4 discussion.
As seen in Figure 7, method 700 can start from the protocol stack of the first communication protocol, receive the first affairs (frame 710) by gum.Such as, the various logic, other enforcement engine etc. of the root complex of such as kernel seek transmission information to another equipment.Therefore, this information can be passed to transaction layer.As can be seen, control to be passed to frame 720, wherein affairs can be processed and be supplied to the logical gate of the PHY of second communication agreement.About the various operations that the flow process of Fig. 4 is discussed above this process can comprise, wherein can occur to receive data, perform the various operations such as current control, link operation, packing operation.In addition, data link layer packets can be provided to the various operations of PHY.Next, control to be passed to frame 730, wherein in the logical gate of PHY, these first affairs can be converted into the second form affairs.Such as, can any conversion (when needing) of DO symbol.In addition, the various conversion operations therefore described affairs to be converted into the form for transmitting on said link can be performed.Therefore, control to be passed to frame 740 by gum, wherein via link, these the second form affairs can be sent to equipment from PHY.As an example, the second form affairs energy gum is the serialized data after line coding, serialization etc.Although high-levelly to illustrate with this in the embodiment of Fig. 7, be appreciated that scope of the present invention is not limited thereto.
With reference now to Fig. 8, show a kind of block diagram of the assembly according to existing in the computer system of the embodiment of the present invention.As shown in Figure 8, system 800 can comprise many different assemblies.These assemblies can be implemented as IC, its part, discrete electric subset or are fitted to the motherboard of such as computer system or insert other module of circuit board of card and so on, or are embodied as the assembly be incorporated in another manner in the cabinet of computer system.Be also noted that, the block diagram of Fig. 8 is intended to the high-level view of many assemblies that computer system is shown.But, be appreciated that can there is add-on assemble in some embodiments, and in addition, the difference that shown assembly can occur in other embodiments is arranged.
As seen in Figure 8, processor 810 (it can be the low power multi-core processor slot of such as ultralow voltage processor) can serve as Main Processor Unit for the various component communications with described system and central hub.This processor can be implemented as SoC.In one embodiment, processor 810 can be based on framework Core tMprocessor (i3, i5, the i7 that such as can obtain from the Intel company of California Santa Clara or another this type of processor).But, be appreciated that can alternatively to exist in other embodiment of such as apple A5 processor such as can obtain from the senior micro equipment company (AMD) of California Sunnyvale other low-power processor, the design based on ARM from Pty Ltd of ARM company or the MIPS Technologies Inc. from California Sunnyvale or their design based on MIPS obtaining permission person or adopter.
Processor 810 can communicate with system storage 815, and system storage 815 is implemented by multiple memory devices to be supplied to quantitative system storage in an embodiment.As an example, this storer can according to the design based on low-power double data rate (LPDDR) of jedec (JEDEC), such as according to the current LPDDR2 standard (in April, 2009 publication) of JEDEC JESD 209-2E, or be called LPDDR3, will provide the expansion of LPDDR2 to increase the LPDDR standard of future generation of bandwidth.As an example, the system storage of 2/4/8 GB (GB) can be there is, and processor 810 can be couple to via one or more memory interconnect.In various embodiments, individual memory devices can have different encapsulated types, such as single die encapsulation (SDP), dual-die encapsulation (DDP) or four die package (QDP).These equipment can directly be soldered in certain embodiments to provide low profile solution on motherboard, and in other embodiments, described equipment can be configured to one or more memory module, and it can be couple to motherboard by given connector by gum then.
In order to provide the lasting storage of information (such as data, application, one or more operating systems etc.), massage storage 820 also can be couple to processor 810.In embodiments, in order to realize thinner and lighter system, and in order to improved system response, this massage storage can be implemented via SSD.But, in other embodiments, massage storage can mainly use hard disk drive (HDD) to implement, wherein small amount SSD storer serves as SSD high-speed cache thus realizes the non-volatile memories of background state and other this type of information during shut down event, to make fast powering-up to occur when restarting system activity.Also illustrate in Fig. 8, flash memory device 822 can be couple to processor 810, such as, via serial peripheral interface (SPI).This flash memory device can provide the non-volatile memories of the system software of other firmware comprising basic I/O software (BIOS) and this system.
Various I/O (IO) equipment can be there is in system 800.Particularly illustrate display 824 in the embodiment of Fig. 8, it can be the High Resolution LCD or LED panel that configure in the cap of cabinet.This display pannel can also provide touch-screen 825, such as external adapter is mutual with what make via user and this touch-screen on described display pannel, user's input can be provided to system to realize the operation expected, such as, about information displaying, message reference etc.In one embodiment, display 824 can be couple to processor 810 via the display interconnection that can be implemented as high performance graphics interconnection.Touch-screen 825 can be couple to processor 810 via another interconnection, and it can be I in one embodiment 2c interconnects.As further shown in Figure 8, except touch-screen 825, can also be occurred via touch pad 830 by user's input of touch manner, touch pad 830 can be configured in described cabinet, and can also be couple to the I identical with touch-screen 825 2c interconnects.
Calculate and other object for perception, various sensor may reside in described system, and can be coupled to processor 810 by different way.Some inertia and environmental sensor can by sensor hub 840 (such as via I 2c interconnects) be couple to processor 810.In embodiment in fig. 8, these sensors can comprise accelerometer 841, surround lighting sensor (ALS) 842, compass 843 and gyroscope 844.In one embodiment, other environmental sensor can comprise one or more thermal sensor 846, and it can be couple to processor 810 via System Management Bus (SMBus) bus.It is also understood that, according to embodiments of the invention, one or more described sensor can be couple to processor 810 via LPS link.
Also see in Fig. 8, various peripherals can also be couple to processor 810 via low pin count (LPC) interconnection.In an illustrated embodiment, various assembly can be coupled by embedded controller 835.These assemblies can comprise keyboard 836 (such as, being coupled via PS2 interface), fan 837 and thermal sensor 839.In certain embodiments, touch pad 830 can also be couple to EC835 via PS2 interface.In addition, safe processor (such as according to the such as credible platform module (TPM) 838 of trust computing group (TCG) TPM specification version 1.2 (on October 2nd, 2003)) also can be couple to processor 810 via this LPC interconnection.
System 800 can to comprise various mode and the peripheral communications of wireless mode.In embodiment in fig. 8, there is various wireless module, wherein each can correspond to the radio for particular wireless communication protocols configuration.One can via near-field communication (NFC) unit 845 for the mode of the radio communication in short distance (such as near field), in one embodiment, near-field communication (NFC) unit 845 can communicate with processor 810 via SMBus.It should be noted that via this NFC unit 845, the equipment be closely adjacent to each other can communicate.Such as, by tight two equipment being fitted in together and realizing information (such as identification information, payment information, the data etc. of such as view data) transmit, user can make system 800 can communicate with another (such as) portable equipment (smart phone of such as user).NFC system can also be used to perform wireless power transmission.
As further in fig. 8 seen by, additional radio-cell can comprise other short-distance radio engine, comprises WLAN unit 850 and bluetooth unit 852.Use WLAN unit 850, the Wi-Fi according to given electric and EEA Eelectronic Eengineering Association (IEEE) 802.11 standard can be realized tM, simultaneously via bluetooth unit 852, the junction service via Bluetooth protocol can be there is in communication.These unit can communicate with processor 810 via such as USB link or Universal Asynchronous Receive transmitter (UART) link.Or these unit can be couple to processor 810 via interconnection via the low-power interconnection of all polymerization PCIe/MIPI as described herein interconnection or another this quasi-protocol of such as serial date transfer/output (SDIO) standard.Certainly, can connect at one or more actual physics inserted between these peripherals blocking configuration can by being fitted to the mode of the NGFF connector of motherboard.
In addition, wireless wide-area communication (such as according to honeycomb or other wireless wide-area agreement) can occur via the WWAN unit 856 that then can be couple to subscriber identification's module (SIM) 857.In addition, in order to realize reception and the use of positional information, GPS module 855 can also be there is.It should be noted that in the embodiment in fig. 8, the integrated capture device of WWAN unit 856 and such as camera module 854 can via given usb protocol (such as USB2.0 or 3.0 links), or UART or I 2c protocol communication.The actual physics of these unit connects can be fitted to via NGFF is inserted card the NGFF connector configured on motherboard again.
Input to provide audio frequency and export, audio process can be implemented via digital signal processor (DSP) 860, and it can be couple to processor 810 via high definition audio (HAD) link.Similarly, DSP860 can communicate with integrated encoder/demoder (CODEC) and amplifier 862, and integrated encoder/demoder (CODEC) and amplifier 862 can be couple to the output loudspeaker 863 can implemented in cabinet then.Similarly, amplifier and CODEC862 can be coupled to input from microphone 865 audio reception, and microphone 865 can be implemented to provide high quality audio to input via two array microphone thus realize controlling the voice activation of operation various in system in an embodiment.Be also noted that, audio frequency exports can be provided to earphone jack 864 from amplifier/COEDC862.
Therefore, it is possible to use embodiment in many varying environments.With reference now to Fig. 9, show the instance system 900 that can use together with embodiment.As can be seen, system 900 can be smart phone or other wireless communicator.As shown in the block diagram of Fig. 9, system 900 can comprise baseband processor 910, and it can be the polycaryon processor that can process Base-Band Processing task and application process.Therefore, baseband processor 910 can perform the various signal transacting about communication, and performs the calculating operation being used for described equipment.Then, baseband processor 910 can be couple to user interface/display 920, and user interface/display 920 can be realized by touch-screen display in certain embodiments.In addition, baseband processor 910 can be couple to accumulator system, and it comprises nonvolatile memory (i.e. flash memory 930) and system storage (i.e. dynamic RAM (DRAM) 935) in the embodiment in fig. 9.As further seen, baseband processor 910 can be couple to capture device 940 further, all if the image capture device of recording of video and/or rest image.
In order to realize transmission and the reception of communication, between baseband processor 910 and antenna 980, various circuit can be coupled.Especially, radio frequency (RF) transceiver 970 and WLAN (wireless local area network) (WLAN) transceiver 975 can be there is.In general, RF transceiver 970 may be used for according to such as receiving according to the given wireless communication protocol of such as 3G or the 4G wireless communication protocol of CDMA (CDMA), global system for mobile communications (GSM), Long Term Evolution (LTE) or other agreement and transmitting wireless data and call out.Other radio communication such as receiving or transmit radio signal can also be provided, such as AM/FM, or HA Global Positioning Satellite (GPS) signal.In addition, via WLAN transceiver 975, local area radio signal can also be realized, such as according to Bluetooth tMstandard or IEEE802.11 standard (such as IEEE802.11a/b/g/n).It should be noted that the link in baseband processor 910 and transceiver 970 and 975 between one or two via combination and can map PCIe tMthe low-power polymeric interconnect of the function of interconnection and low-power interconnection (such as MIPI interconnection).Although high-levelly to illustrate with this in the embodiment of Fig. 9, be appreciated that scope of the present invention is not limited thereto.
Embodiment can be used in many dissimilar systems.Such as, in one embodiment, communication facilities can be arranged to and perform various method as herein described and technology.Certainly, scope of the present invention is not limited to communication facilities, and on the contrary, other embodiment can relate to other types of devices for the treatment of instruction, or one or more machine readable media, comprise and make described equipment perform the instruction of one or more methods as herein described and technology in response to being performed on the computing device.
Embodiment can with code implementation, and can be stored on non-transitory storage medium, non-transitory storage medium have stored thereon, can be used in System Programming to perform the instruction of described instruction.Described storage medium can comprise, but be not limited to: the disk of any type, comprise floppy disk, CD, solid-state drive (SSD), compact disk ROM (read-only memory) (CD-ROM), compact disk (CD-RW) can be rewritten, and magneto-optic disk; Semiconductor equipment, such as ROM (read-only memory) (ROM), random access memory (RAM) (such as dynamic RAM (DRAM), static RAM (SRAM)), Erasable Programmable Read Only Memory EPROM (EPROM), flash memory, Electrically Erasable Read Only Memory (EEPROM); Magnetic or light-card or be suitable for other type media any of store electrons instruction.
Although describe the present invention about a limited number of embodiment, it will be appreciated by those skilled in the art that the many modifications and variations come by it.Appended claim is intended to cover these type of modifications and variations all fallen in true spirit of the present invention and scope.
accompanying drawing is sketched
Fig. 1 is the high-level block diagram of the protocol stack for communication protocol according to the embodiment of the present invention.
Fig. 2 is the block diagram of the SOC (system on a chip) (SoC) according to the embodiment of the present invention.
Fig. 3 is the block diagram of physical location according to another embodiment of the present invention.
Fig. 4 is the block diagram of the further details of the protocol stack illustrated according to the embodiment of the present invention.
Fig. 5 is the constitutional diagram for Link Training State Machine, and it can be the part of the link manager according to the embodiment of the present invention.
Fig. 6 is the process flow diagram of each state for sideband mechanism according to the embodiment of the present invention.
Fig. 7 is the process flow diagram of the method according to the embodiment of the present invention.
Fig. 8 is the block diagram of the assembly existed in the computer system according to the embodiment of the present invention.
Fig. 9 is the block diagram of the instance system that embodiment can therewith use.

Claims (19)

1. a device, comprising:
For peripheral assembly high speed interconnect tM(PCIe tM) protocol stack of communication protocol, described protocol stack comprises transaction layer and link layer; And
Physics (PHY) unit, be couple to described protocol stack to provide described device and the communication of equipment room being couple to described device via physical link, described PHY unit has low power communication agreement, and comprise according to the physical location circuit of described low power communication agreement with by the logical layer of described protocol stack and described physical location circuit interface, described logical layer comprises the Link Training State Machine of the link training performing described physical link, and comprises and will have described PCIe tMfirst special symbol of communication protocol is mapped to the mapping logic of second special symbol with described low power communication agreement.
2. device as claimed in claim 1, wherein, described physical link from described device to described equipment have with from described equipment to the asymmetric width of described device, and described physical link can be configured to from described device to described equipment with from described equipment to the asymmetric frequencies operations of described device.
3. device as claimed in claim 1, wherein said Link Training State Machine when not consulting with described equipment in advance by physical link from the reset initialization of described device to initial link circuit width and frequency.
4. device as claimed in claim 3, wherein said Link Training State Machine causes change when not consulting with described equipment in the link width of described physical link.
5. device as claimed in claim 1, comprise sideband channel that described device couples with described equipment room, that be separated with described physical link further, described sideband channel comprises the serial link with the second PHY unit be separated with described PHY unit, and there is Signal transmissions to described equipment first in wherein said second PHY unit, and receive second from described equipment and there is signal, signal is there is and configures described physical link in described Link Training State Machine in response to receiving second in the second PHY unit.
6. a method, comprising:
Be couple in the first integrated circuit of the second integrated circuit via physical link, in response to powering on of described first integrated circuit, perform the detected state of the Link Training State Machine of physics (PHY) unit that have low power communication agreement, that comprise physics element circuit, described PHY unit is couple to the peripheral assembly high speed interconnect for comprising transaction layer and link layer tM(PCIe tM) protocol stack of communication protocol;
After the described detected state of execution, in described first integrated circuit, perform the configuration status of described Link Training State Machine, comprise, via the sideband link coupled between first and second integrated circuit described, configuration ready signal is sent to described second integrated circuit; And
In described first integrated circuit; the second configuration ready signal is received from described second integrated circuit in response to via described sideband link; perform the stopped status of Link Training State Machine, wherein during described stopped status, described PHY unit drives difference n-signal on described physical link.
7. method as claimed in claim 6, comprises: in described stopped status, start burst sequences, further to be transformed in the active state of described Link Training State Machine.
8. method as claimed in claim 7, comprises further: in described active state, service load is sent to described second integrated circuit from described first integrated circuit, and the afterbody transmitting burst is afterwards to be transformed into described stopped status.
9. method as claimed in claim 6, comprises further: be transformed into the first low power state from described stopped status, and on described physical link, drive described difference n-signal in described first low power state.
10. method as claimed in claim 9, comprises further: there is signal in response to receiving from described second integrated circuit via described sideband link, being transformed into described stopped status from described first low power state.
11. methods as claimed in claim 9; comprise further: when meeting one group of predetermined condition; the second low power state is transformed into from described stopped status; described second low power state lower than described first low power state, and drives difference high impedance signal in described second low power state on described physical link.
12. methods as claimed in claim 7, comprise further: in response to receiver mistake, are transformed into return to form from described active state.
13. methods as claimed in claim 6, comprise further:
Via described sideband channel, shutdown enabling signal is sent to described second integrated circuit; And
Described stopped status is transformed in response to receiving shutdown indicator signal via described sideband link from described second integrated circuit.
14. methods as claimed in claim 7, comprise further: be transformed into off-position in response to the communication received from described protocol stack in PHY unit from described active state.
15. 1 kinds of systems, comprising:
Polycaryon processor, comprise multiple kernel and realize described polycaryon processor and the protocol stack communicated via physical link between peripherals, described protocol stack comprises:
According to peripheral assembly high speed interconnect tM(PCIe tM) transaction layer of communication protocol;
According to described PCIe tMthe data link layer of communication protocol; And
According to low power communication agreement, the Physical layer that comprises physical layer transmission controller and physics (PHY) unit transmission circuit, wherein said physical layer transmission controller is fitted to described PHY unit transmission circuit has PCIe tMthe transaction layer of communication protocol and data link layer, described Physical layer comprises the Link Training State Machine of the link training performing described physical link further, and comprises and will have described PCIe tMfirst special symbol of communication protocol is mapped to the mapping logic of second special symbol with described low power communication agreement; And
Be couple to the peripherals of described polycaryon processor.
16. systems as claimed in claim 15, wherein said Link Training State Machine: in response to powering on of described polycaryon processor, performing the configuration status performing described Link Training State Machine after detected state, comprising sending via the sideband link coupled between described polycaryon processor and described peripherals and configure ready signal to described peripherals; And perform the stopped status of described Link Training State Machine in response to receiving the second configuration ready signal via described sideband link from described peripherals; wherein during described stopped status, described PHY unit transmission circuit drives difference n-signal on described physical link.
17. systems as claimed in claim 16; wherein said Link Training State Machine starts burst sequences to be transformed in the active state of described Link Training State Machine in described stopped status; and in described active state, service load is sent to described peripherals from described polycaryon processor, and the afterbody transmitting burst is afterwards to be converted to described stopped status.
18. systems as claimed in claim 17; shutdown enabling signal signal is sent to described peripherals via described sideband link by wherein said Link Training State Machine, and is converted to described stopped status in response to receiving shutdown indicator signal via described sideband link from described peripherals.
19. systems as claimed in claim 15, wherein said peripherals comprises multi radio integrated circuit.
CN201380021347.8A 2012-05-22 2013-05-16 Apparatus and method for the link training and management of optimization Active CN104380274B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610857743.XA CN107092335B (en) 2012-05-22 2013-05-16 Optimized link training and management mechanism

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/477,310 US8437343B1 (en) 2012-05-22 2012-05-22 Optimized link training and management mechanism
US13/477310 2012-05-22
PCT/US2013/041322 WO2013176954A2 (en) 2012-05-22 2013-05-16 Optimized link training and management mechanism

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN201610857743.XA Division CN107092335B (en) 2012-05-22 2013-05-16 Optimized link training and management mechanism

Publications (2)

Publication Number Publication Date
CN104380274A true CN104380274A (en) 2015-02-25
CN104380274B CN104380274B (en) 2017-10-24

Family

ID=52569929

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201610857743.XA Active CN107092335B (en) 2012-05-22 2013-05-16 Optimized link training and management mechanism
CN201380021347.8A Active CN104380274B (en) 2012-05-22 2013-05-16 Apparatus and method for the link training and management of optimization

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN201610857743.XA Active CN107092335B (en) 2012-05-22 2013-05-16 Optimized link training and management mechanism

Country Status (1)

Country Link
CN (2) CN107092335B (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107436856A (en) * 2016-05-28 2017-12-05 硅实验室公司 With the communicator and correlation technique directly controlled
CN109416677A (en) * 2016-07-22 2019-03-01 英特尔公司 Support the technology of a variety of interconnection agreements for one group of public interconnecting connector
CN109426549A (en) * 2017-09-01 2019-03-05 英特尔公司 Distribution is interconnected for the accelerator of virtual environment
CN110647486A (en) * 2019-09-29 2020-01-03 江苏芯盛智能科技有限公司 PCIe link training method, end equipment and communication system
CN112015683A (en) * 2020-08-27 2020-12-01 深圳忆联信息系统有限公司 Dynamic switching method and device of PCIE link, computer equipment and storage medium
CN113434446A (en) * 2018-05-04 2021-09-24 英特尔公司 Flexible bus protocol negotiation and enablement sequence

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118093490B (en) * 2024-04-16 2024-07-26 北京开源芯片研究院 Bus protocol conversion method and device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080065796A1 (en) * 1999-08-04 2008-03-13 Super Talent Electronics Inc. High-Level Bridge From PCIE to Extended USB
US20090106476A1 (en) * 2007-10-22 2009-04-23 Peter Joel Jenkins Association of multiple pci express links with a single pci express port
CN101640643A (en) * 2008-07-25 2010-02-03 美国博通公司 Method for energy efficient Ethernet and physical layer equipment for enery efficient ethernet
CN102014048A (en) * 2009-06-30 2011-04-13 英特尔公司 Link power savings with state retention

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040221315A1 (en) * 2003-05-01 2004-11-04 Genesis Microchip Inc. Video interface arranged to provide pixel data independent of a link character clock
US8218580B2 (en) * 2008-07-15 2012-07-10 Intel Corporation Managing timing of a protocol stack
US8621128B2 (en) * 2009-12-04 2013-12-31 St-Ericsson Sa Methods and systems for reliable link startup

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080065796A1 (en) * 1999-08-04 2008-03-13 Super Talent Electronics Inc. High-Level Bridge From PCIE to Extended USB
US20090106476A1 (en) * 2007-10-22 2009-04-23 Peter Joel Jenkins Association of multiple pci express links with a single pci express port
CN101640643A (en) * 2008-07-25 2010-02-03 美国博通公司 Method for energy efficient Ethernet and physical layer equipment for enery efficient ethernet
CN102014048A (en) * 2009-06-30 2011-04-13 英特尔公司 Link power savings with state retention

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107436856A (en) * 2016-05-28 2017-12-05 硅实验室公司 With the communicator and correlation technique directly controlled
CN107436856B (en) * 2016-05-28 2023-08-22 硅实验室公司 Communication device with direct control and related method
CN109416677A (en) * 2016-07-22 2019-03-01 英特尔公司 Support the technology of a variety of interconnection agreements for one group of public interconnecting connector
CN109416677B (en) * 2016-07-22 2024-03-01 英特尔公司 Techniques to support multiple interconnect protocols for a set of common interconnect connectors
CN109426549A (en) * 2017-09-01 2019-03-05 英特尔公司 Distribution is interconnected for the accelerator of virtual environment
CN113434446A (en) * 2018-05-04 2021-09-24 英特尔公司 Flexible bus protocol negotiation and enablement sequence
CN110647486A (en) * 2019-09-29 2020-01-03 江苏芯盛智能科技有限公司 PCIe link training method, end equipment and communication system
CN112015683A (en) * 2020-08-27 2020-12-01 深圳忆联信息系统有限公司 Dynamic switching method and device of PCIE link, computer equipment and storage medium

Also Published As

Publication number Publication date
CN104380274B (en) 2017-10-24
CN107092335B (en) 2020-07-21
CN107092335A (en) 2017-08-25

Similar Documents

Publication Publication Date Title
CN106209695B (en) Providing low power physical units for load/store communication protocols
CN106970886B (en) Controlling a physical link of a first protocol using an extended functionality architecture of a second protocol
US9141577B2 (en) Optimized link training and management mechanism
US9223735B2 (en) Providing a consolidated sideband communication channel between devices
US9830292B2 (en) Architected protocol for changing link operating mode
CN104380274A (en) Optimized link training and management mechanism
US20150089107A1 (en) Providing A Serial Protocol For A Bidirectional Serial Interconnect

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
CI01 Publication of corrected invention patent application

Correction item: Application Date|Priority|International application date

Correct: 2013;05;16|13/477310 2012.05.22 US|2013;05;16

False: 2013;07;16|no|2013;07;16

Number: 08

Volume: 31

CI02 Correction of invention patent application

Correction item: Application Date|Priority|International application date

Correct: 2013.05.16|13/477310 2012.05.22 US|2013.05.16

False: 2013.07.16|None|2013.07.16

Number: 08

Page: The title page

Volume: 31

ERR Gazette correction

Free format text: CORRECT: APPLICATION DATE; PRIORITY DATA; INTERNATIONAL APPLICATION DATE; FROM: 2013;07;16; NONE;2013;07;16 TO: 2013;05;16;13/477310 2012.05.22 US;2013;05;16

RECT Rectification
GR01 Patent grant
GR01 Patent grant