WO2012163019A1

WO2012163019A1 - Method for reducing power consumption of externally connected ddr of data chip and data chip system

Info

Publication number: WO2012163019A1
Application number: PCT/CN2011/081241
Authority: WO
Inventors: 张红标
Original assignee: 华为技术有限公司
Priority date: 2011-10-25
Filing date: 2011-10-25
Publication date: 2012-12-06
Also published as: CN102439534A

Abstract

The present invention relates to a method for reducing the power consumption of an externally connected DDR of a data chip and a data chip system. The method comprises: when the data chip system is lightly loaded or uncongested, storing the data to be written in a cache module added to the data chip; when the data chip system is heavily loaded or congested, starting the externally connected DDR, and after all the data in the externally connected DDR of the data chip system has been read out, shutting down the externally connected DDR. The data chip is capable of shutting down the externally connected DDR as much as possible during normal operation, thereby reducing the power consumption of the externally connected DDR of the data chip.

Description

Method for reducing data chip external DDR power consumption and data chip system

The invention relates to a chip energy-saving technology, in particular to a method for reducing power consumption of a data chip external DDR and a data chip system. Background technique

With the rapid development of data services, DDR (Double Data Rate, Double Rate Synchronous Dynamic Random Access Memory) is widely used in various data chips by means of external plug-ins to ensure large traffic data due to its low cost and large cache space. Traffic forwarding and forwarding for service forwarding.

Usually, the data chip externally DDRs through the external interface module DDRCTRL. Within the DDRCTRL module, a two-level cache is implemented using a ternary content addressable memory (TCAM) and an external DDR. Due to the limitation of TCAM resource overhead, the amount of information that can actually be stored is small, usually for external DDR read and write delays, and the operation of writing data to DDR is not completed, but the data needs to be read from DDR. To complete the read data Bypass processing in this case.

In the working process of the above data chip, no matter what application scenario, the DDR plug-in must be opened, and data is written at any time. In fact, in many applications, such as light load conditions, or no congestion full bandwidth, DDR plug-ins at this time are actually useless, but with this structure will introduce huge power consumption. Summary of the invention

Embodiments of the present invention provide a method and a data chip system for reducing power consumption of a data chip external DDR to reduce external DDR power consumption of a data chip.

Embodiments of the present invention provide a method for reducing power consumption of a data chip external DDR, including: storing data to be written in the data chip system under light load or non-congestion a cache module added to the class chip;

In the case that the data type chip system is overloaded or congested, the external DDR is started, and when the data in the external DDR of the data type chip system is completely read, the external DDR is turned off.

The embodiment of the present invention further provides a data chip system, including a DDRCTRL module, a chip, and an external DDR connected to the DDRCTRL module, wherein the chip is provided with a cache module and the cache module, the DDRCTRL The BUFCTRL module connected to the module, the BUFCRTL module includes:

a cache write unit, configured to store data to be written into the cache module in a case where the data class chip system is lightly loaded or uncongested;

a shut down unit, configured to be in a case where the data type chip system is lightly loaded or uncongested, the plugin

After the data in the DDR is completely read, the external DDR is turned off;

And an activation unit, configured to start the hang DDR in case the data type chip system is overloaded or congested.

The method for reducing the power consumption of the data chip external DDR and the data chip system provided by the embodiment of the present invention, the external DDR is turned off under the light load or non-congestion of the data chip system, and the data type chip system is overloaded or In the case of congestion, the external DDR is activated, so that the data chip can close the external DDR as much as possible under normal operation, and the external DDR power consumption of the data chip is reduced. DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings to be used in the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the present invention, Those skilled in the art can also obtain other drawings based on these drawings without paying any creative work.

FIG. 1 is a flowchart of a method for reducing power consumption of a data chip external DDR according to an embodiment of the present invention; 2 is a schematic diagram of a water line in a method for reducing power consumption of a data chip external DDR according to an embodiment of the present invention;

3 is a schematic diagram of three banks in an external DDR in a method for reducing power consumption of a data chip external DDR according to an embodiment of the present invention;

4 is a schematic structural diagram of a data chip system according to an embodiment of the present invention;

FIG. 5 is a schematic structural diagram of a power consumption control module in a data chip system according to an embodiment of the present disclosure;

Figure 6 is a schematic diagram of the interface part of the data chip when the DDR is externally connected; Figure 7 is a schematic diagram of the bank address in the external DDR. detailed description

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

1 is a flow chart of a method for reducing power consumption of a data chip external DDR according to an embodiment of the present invention, including:

Step 11. In the case that the data type chip system is lightly loaded or uncongested, the data to be written is stored in the cache module added in the data type chip;

Step 12: When the data chip system is overloaded or congested, the plugin is started.

DDR, and when the data in the external DDR of the data chip system is completely read, the external DDR is turned off.

For example, if a secondary shared cache RAM is set in the data chip, the data type chip system is lightly loaded or the system has no congestion time (the cache time is short, and the cache is required under a certain bandwidth flow condition). The smaller the space, in fact, similar to the no-congestion condition, the data is buffered by the RAM in the data-based chip. At this time, the data to be written can be written to the chip. After setting the cache module RAM, and then waiting for the data in the external DDR to be read, the power of the external DDR is turned off, which greatly reduces the power consumption of the entire data chip system.

When the system needs a large buffer space under high load or congestion conditions, the internal logic automatically starts the external DDR cache, and transfers some data of the on-chip cache to the external DDR to ensure that the data chip continues to perform normal data storage and access. In conjunction with algorithms for evaluating or predicting system congestion or reloading, consider moving out queues that require a large amount of cache space. For example, whether the system is congested or overloaded is determined by the dwell time of the data in the cache, the depth of the queue, and the like. In general, a larger queue depth indicates that the queue is more congested.

In the above step 11, the cache module may store data by means of independent queue management or shared queue management.

Among them, the shared queue management method is beneficial to make full use of the cache space of the cache module and reduce the overhead of the cache module. Specifically, since the shared queue management mode is used for interfacing with specific application conditions and subsequent queue scheduling, the shared queue management mode can be implemented under the condition of avoiding the use of a large TCAM for the inherent sequence of the queues. Most of the data does not need to be written to the external DDR and is directly dispatched by Bypass. Therefore, in normal applications, the access to the external DDR can be well reduced, and the overall power consumption of the system is reduced, which is particularly suitable for distributed routing. A scenario in which the upstream data bandwidth of the chip is large but there is no congestion. In other words, the shared on-chip cache not only reduces the access frequency of the DDR, but also does not access the DDR even in light load or no congestion. It also solves the problem that the ordinary secondary TCAM cache cannot handle a large amount of data due to resource limitations. Limit the problem.

The watermark can also be set in the cache module as a basis for determining the light load or heavy load, congestion or non-congestion of the data chip system, thereby determining whether to close the external DDR according to whether the data storage capacity in the cache module reaches the water line. .

Specifically, as shown in FIG. 2, a first water line, a second water line, a third water line, and a fourth water line are disposed. The amount of data stored in the cache module reaches a first watermark, and the data to be written is stored in an added cache module in the data type chip.

After that, wait for the data in the external DDR to be read. When the data in the external DDR is read After that, turn off the power of the external DDR.

When the amount of data storage in the cache module reaches the second watermark, the power of the external DDR is turned on and initialized.

After starting the plug-in DDR, the method further includes:

In the case where the amount of data storage in the cache module reaches the third watermark, the queue with the largest amount of data cache is selected from the cache module; such a queue is also referred to as a bad queue.

Write the selected queue to the external DDR. Write bad queues to external DDRs to minimize the number of queues written to the external DDR, so that the cache module set in the data chip can free up enough space to cache other queues with less cache and fast scheduling, which can maximize the internal cache. The ground is used by other low-congestion queues, which helps to reduce the access frequency of the external DDR, and also helps to further reduce the power consumption of the data chip system. Moreover, for the same queue, the buffer space in the DDR is Bank continuous, so that the bandwidth of the DDR can be utilized to the utmost.

After starting the plug-in DDR, the method further includes:

In the case that the data storage amount in the cache module reaches the fourth watermark, a back pressure operation is performed to prevent the upper module from continuing to write data.

The process of writing the selected queue to the external DDR may include: equally distributing the data in the selected queue to the bank of the external DDR in order.

As shown in FIG. 3, three queues: the first queue, the second queue, the third queue, and three banks in the DDR: Bank0, Bank1, and Bank2 are taken as an example for description. Write the data in the first queue to the addresses 0, 1, 6, 7, and Bank1 addresses 0, 1, 6, 7 and Bank2 addresses 0, 1, 6, and 7 in sequence; The data in the sequence is sequentially written to BankO's address 2, 3, 8, 9, Bankl's addresses 2, 3, 8, 9 and Bank2's addresses 2, 3, 8, and 9. The data in the third queue is pressed. The sequence is sequentially written to BankO's addresses 4, 5, 10, 11, Bankl's addresses 4, 5, 10, 11 and Bank 2's addresses 4, 5, 10, 11. This method does not need to record the bank number information of each storage address, and does not waste the buffer space of the external DDR. At the same time, it can completely avoid the waste of bandwidth caused by the bank conflict of the external DDR when writing data. A person skilled in the art can understand that all or part of the steps of implementing the above method embodiments may be completed by using hardware related to program instructions, and the foregoing program may be stored in a computer readable storage medium, and the program is executed when executed. The foregoing steps include the steps of the foregoing method embodiments; and the foregoing storage medium includes: a medium that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disk.

FIG. 4 is a schematic structural diagram of a data chip system according to an embodiment of the present invention. As shown in FIG. 4, the data chip system includes a DDRCTRL module 41, a BUFCTRL module 42, a chip 43 and an external DDR 44. The BUFCTRL module 42 is connected to the DDRCTRL module 41, and the DDRCTRL module 41 is connected to the external DDR 44. The DDRCTRL module 41 and the BUFCTRL module 42 are both disposed in the chip 43, the BUFCTRL module 42 includes a BUF-RAM and a power consumption control module 423, and the BUF_RAM includes a buffer module 421 and a multiplexer (MUX 422).

Write control module WR-CTRL and read control module RD- CTRL and BUF-RAM interface Wr_ddrl, Rd ddrl, TCAM and BUF-RAM interface Wr_ddr2, Rd_ddr2, similar to the existing write control module WR—CTRL and read control module RD—The interface between CTRL and TCAM.

The MUX 422 and the power consumption control module 423 are connected to the cache module 421. The power control module 423 is connected to the DDR interface and the TCAM as a prwd-ddr signal line, and the prwd-ddr signal is an indication to trigger a DDR power off (PowerDown), which is mainly used to control system power consumption.

FIG. 5 is a schematic structural diagram of a power consumption control module in a data chip system according to an embodiment of the present invention. As shown in FIG. 5, the power consumption control module includes: a cache write unit 51, a shutdown unit 52, and a boot unit 53.

The cache write unit 51 is configured to store the data to be written into the cache module added in the data chip when the data chip system is lightly loaded or uncongested;

The closing unit 52 is configured to close the external DDR after the data in the external DDR of the data chip system is read out under the condition that the data chip system is lightly loaded or uncongested;

The starting unit 53 is configured to start the method if the data class chip system is overloaded or congested Xi Bu hanging DDR.

The closing unit 52 may be specifically configured to store the data to be written into the added cache module in the data type chip if the data storage amount in the cache module reaches the first water line.

The activation unit 53 may be specifically configured to: when the data storage amount in the cache module reaches the second water line, turn on the power of the external DDR and initialize.

The power control module can also include:

a queue selection unit, configured to select, after the startup unit starts the external DDR, a queue with the most data volume cache from the cache module, when the data storage amount in the cache module reaches a third watermark ;

a DDR write unit, configured to write the queue selected by the queue selection unit to the plugin

DDR.

The DDR write unit may be specifically configured to evenly distribute data in the selected queue to the bank of the external DDR.

The power control module may further include: a back pressure unit, configured to perform a back pressure operation in a case where the data storage amount in the cache module reaches the fourth water line.

The cache module 421 can be a RAM.

The shared cache RAM in the BUFCTRL module 42 is the cache module 421 for buffering the received data information. The power control module 423 in the BUFCTRL module 42 is used to close the external DDR buffer due to the small amount of data to be cached under light or non-congested conditions of the data chip system. At this time, all the data is stored in the buffer module 421 of the on-chip BUFCTRL module 42, and the read operation scheduled by the schedule is directly read from the cache module 421. The data written in the cache module 421 can adopt the shared queue management mode mentioned in the foregoing method embodiment. For details, refer to the description in the foregoing method embodiment.

As shown in FIG. 2, a watermark is set for the cache module 421 in the BUFCTRL module 42, wherein the fourth watermark is used to generate a back pressure requirement under extreme conditions, and the second watermark is used to trigger the BUFCTRL module 42 to activate the external DDR. It is also possible to set the watermark of the third watermark to the DDR to initiate the write request. If the data storage capacity in the cache module 421 reaches the first watermark, or the data storage amount in the cache module 421 reaches the first watermark, the power control module 423 automatically starts the external DDR, and prepares to write some of the on-chip cached data. Go to the external DDR.

When the cache module 421 caches data in a shared queue management manner, the power consumption control module 423 can combine data according to the characteristics of the queue according to the access characteristics of the external DDR address, such as sequentially arranging the data in each queue. When it is distributed to eight banks, when a queue is removed from the cache module to the external DDR, the problem of DDR read and write Bank conflicts can be completely avoided by copying the storage address space of the bank. And to a certain extent, it is beneficial to improve the read bandwidth utilization.

See the description of the embodiment shown in Figure 3 above for details. When the data of all the queues in the external DDR is evenly and continuously allocated to 8 banks in sequence, a plurality of consecutive data for each queue is written into the DDR, and it is surely a continuous write of a plurality of banks. When the granularity of each queue is continuously written to the DDR to a certain extent, if 8 cells are continuously written together, the bandwidth waste caused by the bank conflict of writing DDR can be completely avoided.

When the queue selected for writing to the DDR is the queue with the largest amount of data cache in the data type chip, the number of queues written in the external DDR can be minimized, so that the cache module 421 can free up enough space to cache other caches and require less scheduling. The queue helps to reduce the frequency of access to the DDR plug-in, which in turn helps to reduce system power consumption. Since the input and output bandwidths of the BUFCTRL module 42 are the same, under normal circumstances, the data chip system can completely limit the speed without the full back pressure of the cache module 421.

When the data chip starts the external DDR and then is under the light load condition for a while, the system will gradually schedule the data in the external DDR cache. At this time, the data amount in the cache module 421 is lower than the condition of the first water line. Next, the internal logic, power control module 423, triggers the shutdown of the external DDR buffer, thereby reducing overall system power consumption.

Since the data chip system gradually transfers data to the external DDR according to the queue, if the data needs to be requested from the off-chip DDR, the probability of the read request using the continuous request is greatly increased, and Consider the case of making a continuous request for the same queue by means of prefetching, so as to effectively use

Read access bandwidth of DDR.

Usually, the interface part of the data chip external DDR is shown in Figure 6. The data is written or read by the DDRCTRL module to the external DDR connected to the DDR interface. In order to solve the problem of low DDR bandwidth utilization, the external DDR is generally used for continuous read and write operations to avoid the problem that DDR cannot access the same bank twice in a period of time, and fully utilizes the characteristics of DDR cache space. Use cache space to swap bandwidth. Specifically, only one bank in the external DDR is used to store data, and the other 7Bank is used to back up the data stored in BankO. Thus, as shown in Figure 7, any data written to any address can be written to any of the 8 banks, thus ensuring that data conflicts do not occur in the DDR. However, in order to record which bank the data is ultimately stored in, it is necessary to record a bank number address for each address space, resulting in a waste of on-chip RAM that requires a portion of the space for buffering the record information copied by the Bank. When reading the schedule, the Bank is selected according to the Bank number that is valid at the corresponding address, and the valid data is read. Due to the randomness of the read data, there may be a problem of Bank collision, which is likely to cause bandwidth loss of the external DDR.

The above method and chip system implement the second level cache through the added cache module, and close the external DDR cache under light load conditions or under the condition of less congestion or non-congestion, which not only effectively reduces the system power consumption, but also It avoids the resource bottleneck caused by the current secondary cache through TCAM matching. Further, the shared queue management mode is adopted in the cache module, which greatly reduces the access frequency to the external cache DDR. Moreover, by means of the method of joining the information, the DDR access granularity is improved by sequentially storing the data in each queue into the 8 banks of the DDR, thereby effectively improving the read/write bandwidth utilization of the DDR as a whole and reducing the extremes. In the case of bandwidth risk, the stability of the data chip system is improved, and the resources of the recorded Bank information required for the original DDR storage space backup are exponentially reduced, and a part of the RAM is used for buffering the bank copy record in the DDR. The way of information bank copying improves on-chip RAM resource utilization, exponentially reduces or even eliminates the waste of DDR storage space existing in the prior art. It should be noted that the above embodiments are only for explaining the technical solutions of the present invention, and are not intended to be limiting; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that: The technical solutions described in the foregoing embodiments are modified, or some of the technical features are equivalently replaced. The modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

Rights request

A method for reducing power consumption of a data chip external DDR, comprising: adding data to be written to the data chip in a case where the data chip system is lightly loaded or uncongested; Cache module;

2. The method of reducing data chip external DDR power consumption according to claim 1, wherein the cache module stores data in a shared queue management manner.

3. The method for reducing power consumption of a data chip external DDR according to claim 1, wherein the data to be written is stored in the data class in a case where the data chip system is lightly loaded or uncongested. The process of adding a cache module to the chip, including:

In the case that the amount of data storage in the cache module reaches the first watermark, the data to be written is stored in the cache module added in the data type chip.

4. The method of reducing the power consumption of a data chip external DDR according to claim 1, wherein the process of starting the external DDR in the case that the data chip system is overloaded or congested includes:

The method for reducing power consumption of a data chip external DDR according to any one of claims 1 to 4, wherein after the external DDR is activated, the method further comprises:

When the amount of data storage in the cache module reaches the third watermark, the queue with the largest amount of data cache is selected from the cache module;

Write the selected queue to the external DDR.

The method for reducing the power consumption of the data chip external DDR according to claim 5, wherein the process of writing the selected queue to the external DDR comprises: The data in the selected queue is evenly distributed to the banks of the plug-in DDR in order.

7. The method for reducing power consumption of a data chip external DDR according to claim 5, wherein the booting the DDR further comprises:

In the case where the amount of data storage in the cache module reaches the fourth watermark, a back pressure operation is performed.

A data-based chip system, comprising a DDRCTRL module, a chip, and an external DDR connected to the DDRCTRL module, wherein the chip is provided with a BUFCTRL module connected to the DDRCTRL module, and the BUFCRTL module includes a cache module and a power consumption control module connected to the cache module, where the power consumption control module includes:

a closing unit, configured to close the external DDR after the data in the external DDR is read out in a case where the data type chip system is lightly loaded or uncongested;

9. The data chip system according to claim 8, wherein the cache module is a RAM.

The data chip system according to claim 8, wherein the cache write unit is specifically configured to: when the data storage amount in the cache module reaches the first watermark, The data is stored in an added cache module within the data class chip.

The data chip system according to claim 8, wherein the activation unit is specifically configured to open the external DDR if the data storage amount in the cache module reaches a second watermark Power, and initialize.

The data chip system according to any one of claims 8 to 11, further comprising:

a queue selection unit, configured to: after the boot unit starts the plug-in DDR, When the amount of data storage in the storage module reaches the third watermark, the queue with the largest amount of data cache is selected from the cache module;

a DDR write unit, configured to write a queue selected by the queue selection unit to the external DDR.

The data chip system according to claim 12, wherein the DDR write unit is specifically configured to evenly distribute data in the selected queue to the bank of the external DDR.

The data chip system according to claim 12, further comprising: a back pressure unit, configured to perform a back pressure operation when the data storage amount in the cache module reaches a fourth water line .