CN115934614A - UART communication interface with FIFO buffer function based on APB bus - Google Patents

Abstract

The invention discloses a UART communication interface with FIFO buffer function based on an APB bus, which comprises an APB slave machine, a register control module, an FIFO and a UART bus interface controller. The output of the APB slave machine is signals including FIFO read-write signals, data streams and the like, and is responsible for writing data transmitted on an APB bus into the FIFO and reading the data from the FIFO and transmitting the data to the processor. The register control module is responsible for latching addresses on the APB and controlling configuration baud rate and other information. The FIFO module is an asynchronous FIFO and is responsible for data synchronous cache between the UART bus interface controller and the APB bus interface. The UART bus interface controller comprises a filter circuit module and a shift register module. The UART controller is flexibly configured through the AMBA bus, so that the UART controller supports functions of baud rate modification, configurable transmission bit number and parity check mode and the like. During data transmission, FIFO can buffer data, and meanwhile, UART equipment is prevented from occupying APB bus and processor for a long time, and data transmission efficiency is improved.

Description

UART communication interface with FIFO buffer function based on APB bus

Technical Field

The invention relates to a UART communication interface with FIFO buffer function based on an APB bus, belonging to the field of embedded system communication.

Background

UART (Universal Asynchronous Receiver/transmitter) is a type of Universal Asynchronous Receiver/transmitter for serial data communication. For asynchronous communications. The bus is in bidirectional communication, and full duplex transmission and reception can be realized. It may receive data from the peripheral device and convert between serial communication and parallel communication. Compared with IIC and SPI communication protocols, the UART can realize full duplex asynchronous transmission only by two lines, saves resources better, is good at remote transmission, and is widely applied to MCU multi-computer communication and various external modules for carrying out cached data transmission at present. The UART protocol specifies that the receiving data and the sending data are transmitted by one line respectively, a clock line is not needed, and the transmission rate needs to be determined by the baud rate. However, the existing UART design function is not comprehensive enough, parameters such as baud rate and frame length of part of UART interfaces cannot be configured flexibly, and communication rate and data cache between part of high-speed devices and UART devices based on an APB bus are limited, so that a single application scene is caused.

Disclosure of Invention

In view of the above-mentioned deficiencies that the bus is occupied for a long time during the communication between the high-speed device and the low-speed UART device to affect the transmission efficiency and the related parameters of the UART interface cannot be flexibly configured, the present invention improves this, and can flexibly configure the UART controller through the AMBA bus, so that the UART controller can support the functions of baud rate modification, configurable transmission bit number and parity check mode, etc. And an asynchronous FIFO buffer function is added, so that the communication between the high-speed device and the low-speed UART device can be realized. During data transmission, FIFO can buffer data, and meanwhile, UART equipment is prevented from occupying APB bus and processor for a long time, and data transmission efficiency is improved.

In order to achieve the purpose of the invention, the following technical scheme is adopted:

a UART communication interface structure with FIFO buffer function based on APB bus is shown in fig. 1, the communication interface is used between APB bus and UART bus; the UART bus communication device comprises an APB slave machine, a register control module, an FIFO, a UART bus interface controller and the like.

The APB slave machine is a connection bridge between the UART interface and the APB bus, and the APB bus controls the read/write of the whole UART internal register. It is responsible for data exchange with the CPU over the APB bus. The output of the APB slave machine is signals including FIFO read-write signals, data streams and the like, and is responsible for writing data transmitted on an APB bus into the FIFO and reading the data from the FIFO and transmitting the data to the processor.

The register control module is responsible for latching addresses on the APB and controlling configuration baud rate and other information. Meanwhile, the CPU can operate corresponding control registers and state registers through an APB bus.

The FIFO module is an asynchronous FIFO and is responsible for data synchronous buffering between the UART bus interface controller and the APB bus interface. Includes two FIFOs: one is TX _ FIFO, which is responsible for buffering data transmitted by the processor through an APB bus for the UART bus controller to read and transmit to UART equipment, specifically, when transmitting data to the UART equipment, if the controller is not busy, the processor writes the data to be transmitted into the TX _ FIFO through the APB bus, then releases the bus, relieves the UART bus controller from occupying the bus and the processor time, and the UART bus interface controller reads the data from the TX _ FIFO and transmits the data to the UART equipment; the other is RX _ FIFO, which is responsible for buffering data transmitted from the UART device, specifically, when the processor is to read or receive the data of the UART device, the UART interface controller first buffers the data transmitted by the UART device into the RX _ FIFO, during which the bus and the processor are not occupied.

The UART bus interface controller comprises a filter circuit module and a shift register module. When data is input to the UART port, glitch noise may occur. If not filtered, the received signal may exhibit meta-stability. If used directly, it may result in errors in the data transmission results. Serial reception and transmission of data is realized by a reception shift register RX _ shift and a transmission shift register TX _ shift.

Drawings

Fig. 1 is a schematic diagram of a UART communication interface module.

Fig. 2 is a UART transmission protocol timing diagram.

Fig. 3 is a timing diagram of an APB bus write operation.

Fig. 4 is a timing diagram of an APB bus read operation.

FIG. 5 is an illustration of a control register of the present invention.

Fig. 6 is a diagram illustrating a state machine when transmitting data according to the present invention.

Fig. 7 is an explanatory diagram of a state machine when receiving data according to the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a UART communication interface module.

Fig. 2 is a timing chart of data transmission of the UART transmission protocol. The UART has a receive data line and a transmit data line. When the signal line is idle and not transmitting data, the signal line is in a high level logic '1' state, which indicates that no data is transmitted on the current line. The master then first signals a logic "0" indicating the start of the transmission of the character. The data bits, which may be 5-8 bits of logical "0" or "1", are then transmitted. Such as ASCII code (7 bits), extended BCD code (8 bits) mostly uses little-endian transmission. The data bit is then followed by a parity bit, which is added to the data bit such that the number of "1" bits should be either even (even parity) or odd (odd parity). Finally, a stop bit is sent, which is an end flag of one character data. High level which can be 1 bit, 1.5 bit, 2 bit.

FIG. 3 is a timing diagram of the write operation of the APB bus. The rising edge of the clock PCLK triggers active during write transfer. The first period of T1 to T2 is IDLE state, the second period of T2 to T3 PSEL =1, and PENABLE =0 is SETUP state period, the third period of T3 to T4 PSEL =1, and PENABLE =1 is ENABLE state period, and the fourth period of T4 to T5 PSEL =0, and PENABLE =0 returns to IDLE state. After the rising edge of T2 in the figure at the start of the write transfer, the write signal PWRITE, the write address PADDR, the write data PWDATA, and the chip select signal PSEL all change to the active state, the ENABLE signal ENABLE is active at the rising edge of the next cycle, T3 in the figure, and PADDR, PWRITE, PWDATA, and PSEL remain stable throughout the ENABLE cycle, the write transfer is performed during this cycle, and the ENABLE is inactive after this cycle ends, and the write transfer is completed once. PSEL becomes inactive if the device does not continue transmission after the transmission is complete, while PADDR, PWRITE, and PWDATA have no effect on system transmission in the IDLE state, and may remain unchanged until the next transmission in order to reduce power consumption.

Fig. 4 is a timing diagram of the read operation of the APB bus. The read transfer process clock is also a rising edge trigger. The APB read operation process, PADDR, PWRITE, PSEL, penalty timing, is similar to the write operation timing except that the SETUP period PWRITE at the start of the transfer changes to low, indicating a read transfer state. Secondly, during the ENABLE period, the slave peripheral must provide valid data in advance to ensure that the rising edge of the clock at the end of the ENABLE period can be reached to ENABLE the host to read the correct data.

Fig. 5 is an explanatory diagram of the related register control. BAUD _ SEL selects bits for BAUD rate in the registers, and the highest speed can reach 115200 bits/s; PARITY _ MODE is a PARITY MODE selection bit; DATA _ LENGTH is DATA frame LENGTH selection bits, and 2'b00-2' b11 respectively represent transmission LENGTHs from 5 bits to 8 bits; STOP _ BIT is a STOP BIT length selection BIT; MSB _ SEL is the position where the selected data starts to be transmitted; TX _ FIFO _ EMPTY and TX _ FIFO _ FULL are EMPTY and FULL judging registers of a sending data buffer area; RX _ FIFO _ EMPTY and RX _ FIFO _ FULL are EMPTY determination registers of the reception data buffer. Before starting transmission, the APB SLAVE configures corresponding control bits in a control register, and the APB bus can read data of the register to carry out flexible configuration in the transmission process.

Fig. 6 is a diagram illustrating a state machine when transmitting data according to the present invention. After the circuit is reset, firstly, the IDLE state is entered, and before the UART starts to work, the APB SLAVE configures the corresponding working mode, such as the size of baud rate, the mode selection of parity check, the data frame and stop bit length, and whether the start bit of data transmission is MSB or LSB. When it is detected that the FIFO transmit data buffer is not empty, it goes to START. When the main control sends a low level start bit, the main control enters a WAIT state, then starts to send an effective data bit, enters a SHIFT state after different time intervals according to the selection of baud rate, sends a SHIFT signal, then enters the next WAIT state again, sends the next data bit, determines to send several data bits according to the length of a configured data frame, enters a PARITY state after the effective data is sent, sends a PARITY bit according to a configured mode, finally SHIFTs to a STOP state, and sends a STOP bit, thus completing the sending process of a data frame. If it is detected at this time that the FIFO send data buffer is not empty, a jump is made from the STOP state to the START state, otherwise a jump is made to the IDLE state.

Fig. 7 is a diagram illustrating a state machine when receiving data according to the present invention. Similar to the sending operation, a corresponding working mode needs to be configured firstly, the IDLE state is defaulted, when a low-level signal is detected, the START state is switched, when the low-level signal is counted to the middle of a receiving bit unit according to the setting of the baud rate, if the low-level signal is detected, the START bit is determined, the START bit alternately enters the WAIT state and the SAMPLE state along with a state machine to receive corresponding valid data bits, then the PARITY state is entered to receive PARITY bits, and finally the STOP bit is received in the STOP state to complete the whole receiving process.

While the invention has been described with reference to a particular embodiment, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (7)

1. The UART communication interface with the FIFO buffer function based on the APB bus is characterized in that the UART communication interface is used between the APB bus and the UART bus; the UART bus communication device comprises an APB slave machine, a register control module, an FIFO and a UART bus interface controller;

the APB slave computer is a connection bridge between the UART interface and the APB bus, and the APB bus controls the read/write of the whole UART internal register; the APB slave computer is responsible for exchanging data with the CPU through an APB bus; the output of the APB slave machine comprises FIFO read-write signals and data flow signals, and is responsible for writing data transmitted from the APB bus into the FIFO and reading the data from the FIFO and transmitting the data to the processor;

the register control module is responsible for latching addresses on the APB and controlling the configuration baud rate, and the CPU operates corresponding control registers and state registers through an APB bus;

the FIFO module is an asynchronous FIFO and is responsible for data synchronous cache between the UART bus interface controller and the APB bus interface; includes two FIFOs: one is TX _ FIFO, which is responsible for buffering data transmitted by the processor through the APB bus for the UART bus controller to read and transmit to the UART device, when transmitting data to the UART device, if the controller is not busy, the processor writes the data to be transmitted into the TX _ FIFO through the APB bus, then releases the bus, relieves the UART bus controller from occupying the bus and the processor time, and the UART bus interface controller reads the data from the TX _ FIFO and transmits the data to the UART device; the other is RX _ FIFO, which is responsible for buffering data transmitted from the UART device, specifically when the processor needs to read or receive the data of the UART device, the UART interface controller firstly buffers the data transmitted by the UART device into the RX _ FIFO, and no bus or processor is occupied in the period;

the UART bus interface controller comprises a filter circuit module and a shift register module; when data is input to the UART port, glitch noise may occur; if not filtered, the received signal may exhibit meta-stability; if the data transmission method is directly used, errors can be caused in data transmission results; serial reception and transmission of data is realized by a reception shift register RX _ shift and a transmission shift register TX _ shift.

2. The APB-based UART communication interface with FIFO buffer function according to claim 1, wherein the UART has a receiving data line and a transmitting data line in the data transmission sequence of the UART transmission protocol; when the signal line is idle and does not transmit data, the signal line is in a high-level logic '1' state, which indicates that no data is transmitted on the current line; then the master device first sends out a logic '0' signal to indicate the beginning of the character transmission; then sending data bits, which are 5-8 bits of logic "0" or "1"; a check bit is connected behind the data bit, and after the check bit is added to the data bit, the number of the 1 bit is an even number or an odd number; finally, a stop bit is sent, and is an end mark of character data; the character data is high level of 1 bit, 1.5 bits or 2 bits.

3. The UART communication interface with FIFO buffer function based on APB bus of claim 1, wherein in the APB bus write operation timing, the rising edge of the PCLK clock in the write transmission process is activated; wherein the first period of T1 to T2 is IDLE state, the second period of T2 to T3 PSEL =1, PENABLE =0 is SETUP state period, the third period of T3 to T4 PSEL =1, PENABLE =1 is ENABLE state period, and the fourth period of T4 to T5 PSEL =0, PENABLE =0 returns to IDLE state again; after the rising edge of T2, namely the beginning of the write transmission, the write signal PWRITE, the write address PADDR, the write data PWDATA and the chip selection signal PSEL are all changed into an effective state, T3 is realized when the rising edge of the next period comes, the ENABLE signal PENABLE is effective, in the whole ENABLE period, the PADDR, the PWRITE, the PWDATA and the PSEL are kept stable and unchanged, the write transmission is carried out in the period, and the PENABLE is invalid after the period is ended, and the write transmission is finished once; if the device does not continue transmission after the transmission is completed, PSEL becomes invalid, whereas PADDR, PWRITE, and PWDATA have no effect on system transmission in the IDLE state and remain unchanged until the next transmission in order to reduce power consumption.

4. The UART communication interface with FIFO buffer function based on APB bus of claim 1, wherein in the APB bus read operation timing, the read transmission process clock is also rising edge triggered; the APB read operation process, PADDR, PWRITE, PSEL, penalty is compared with the write operation timing, except that the SETUP period PWRITE at the start of transfer changes to low, indicating a read transfer state; during the ENABLE cycle, the slave peripheral must provide valid data ahead of time to ensure that the rising edge of the clock at the end of the ENABLE cycle can be taken for the host to read the correct data.

5. The UART communication interface with FIFO buffer function based on APB bus of claim 1, characterized in that, in the related register control, BAUD _ SEL selects bits for BAUD rate in these registers, and the highest speed can reach 115200 bits/s; PARITY _ MODE is a PARITY MODE selection bit; DATA _ LENGTH is a DATA frame LENGTH selection bit, and 2'b00-2' b11 respectively represents a transmission LENGTH from 5 bits to 8 bits; STOP _ BIT is a STOP BIT length selection BIT; MSB _ SEL is the position where the selected data starts to be transmitted; TX _ FIFO _ EMPTY and TX _ FIFO _ FULL are EMPTY and FULL judging registers of a sending data buffer area; RX _ FIFO _ EMPTY and RX _ FIFO _ FULL are EMPTY and FULL determination registers of the reception data buffer; before starting transmission, APB SLAVE configures the corresponding control bit in the control register, and APB bus reads the data of the register for configuration during transmission.

6. The UART communication interface with FIFO buffer function based on APB bus of claim 1, wherein in the description of the state machine during data transmission, the circuit first enters IDLE state after reset, and APB SLAVE configures the corresponding operation mode before the UART starts to work, such as the size of baud rate, mode selection of parity check, data frame and stop bit length and whether the start bit of data transmission is MSB or LSB; when the FIFO sending data buffer is detected not to be empty, turning to a START state; when the master control sends a low level start bit, the master control enters a WAIT state, starts to send an effective data bit, enters a SHIFT state after different time intervals according to the selection of baud rate, sends a SHIFT signal, then enters the next WAIT state again, sends the next data bit, determines to send several data bits according to the length of a configured data frame, enters a PARITY state after the effective data is sent, sends a PARITY bit according to a configured mode, finally SHIFTs to a STOP state, and sends a STOP bit, thus finishing the sending process of a data frame; if it is detected at this time that the FIFO send data buffer is not empty, a jump is made from the STOP state to the START state, otherwise a jump is made to the IDLE state.

7. The UART communication interface with FIFO buffer function based on the APB bus of claim 1, wherein in the specification of the state machine for receiving data, a corresponding operation mode needs to be configured first, similar to the transmission operation, the state is default to IDLE state, when a low level signal is detected, the state is shifted to START state, when a low level signal is detected in the middle of the receiving bit unit according to the setting count of baud rate, if it is detected that the low level signal is still low level, it is determined that it is a START bit, the state machine alternately enters WAIT state and SAMPLE state to receive corresponding valid data bit, then enters PARITY state to receive PARITY bit, and finally enters STOP state to receive STOP bit, thereby completing the whole receiving process.

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