CN103856761A - Image monitoring system based on Zynq-7000 - Google Patents
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Abstract
The invention discloses an image monitoring system based on Zynq-7000. The image monitoring system comprises an ONSEMI image sensor, wherein the ONSEMI image sensor is used for collecting image video information and transmitting the information to a Zedboard through an FMC daughter board, an HDMI-IN interface in the Zedboard obtains image data from the FMC daughter board, line field signals of video data are detected through a VTC module, the resolution ratio of images is judged according to the line field signals, the images are transmitted to a DVI2AXI module through a TPG module, the DVI2AXI module is used for converting the images output by the TPG module to be in a data format meeting an AXI-Stream interface protocol, the images are transmitted to a CRESMAPLE module through the AXI- Stream interface protocol, so that YUV data format conversion is finished, then YUV data are converted to be in a RGB data format through a YUV2GB module, image data are transmitted to a storage device for filtering treatment through a Video DMA IP core, M-JPEG is used for performing compressed encoding on the images, and then the images after compressed encoding are transmitted to a browser through a Web server. The image monitoring system has the advantages that the internal data bus speed is high, a high-performance processor is used for brilliant image processing, and the high-performance Web server is high in processing and responding speed.
Description
Technical field
The present invention relates to a kind of frequency image monitoring system based on Zynq-7000.
Background technology
Image/video monitoring, as an important element of safety-protection system, has been widely used at present the fields such as national defence, industry, traffic, the energy, information technology and daily life, and has brought into play extremely important effect.Especially in daily life, individual can build one's own frequency image monitoring system.Along with development and the popularization of correlation technique, front end is integrated, video data digitlization, monitor network, system integration have become the generally acknowledged developing direction of video monitoring system.
At present, video monitoring system mainly adopts the scheme that adds video frequency collection card based on PC, and this scheme network function is powerful, but because PC cannot be applicable to long-term continuous operation, therefore has the shortcoming that the stability of a system is low, and this can reduce the performance of whole supervisory control system.In view of this drawback, be the video image acquisition scheme that uses basic embedded web server in addition.Compared with traditional video monitoring system, Embedded network video surveillance is little with volume, cost is low, stability is high, be applicable to the advantages such as multiple complex work environment, has good application and development prospect, has become the main flow of current video supervisory control system.
Network monitoring principle based on embedded web server: on DPS or the contour performance Soc platform of ARM, the image that first-class shooting transducer is gathered or Video coding compression, be sent to built-in Web server by internal bus.User can directly use browser, obtains the image information on Web server, can also control the first-class transducer of making a video recording.
On market, the built-in network camera product of this built-in Web server has a lot, and it can pass to the data of collection in built-in Web server and check for user.But these products mostly performance are not strong, cannot process video and the image of high definition, Web server can not be processed the request of multiple accesses simultaneously, and processing speed is slow, and real-time is not strong.Therefore the present invention proposes the image/video monitoring scheme of realizing based on Zynq-7000.
Zynq-7000 be based on Xilinx complete programmable can extension process platform structure, this structure is integrated treatment system (the Processing System with the double-core ARM Cortex-A9 polycaryon processor of the feature of enriching in single-chip, and Xilinx FPGA (Field Programmable Gate Array) (Programmable Logic, PL) PS).Double-core ARM Cortex-A9 multi-core CPU is PS " heart ", and it comprises on-chip memory, external memory interface and a set of abundant I/O peripheral hardware.PL in Zynq-7000 has adopted the FPGA technology of Xilinx7 series, for expanded function, to meet specific functional requirement.
The product that Zynq-7000 combines closely high-performance ARM Cortex A series processors and high-performance FPGA as first in single-chip, compared with Xilinx FPGA is on veneer, it can be had and has the following advantages with other independent ARM Cortex-A9: design cost reduces; Design overall power reduces; Design volume reduces; Design Risk Reduction; Design more flexible.In order to realize these advantages, Xilinx not only will merge the processor of different process feature and FPGA on a chip and ensure its yields in the time of design Zynq-7000, more will design interconnected path between the interior high-performance processor of efficient sheet and FPGA.This interconnected path is realized by AXI bus, AXI is a kind of bus protocol, this agreement is most important part in the AMBA agreement that proposes of ARM company, is a kind of bus on chip towards high-performance, high bandwidth, low delay, meets the design requirement of very-high performance and complicated SOC (system on a chip).AXI ensures in sheet and the basis of interconnected high-speed communication on sheet.The internal unit of Zynq-7000 has AXI interface, and by AXI bus protocol, internal unit can carry out the communication of the low delay of high speed, and ARM and FPGA can ensure transfer of data at a high speed.
Summary of the invention
Object of the present invention is exactly in order to address the above problem, a kind of frequency image monitoring system based on Zynq-7000 is provided, and it is fast that it has internal data bus speed, and high performance processor is for picture rich in detail processing, high performance Web server, the advantages such as processing and fast response time.
To achieve these goals, the present invention adopts following technical scheme:
Based on the frequency image monitoring system of Zynq-7000, comprise ON imageing sensor, described ON imageing sensor gathers image/video information and information exchange is crossed to FMC daughter board and is uploaded to the Zedboard development board based on Zynq-7000, the treatment system Processing System of integrated double-core ARM Cortex-A9 processor and Xilinx FPGA (Field Programmable Gate Array) Programmable Logic on described Zedboard development board, the HDMI_IN interface of described Zedboard development board obtains view data from FMC daughter board, detect the row field signal of video data by VTC module, and judge the resolution of image according to row field signal, by TPG module by image transmitting to DVI2AXI module, the image of TPG module output is converted to the data format that meets AXI_Stream interface protocol by described DVI2AXI module, and transfer to CRESMAPLE module by AXI_Stream interface protocol, complete the conversion of yuv data form, then yuv data is become to RGB data format by YUV2RGB module converts, when completing after data transaction, by Video DMA IP kernel, view data is sent in memory for filtering processing again, image after filtering is finished dealing with or do not need the image of filtering, export HDMI/DVI interface chip to by LogicCVC IP kernel and complete demonstration, utilize M-JPEG to carry out after compressed encoding image, be sent to browser through Web server again.
Described by TPG module by image transmitting to DVI2AXI module, if there is external image input, will after external image collection, export DVI2AXI module to; If there is no external image input, the test pattern that produces voluntarily 1080P exports DVI2AXI module to.
Described filtering processing, if upper strata instruction is software filtering, treatment system Processing System reads image data from internal memory of double-core ARM Cortex-A9 processor completes after filtering storing back in internal memory; If upper strata instruction is hardware filtering, the hardware Sobel filtration module in Xilinx FPGA (Field Programmable Gate Array) Programmable Logic obtains view data by AXI Interconnect → AXI_HP from DDR3 memory, complete after filtering processing, then store back in DDR3 memory.
On described Zedboard development board, be equipped with LPC FMC slot, described LPC FMC slot is connected with FMC daughter board, and described LPC FMC slot is connected with HDMI_IN interface.
Connecting interface between the treatment system Processing System of described double-core ARM Cortex-A9 processor and Xilinx FPGA (Field Programmable Gate Array) Programmable Logic is three AXI Interconnect interconnect matrixes, one of them AXI Interconnect interconnect matrix is received AXI_GP port, and two other AXI Interconnect interconnect matrix is received AXI_HP interface.
The AXI Interconnect interconnect matrix of the described AXI_GP of receiving port can be connected to all hardware peripheral hardware by AXI Lite, accesses the passage of peripheral hardware register as the treatment system Processing System of double-core ARM Cortex-A9 processor.
Described two other AXI Interconnect interconnect matrix is respectively video input output hardware module, by AXI_HP reference to storage equipment, and image hardware Sobel filtering hardware module, by the connection of AXI_HP reference to storage.
Described Web server comprises authentication module, and described authentication module receives the connection request of browser, and establishes a connection with request processing module, and described request processing module comprises processing selecting module, and described processing selecting module receives the HTTP request of browser,
If dynamic requests is just utilized CGI dynamic process, module is processed, the function of first message call head processing module is processed request, initialization is also filled in CGI environmental variance, then carry out CGI function, wait for execution result, finally resolve according to CGI specification the result of returning, generate response message, fill in corresponding construction, return to processing selecting module, return to browser;
If static requests just utilizes static page processing module to process, according to the HTTP request of having resolved, first the function of message call head processing module is processed request, then the static page mirror image in audit memory, and generate corresponding information, fill in corresponding construction body weight, return to processing selecting module, return to browser.
Described ON imageing sensor is used for gathering image and video information;
Described FMC daughter board is used for carrying ON imageing sensor, and is connected with Zedboard development board;
Described Web server is used to client to use browser that the server of information browse is provided;
Described browser is used for accessing Web server, obtains needed information, such as image information.
Described authentication module is used for mainly completing the initialization of Web server, the functions such as foundation and setting parameter are dynamically connected.This module creation session table, monitors TCP80 port, for the connection request creation task receiving, finally detects each connection status, as produced mistake, closes connection or restarts server.
Described memory pages is used for storing data, herein main store image information.
Described message header processing module, for according to transmitted the different request headers and the overall head that come by processing module, requires to process according to http protocol, and result is returned to request processing module.
Described outside cgi script module is carried out respective handling for the information of submitting to according to user at server end, and information is returned to user.
Described request processing module is used for accepting HTTP request, resolves HTTP request, carries out authorization identifying, selects processing module, generates response message and sends response.First message call head is processed the function of library module and is processed request, and initialization is also filled in CGI environmental variance, then carries out CGI function, waits for execution result.Finally resolve according to CGI specification the result of returning, generate response message, fill in response structure, return to processing selecting submodule.Static page is processed submodule: according to the HTTP request of having resolved, first message call head is processed the function processing request of library module, the then static page mirror image in audit memory, and generate corresponding information, fill in corresponding construction body, return to processing selecting submodule.
Described processing selecting module, for according to different Static and dynamic requests, is selected different processing modules.
Described CGI dynamic process module is for the processing of user's dynamic requests visit data.
Described static page processing module is for the processing of user's static requests visit data.
Beneficial effect of the present invention:
1 after tested, if while completing the Sobel filtering of high-definition image with ARM Cortex-A9 processor single in Zynq-7000, processor resource is taken by 100%, but can only processing 5～6 two field pictures per second, when video output, there is obvious pause and transition in rhythm or melody sense; Switch while completing with FPGA, ARM is discharged completely, in the case of taking less than FPGA resource in 5% sheet, and the processing that can complete in real time 60 frames per second for 1080P image.Therefore the present invention utilizes the part of FPGA in Zynq to complete the preliminary treatment of high-speed video, for example splicing of expansions, burn into white balance, filtering, multi-channel video etc., and ARM is mainly responsible for control and the computing of operating system, complexity.
The internal unit of 2Zynq-7000 has AXI interface, and by AXI bus protocol, internal unit can carry out the communication of the low delay of high speed, and ARM and FPGA can ensure transfer of data at a high speed, and internal data mutual can not become the bottleneck in speed.
3 IMAQs and Web server combine, and reduce the time of image transmitting to Web server, and user transmit a request to Web server, can get image information from internal bus.
The mode that 4Web server uses Static and dynamic resume module to combine, both can process static state and obtain memory pages, also can carry out respective handling at server end by dynamic CGI, and the high-performance of Zynq-7000 ensures real-time, can process more connection request simultaneously.
Brief description of the drawings
Fig. 1 is overall architecture schematic diagram of the present invention;
Fig. 2 is the Web server schematic diagram of Fig. 1;
Fig. 3 is PS and PL interface inter-link matrix in Zedboard;
Fig. 4 is browser, server and cgi script relation.
Embodiment
Below in conjunction with accompanying drawing and embodiment, the invention will be further described.
The design of high-performance video image processing system:
On Zedboard, be equipped with a LPC FMC slot, to support more expansion daughter board.LPC FMC mono-has 160 pins, can offer 68 available single-ended I/O of user or 34 pairs of differential signals.Xilinx provides video FMC daughter board simultaneously, contains HDMI I/O and imageing sensor input function, and ONNN imageing sensor is provided simultaneously, can realize the demand of image/video collection and advanced video processing based on this hardware structure.On Zedboard, realize the schematic diagram of this scheme as shown in Figure 1.
System architecture design:
Data flow is mainly inputted from HDMI_IN by video source, after the module such as TRG, Video_MUX gathers, output valve DVI2AXI is converted into AXI interface data, then is RGB data by YUV2RGB module converts, and inputs to the medium processing to be filtered of video memory by TPG dma module.If upper strata instruction is designated as software filtering, an ARM Cortex-A9 processor will reads image data be stored back in internal memory after completing filtering from internal memory again; If upper strata instruction is designated as hardware filtering, the hardware Sobel filtration module in FPGA obtains view data by AXI Interconnect → AXI_HP from DDR3 memory, completes after filtering processing, then stores back in DDR3 memory.The effect of different IP kernels is below described.
(1) PS and PL interface inter-link matrix.One have three AXI Interconnect interconnect matrixes as PS and PL interface as shown in Figure 3, receive AXI_GP port for one, receive AXI_HP interface for two.The interconnect matrix of receiving AXI_GP interface can be connected to all hardware peripheral hardware by AXI Lite, is mainly that data traffic is not high, therefore adopts the AXI_GP port of PS part as the passage of arm processor access peripheral hardware register.Another two AXI Interconnect are respectively video input output hardware modules, and it is by AXI_HP reference to storage equipment, and image hardware Sobel filtering hardware module, and it is by the connection of AXI_HP reference to storage.Each high-speed video processing module is monopolized an AXI Interconnect to guarantee the highest efficiency of transmission, each AXI Interconnect port agreement is consistent simultaneously, each Interconnect internal agreement tts resource is reduced, and aggregate resource can obviously not increase.
(2) video image acquisition and output display.HDMI_IN module gets the view data of form CrCb4:2:2 from FMC subcard.VTC module is a module that can produce general video sequential, have measuring ability, and it judges the resolution of image mainly for detection of the row field signal of video data according to these signals.TPG module mainly completes two parts work: in the time having external image input, will after external image collection, export DVI2AXI module to; If while thering is no external image input, the test pattern that produces voluntarily 1080P exports DVI2AXI module to.The image of TPG module output is converted to the data format that meets AXI_Stream interface protocol by DVI2AXI module, and transfer to CRESMAPLE module by AXI_Stream interface protocol, complete the conversion of 4:2:2 to 4:4:4YUV data format, the original RGB data format that then yuv data is become easily to carry out image processing by YUV2RGB module converts.When completing after data transaction, then by the Video DMA IP kernel of Xilinx, view data is sent in memory for filtering processing.Image after filtering is finished dealing with or do not need the image of filtering, exports HDMI/DVI interface chip on plate to by LogicCVC IP kernel and completes demonstration.
(3) image compression module.Image compression, is the First of realizing video data Internet Transmission, not yet passes through the video image of compressed encoding, and volume is excessive, brings difficulty can to general Internet Transmission, cannot ensure the real-time of image.M-JPEG is a kind of dynamic image compression technique growing up based on Static Picture Compression technology JPEG, moving image that can formation sequence.The present invention adopts at this M-JPEG encoding software-mjpg-streamer optimizing.Utilize M-JPEG to carry out after compressed encoding image, then send through Web server.
Web server is realized:
Web server is to be connected to a kind of equipment/program that web access service is provided on network.Here, we will move a program that Web service is provided on Zedboard, make Zedboard become the equipment that Web service can be provided.In general, Web service program can be accepted HTTP request from network, then provides HTTP to reply to requestor, and HTTP comprises a html file in replying, and also can comprise the file of text, image or other types.These files generally remain in the local file system of web page server, and URL and local filename have an institutional framework, thereby Web server URL and local file is provided provide access services.
On Zedboard based on Zynq-7000, realize Web server, though Zynq-7000 is the combination of high performance ARM and FPGA, can there is higher performance than other embedded web servers, but it still has the feature of embedded system, be subject to the restriction of the external conditions such as processor ability and memory capacity.In order to reach the object of obtaining server data and Long-distance Control, must make user and local system carry out alternately, the design selects the CGI(Common gateway interface) CGI of applicable embedded system.Secondly, embedded system has higher requirement to security performance, is the problem that will solve to the safety of dynamic application content and checking.
Realize the technology that this embedded web server relates generally to and have HTML (Hypertext Markup Language) HHTP and CGI(Common gateway interface) CGI.
(1) HTML (Hypertext Markup Language).HHTP is an application layer protocol, uses TCP as transport layer protocol, and fatal http server port is 80 ports of TCP.Http protocol message, based on ASCII text, has two types: solicited message and corresponding information.
(2) CGI(Common gateway interface) CGI.CGI is the interface that moves external program on http server, and it allows to send its Output rusults to Web browser through http server.If there is no CGI, Web server just can only provide static document and the link to other pages or server, has had CGI, and program can be carried out on backstage various dynamic operations.
(3) relation of Web browser, server and cgi script.Client browser sends request to Web server by http protocol, and cgi script is communicated by letter with Web server with standard input by environmental variance, then carries out system operation by methods such as function calls.Again operating result is returned to Web server by environmental variance and standard output, Web server is sent result back to client browser by http protocol again, is illustrated in fig. 4 shown below.
This programme is made up of following module, and the relation between each module and data flow are as shown in Figure 2.
(1) authentication module.This module mainly completes the initialization of Web server, the functions such as foundation and setting parameter are dynamically connected.This module creation session table, monitors TCP80 port, for the connection request creation task receiving, finally detects each connection status, as produced mistake, closes connection or restarts server.
(2) request processing module.This module is mainly used to accept HTTP request, resolves HTTP request, carries out authorization identifying, selects processing module, generates response message and sends response.First message call head is processed the function of library module and is processed request, and initialization is also filled in CGI environmental variance, then carries out CGI function, waits for execution result.Finally resolve according to CGI specification the result of returning, generate response message, fill in response structure, return to processing selecting submodule.Static page is processed submodule: according to the HTTP request of having resolved, first message call head is processed the function processing request of library module, the then static page mirror image in audit memory, and generate corresponding information, fill in corresponding construction body, return to processing selecting submodule.
(3) message header processing module.According to transmitted the different request headers and the overall head that come by processing module, require to process according to http protocol, and result is returned to request processing module.
By reference to the accompanying drawings the specific embodiment of the present invention is described although above-mentioned; but not limiting the scope of the invention; one of ordinary skill in the art should be understood that; on the basis of technical scheme of the present invention, those skilled in the art do not need to pay various amendments that creative work can make or distortion still in protection scope of the present invention.
Claims (8)
1. the frequency image monitoring system based on Zynq-7000, it is characterized in that, comprise ON imageing sensor, described ON imageing sensor gathers image/video information and information exchange is crossed to FMC daughter board and is uploaded to the Zedboard development board based on Zynq-7000, the treatment system Processing System of integrated double-core ARM Cortex-A9 processor and Xilinx FPGA (Field Programmable Gate Array) Programmable Logic on described Zedboard development board, the HDMI_IN interface of described Zedboard development board obtains view data from FMC daughter board, detect the row field signal of video data by VTC module, and judge the resolution of image according to row field signal, by TPG module by image transmitting to DVI2AXI module, the image of TPG module output is converted to the data format that meets AXI_Stream interface protocol by described DVI2AXI module, and transfer to CRESMAPLE module by AXI_Stream interface protocol, complete the conversion of yuv data form, then yuv data is become to RGB data format by YUV2RGB module converts, when completing after data transaction, by Video DMA IP kernel, view data is sent in memory for filtering processing again, image after filtering is finished dealing with or do not need the image of filtering, export HDMI/DVI interface chip to by LogicCVC IP kernel and complete demonstration, utilize M-JPEG to carry out after compressed encoding image, be sent to browser through Web server again.
2. the frequency image monitoring system based on Zynq-7000 as claimed in claim 1, is characterized in that, described by TPG module by image transmitting to DVI2AXI module, if there is external image input, will after external image collection, export DVI2AXI module to; If there is no external image input, the test pattern that produces voluntarily 1080P exports DVI2AXI module to.
3. the frequency image monitoring system based on Zynq-7000 as claimed in claim 1, it is characterized in that, described filtering processing, if upper strata instruction is software filtering, treatment system Processing System reads image data from internal memory of double-core ARM Cortex-A9 processor completes after filtering storing back in internal memory; If upper strata instruction is hardware filtering, the hardware Sobel filtration module in Xilinx FPGA (Field Programmable Gate Array) Programmable Logic obtains view data by AXI Interconnect → AXI_HP from DDR3 memory, complete after filtering processing, then store back in DDR3 memory.
4. the frequency image monitoring system based on Zynq-7000 as claimed in claim 1, is characterized in that, has been equipped with LPC FMC slot on described Zedboard development board, and described LPC FMC slot is connected with FMC daughter board, and described LPC FMC slot is connected with HDMI_IN interface.
5. the frequency image monitoring system based on Zynq-7000 as claimed in claim 1, it is characterized in that, connecting interface between the treatment system Processing System of described double-core ARM Cortex-A9 processor and Xilinx FPGA (Field Programmable Gate Array) Programmable Logic is three AXI Interconnect interconnect matrixes, one of them AXI Interconnect interconnect matrix is received AXI_GP port, and two other AXI Interconnect interconnect matrix is received AXI_HP interface.
6. the frequency image monitoring system based on Zynq-7000 as claimed in claim 5, it is characterized in that, the AXI Interconnect interconnect matrix of the described AXI_GP of receiving port can be connected to all hardware peripheral hardware by AXI Lite, accesses the passage of peripheral hardware register as the treatment system Processing System of double-core ARM Cortex-A9 processor.
7. the frequency image monitoring system based on Zynq-7000 as claimed in claim 5, it is characterized in that, described two other AXI Interconnect interconnect matrix is respectively video input output hardware module, by AXI_HP reference to storage equipment, and image hardware Sobel filtering hardware module, by the connection of AXI_HP reference to storage.
8. the frequency image monitoring system based on Zynq-7000 as claimed in claim 1, it is characterized in that, described Web server comprises authentication module, described authentication module receives the connection request of browser, and establish a connection with request processing module, described request processing module comprises processing selecting module, and described processing selecting module receives the HTTP request of browser
If dynamic requests is just utilized CGI dynamic process, module is processed, the function of first message call head processing module is processed request, initialization is also filled in CGI environmental variance, then carry out CGI function, wait for execution result, finally resolve according to CGI specification the result of returning, generate response message, fill in corresponding construction, return to processing selecting module, return to browser;
If static requests just utilizes static page processing module to process, according to the HTTP request of having resolved, first the function of message call head processing module is processed request, then the static page mirror image in audit memory, and generate corresponding information, fill in corresponding construction body weight, return to processing selecting module, return to browser.
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| CN112231263B (en) * | 2020-10-29 | 2022-12-09 | 超越科技股份有限公司 | FPGA intermediate layer card extends device |
| CN113891039A (en) * | 2021-09-17 | 2022-01-04 | 长春一汽富晟集团有限公司 | Image acquisition and processing system and method for vehicle-mounted all-round viewing system |
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