CN102521190A - Hierarchical bus system applied to real-time data processing - Google Patents
Hierarchical bus system applied to real-time data processing Download PDFInfo
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Abstract
The invention discloses a hierarchical bus system, which comprises a real-time high-speed bus, a non-real-time high-speed bus, a non-real-time low-speed bus, a low-speed bus interconnection module, a high-speed bus interconnection module, a high-speed storage, an embedded processor, a real-time bus input/output module, a real-time bus data processing module, a non-real-time high-speed bus input/output module and a non-real-time low-speed bus input/output module. The real-time bus input/output module, the real-time bus data processing module and the high-speed storage are connected with the real-time high-speed bus through real-time high-speed bus interfaces; the embedded processor and the non-real-time high-speed bus input/output module are connected with the non-real-time high-speed bus through non-real-time high-speed bus interfaces; the non-real-time low-speed bus input/output module is connected with the non-real-time low-speed bus through a non-real-time low-speed bus interface; the non-real-time low-speed bus is connected with the non-real-time high-speed bus through the low-speed bus interconnection module; and the non-real-time high-speed bus is connected with the real-time high-speed bus through the high-speed bus interconnection module. By the aid of the hierarchical bus system, mega data can be efficiently transmitted and processed by the hierarchical bus system in real time, and bus bandwidth is effectively used.
Description
Technical field
The present invention relates to SOC(system on a chip) technical field in the integrated circuit, relate in particular to a kind of multistage bus system that is applied to real time data processing of SOC(system on a chip).
Background technology
SOC(system on a chip) (System on Chip) is the inexorable trend of integrated circuit technique development, along with dwindling of semiconductor feature sizes, and the raising of chip integration, increasing function is integrated in the chip.Chip functions is constantly abundant, and (Intellectual Property IP) constantly increases integrated IP kernel, makes the framework of SOC(system on a chip) also become increasingly complex.Particularly in the real time data processing field, the bus system that design has real-time and high data bandwidth is current research focus.
In the real time data processing field, bus system is simple as far as possible, because the topological structure of the interconnection of SOC(system on a chip) can not be too complicated, so that the real-time of influence response.Secondly; The topological structure of bus system is wanted to reflect the status of each interconnect module in system; If all interconnect modules all are in same status in bus system, then will cause the important module can't initiation request, and low-speed module be occupied bus and do not have the situation of bus request.At last, bus system will have bigger dirigibility, realizes the interconnected of each module because the target of SOC(system on a chip) is a physics cost with minimum, and bus system need all can meet the demands under different application scenes.Though the bus system of SOC(system on a chip) possesses above peculiar requirement, with bus system in the PC a lot of identical points are arranged on function and topological structure, so the development of the bus system in the PC can be offered reference for the bus system of SOC(system on a chip).
Based on above principle, current popular bus system is a unibus system.As shown in Figure 1, adopt a bus to connect all interfacing equipments, cause the travelling speed of each module to mate, bus width is because the wooden barrel effect can influence the data throughput speed of real-time processing module.Fig. 2 is for adopting the bus system of flush bonding processor, and it has higher flexibility, and processing speed data processing module faster can be independent of bus with higher speed operation, and the speeds match of bus and data processing module is accomplished through synchronous logic.This system preferably resolves travelling speed mismatch problems between the inconsistent module of travelling speed; But this bus system does not have extendability; When module increases; Synchronous logic is difficult on the travelling speed of each module, average out, thereby causes the performance of system significantly to reduce with the increase of module.
In sum, the current bus system that is applied to real time data processing also has problems with the system performance aspect aspect extendability.
Summary of the invention
The technical matters that (one) will solve
Technical matters to be solved by this invention is how to make the expansion of bus system have more dirigibility, solves the performance mismatch problem between the disparate modules simultaneously.
(2) technical scheme
Multistage bus system of the present invention comprises real time high-speed bus, non real-time high-speed bus, non real-time low speed bus, HSM, real-time bus input/output module, real-time bus data processing module, non real-time high-speed bus input/output module, non real-time low speed bus input/output module, high-speed bus interconnect module and low speed bus interconnect module; Wherein the real time high-speed bus is used for the transmission and the processing of real-time big data quantity; The non real-time high-speed bus, the big data quantity that is used for non real-time property transmits and handles; The non real-time low speed bus is used for the transmission and the processing of small data quantity; HSM is used to satisfy the call data storage of each module on the bus system; Real time high-speed bus input/output module is used to control the reception and the transmission of high speed input/output port, and carries out protocol analysis, data buffering, the data sync of realization cross clock domain; The real time high-speed bus data processing module is used for the data of input are carried out feature extraction, the coded format conversion, and special efficacy appears and noise filtering, accomplishes the intensive processing of operation of data; Non real-time high-speed bus input/output module is used for cooperating with real time high-speed bus input/output module, and the high speed of carrying out non-real-time data transmits; Non real-time low speed bus input/output module, the low speed that is used for small data quantity transmits; The high-speed bus interconnect module is used for accomplishing the data interaction between non real-time high-speed bus and the real time high-speed bus; The low speed bus interconnect module is used for accomplishing the data interaction between non real-time low speed bus and the non real-time high-speed bus.
(3) beneficial effect
The invention provides a kind of new Real-Time Data Handling System (RTDHS) bus system, when can realize that multimode is handled in real time, support the integrated of low-speed device, and the system that guarantees has extendability flexibly, simultaneously the overall performance of sacrificial system not.
Description of drawings
Fig. 1 is the synoptic diagram of traditional Real-Time Data Handling System (RTDHS) bus system;
Fig. 2 is the synoptic diagram of traditional bus system based on flush bonding processor;
Fig. 3 is the synoptic diagram of the multistage bus system of one embodiment of the present of invention;
Fig. 4 is the embodiment synoptic diagram of multistage bus system that number of modules is expanded;
Fig. 5 is the embodiment synoptic diagram of multistage bus system that bus progression is expanded.
Embodiment
For making the object of the invention, technical scheme and a bit more clear, will combine the accompanying drawing among the present invention below, the technical scheme among the present invention is carried out detailed, complete description.
The invention provides a kind of multistage bus system, comprising: the real time high-speed bus is used for the transmission and the processing of real-time big data quantity; The non real-time high-speed bus, the big data quantity that is used for non real-time property transmits and handles; The non real-time low speed bus is used for the transmission and the processing of small data quantity; And HSM, real-time bus input/output module, real-time bus data processing module, non real-time high-speed bus input/output module, non real-time low speed bus input/output module, high-speed bus interconnect module and low speed bus interconnect module.This multistage bus system can active balance be respectively asked the bus holding time of initiation module, realizes large data sets is transmitted in real time and handles.
The real time high-speed bus is the bus of real-time response and high data bandwidth, is used to realize the arbitration to multimode, and the alignment of data of data sync with the different bit wides of different clock-domains is provided;
The non real-time high-speed bus provides the bus of high data bandwidth, allows operating delay response that each module is initiated, to carry out operation scheduling and to reorder;
HSM is the large-capacity data memory bank, is used to satisfy the call data storage of each module on the bus system, and is operated in the real-time bus clock zone;
Real time high-speed bus input/output module, the reception and the transmission of control high speed input/output port, and carry out protocol analysis, data buffering, the data sync of realization cross clock domain;
The real time high-speed bus data processing module is carried out feature extraction to the data of input, the coded format conversion, and special efficacy appears and noise filtering, accomplishes the intensive processing of operation of data;
Non real-time high-speed bus input/output module cooperates with real time high-speed bus input/output module, and the high speed of carrying out non-real-time data transmits;
Non real-time low speed bus input/output module, the low speed that is used for small data quantity transmits;
The high-speed bus interconnect module is used for the data interaction between non real-time high-speed bus and the real time high-speed bus;
The low speed bus interconnect module is used for the data interaction between non real-time low speed bus and the non real-time high-speed bus.
Fig. 3 is a specific embodiment that is applied to the multistage bus system of real time data processing of the present invention, and this multistage bus system comprises real time high-speed bus, non real-time high-speed bus, non real-time low speed bus, flush bonding processor, HSM, real time high-speed bus input/output module, post-processing module, ethernet module, non real-time low speed bus input/output module, low speed bus interconnect module and high-speed bus interconnect module.
Real time high-speed bus input/output module, real-time bus data processing module and HSM link to each other with the real time high-speed bus through the real time high-speed EBI; Flush bonding processor, ethernet module link to each other with the non real-time high-speed bus through the non real-time high speed bus interface; Non real-time low speed bus input/output module links to each other with the non real-time low speed bus through non real-time low speed bus interface; The non real-time low speed bus links to each other with the non real-time high-speed bus through the low speed bus interconnect module, and the non real-time high-speed bus links to each other with the real time high-speed bus through the high-speed bus interconnect module.
The real time high-speed bus links to each other with the equipment that has real-time to require, and is used to accomplish the request that is connected to equipment on the real time high-speed bus is arbitrated and responded its read-write requests, and read-write requests is sent to HSM.The real time high-speed bus can be the AXI bus, but the present invention is not limited to this, also can be other bus that possesses the real-time response.If other bus realizes that the equipment interface that then is connected on the real time high-speed bus need be done corresponding conversion, be other EBI with the AXI interface conversion of each equipment.The realization of this adaptability conversion can be and equipment integration soft kernel form together, also can be independent entity parts.
The equipment that the non real-time high-speed bus is big with data throughout and real-time is less demanding links to each other; Its read-write requests is arbitrated and is responded in the request that is used to accomplish being connected to equipment on the non real-time high-speed bus; Read-write requests is sent to the real time high-speed bus through the high-speed bus interconnect module, finally send to HSM through the real time high-speed bus.The non real-time high-speed bus can be AXI bus (frequency of operation is lower than the real time high-speed bus), but the present invention is not limited to this, also can be that other possesses the bus of supporting big data throughout.If other bus realizes that the equipment interface that then is connected on the non real-time high-speed bus need be done corresponding conversion, be other EBI with the AXI interface conversion of each equipment.The realization of this adaptability conversion can be and equipment integration soft kernel form together, also can be independent entity parts.
The equipment that the non real-time low speed bus is little with data throughout and real-time is less demanding links to each other; Its read-write requests is arbitrated and is responded in the request that is used to accomplish being connected to equipment on the non real-time low speed bus; Read-write requests is sent to the non real-time high-speed bus through the low speed bus interconnect module; Send to flush bonding processor through the non real-time high-speed bus, or send to the real time high-speed bus, send to HSM through the real time high-speed bus through the high-speed bus interconnect module.The non real-time low speed bus can be an ahb bus, but the present invention is not limited to this, also can be that other possesses the bus of supporting the small data handling capacity.If other bus realizes that the equipment interface that then is connected on the non real-time high-speed bus need be done corresponding conversion, be other EBI with the AHB interface conversion of each equipment.The realization of this adaptability conversion can be and equipment integration soft kernel form together, also can be independent entity parts.
Flush bonding processor links to each other with the non real-time high-speed bus, is used for real time high-speed bus input/output module is carried out the configuration and the start-up control of mode of operation, the filter factor of configuration post-processing module.And according to user's requirement, regulate the tupe of aftertreatment, the startup of control Ethernet, the input and output request of response low speed bus interconnect module.Flush bonding processor can be the flush bonding processor of compatible ARM and/or MIPS instruction set, also can be the flush bonding processor of other instruction set.
Real time high-speed bus input and output module, an end links to each other with the real time high-speed bus, and the other end (not shown) that links to each other with a standard interface is used to receive video and the audio-frequency information that sends from this standard interface, and real-time being written in the HSM.And; Configuration parameter according to flush bonding processor; Real time high-speed bus input/output module reads original video and the audio frequency that is stored in the HSM or passes through optimization of video and the audio frequency that post-processing module was handled, and sends to the transmitting terminal of standard interface with corresponding resolution and refresh rate.This real time high-speed bus input and output module can be to support the input/output module of HDMI standard, and the standard interface that is attached thereto can be the HDMI interface, but the present invention is not limited to this, also can be DVI standard interface or other video standard interface.
HSM can be DDR3 SDRAM, also can be the HSM of other types such as DDR2 SDRAM, is used to store video information and processed video information of input etc.
Post-processing module is the real time high-speed bus data processing module; It links to each other with the real time high-speed bus; Be used for reading the vedio data that is stored in HSM, according to video image information, to vedio data carry out staggered scanning and line by line scan between conversion; According to the filter factor of flush bonding processor configuration, start respective filter vedio data is handled in real time, generate with optimization of video or special efficacy; According to the aftertreatment mode of operation, whether decision-making carries out the conversion of chrominance space to vedio data; Final processing rear video view data is write back in the HSM.Post-processing module can be the realization of chip form, also can be that the form of soft nuclear realizes.
Ethernet module links to each other with the non real-time high-speed bus; It is a kind of non real-time high-speed bus input/output module; Be used for accomplishing the mutual of multistage bus system of the present invention and remote user end (not shown among Fig. 3); The long-distance user can send various instructions to ethernet module through Ethernet is long-range, the startup and the mode of operation of control chart 3 said multistage bus systems of the present invention, and the response or the result of this system turned back to remote user end through Ethernet.This ethernet module can be a Gigabit Ethernet module, perhaps ten thousand mbit ethernet modules.
Non real-time low speed bus input/output module can be AHB, GPIO (general input and output) and UART (universal asynchronous receiver), is used for realizing the system debug and the external interrupt of the said system of Fig. 3.
Low speed bus interconnect module one end links to each other with the non real-time low speed bus, and the other end links to each other with the non real-time high-speed bus, is used for accomplishing the data interaction between non real-time low speed bus and the non real-time high-speed bus.This low speed bus interconnect module can be interconnected between the same bus agreement of different operating frequency of finishing the work, and also can be to accomplish interconnected between the different bus agreement.The low speed bus interconnecting modules can be realized software programmable through configuration register, to adapt to the different application scene.
High-speed bus interconnect module one end links to each other with the non real-time high-speed bus, and the other end links to each other with the real time high-speed bus, is used for accomplishing the data interaction between non real-time high-speed bus and the real time high-speed bus.This low speed bus interconnect module can be interconnected between the same bus agreement of different operating frequency of finishing the work, and also can be to accomplish interconnected between the different bus agreement.The high-speed bus interconnecting modules can be realized software programmable through configuration register, to adapt to the different application scene.
As a preferred embodiment of the present invention; In based on multistage bus system shown in Figure 3; Real time high-speed bus AXI-1 (is to distinguish with non real-time high-speed bus AXI; Add label-1), HDMI reception and sending module, post-processing module be operated in 150MHz, HSM is that DDR3SDRAM is operated in 300MHz, non real-time high-speed bus AXI-2 (is to distinguish with real time high-speed bus AXI; Add label-2), flush bonding processor, ethernet module be operated in 125MHz, non real-time low speed bus AHB, GPIO and UART module are operated in 75MHz.
Fig. 4 has shown the synoptic diagram of another embodiment of the present invention, the multistage bus system that its number of modules that multistage bus system connected that is based on Fig. 3 is expanded.This multistage bus system comprise processing module that every grade of bus connects, extension process module 1, extension process module 2 ..., extension process module n etc.With multistage bus system shown in Figure 3, this expands the link block number that multistage bus system has been expanded this system's each grade bus relatively, makes a plurality of processing modules with equal processing speed and bandwidth demand can be integrated into in the one-level bus.For example on the real time high-speed bus, except that embodiment shown in Figure 3, input and output module that can also integrated DVI, the input and output modules of VGA etc. make multistage bus system under the constant situation of bus progression, integrated more function module.
Fig. 5 has shown another embodiment of the present invention, the multistage bus system that its progression that is based on the multistage bus system of Fig. 3 is expanded.This multistage bus system comprise real time high-speed bus, non real-time high-speed bus, non real-time low speed bus, expansion bus 1, expansion bus 2 ..., expansion bus n etc., also comprise a plurality of expansion bus interconnect modules.Each expansion bus interconnects through said expansion bus interconnect module, and links to each other with the non real-time low speed bus.
With respect to multistage bus system shown in Figure 3, this expands the progression that multistage bus system has further expanded bus, makes this system can support abundanter processing module.When system becomes increasingly complex; The processing speed of various processing modules and bandwidth demand different; Make simple unified in three grades of bus systems shown in Figure 3 difficulty comparatively; The progression of expansion bus can be under the prerequisite that does not change described system performance of Fig. 3 and basic framework, and integrated more function makes system have more competitive power.
The operational process of multistage bus system shown in Figure 3 is following:
1) after system powered on, flush bonding processor read the boot instruction, accomplishes the initialization of flush bonding processor.To being configured of each processing module of bus, and start each processing module, executive utility according to boot instruction.
2) Ethernet is with the instruction of the mode receiving remote user side of web server, the operational mode through real-time each processing module of adjusting of flush bonding processor and operational factor etc.And will need feedback data to turn back to remote user end, and can show through display through Ethernet.
3) after input/output module starts; Load module receives the video image of input; According to the configuration parameter of processor, vedio data is written to the appropriate address of HSM, output module reads the image information of appropriate address in the HSM; Through the HDMI cable, send in real time on the external display device such as display or televisor.
4) after post-processing module starts; Appropriate address from HSM reads pending video information; Mode of operation and filter factor to configure carry out filtering operation or multiple filter bank closing operation to video image; Realize that picture quality optimization or special efficacy generate, accomplish as required and change between chrominance space conversion, staggered scanning and the progressive scanning mode of video image etc.At last the video image information of handling well is write back in the HSM.
5) input/output module or postprocessor module work get into when unusual, and flush bonding processor can show with the respective coding mode abnormal information through GPIO, and the user can carry out the debugging breakpoints of flush bonding processor through the UART module.
The present invention at the scene programmable gate array (Field Programmable Gate Array, FPGA) on the development platform through checking, can satisfy the real-time data acquisition of hyperchannel big data quantity, special efficacy generates, video optimized and real-time demonstration.
Above-described specific embodiment; The object of the invention, technical scheme and beneficial effect have been carried out further explain, and institute it should be understood that the above is merely specific embodiment of the present invention; Be not limited to the present invention; All within spirit of the present invention and principle, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (19)
1. multistage bus system; It is characterized in that; Comprise real time high-speed bus, non real-time high-speed bus, non real-time low speed bus, HSM, real-time bus input/output module, real-time bus data processing module, non real-time high-speed bus input/output module, non real-time low speed bus input/output module, high-speed bus interconnect module and low speed bus interconnect module, wherein:
The real time high-speed bus is used for the transmission and the processing of real-time big data quantity;
The non real-time high-speed bus, the big data quantity that is used for non real-time property transmits and handles;
The non real-time low speed bus is used for the transmission and the processing of small data quantity;
HSM is used to satisfy the call data storage of each module on the bus system;
Real time high-speed bus input/output module is used to control the reception and the transmission of high speed input/output port, and carries out protocol analysis, data buffering, the data sync of realization cross clock domain;
The real time high-speed bus data processing module is used for the data of input are carried out feature extraction, the coded format conversion, and special efficacy appears and noise filtering, accomplishes the intensive processing of operation of data;
Non real-time high-speed bus input/output module is used for cooperating with real time high-speed bus input/output module, and the high speed of carrying out non-real-time data transmits;
Non real-time low speed bus input/output module, the low speed that is used for small data quantity transmits;
The high-speed bus interconnect module is used for accomplishing the data interaction between non real-time high-speed bus and the real time high-speed bus;
The low speed bus interconnect module is used for accomplishing the data interaction between non real-time low speed bus and the non real-time high-speed bus.
2. multistage bus system as claimed in claim 1; It is characterized in that: real time high-speed bus input/output module, real-time bus data processing module and HSM link to each other with the real time high-speed bus; Non real-time high-speed bus input/output module links to each other with the non real-time high-speed bus, and non real-time low speed bus input/output module links to each other with the non real-time low speed bus.
3. multistage bus system as claimed in claim 1 is characterized in that: the non real-time low speed bus links to each other with the non real-time high-speed bus through the low speed bus interconnect module, and the real time high-speed bus is continuous with it through the high-speed bus interconnect module for the non real-time high-speed bus.
4. multistage bus system as claimed in claim 1 is characterized in that: said real time high-speed bus is used to provide the alignment of data of data sync with the different bit wides of different clock-domains.
5. multistage bus system as claimed in claim 1 is characterized in that: the operating delay that said non real-time high-speed bus allows each module is initiated responds, to carry out operation scheduling and to reorder.
6. multistage bus system as claimed in claim 1 is characterized in that: said HSM has high capacity, and is operated in the real-time bus clock zone.
7. multistage bus system as claimed in claim 1 is characterized in that: also comprise the flush bonding processor that links to each other with the non real-time high-speed bus, be used for real time high-speed bus input/output module is carried out the configuration and the start-up control of mode of operation.
8. multistage bus system as claimed in claim 7 is characterized in that: said flush bonding processor is the flush bonding processor of compatible ARM and/or MIPS instruction set.
9. multistage bus system as claimed in claim 1 is characterized in that: also comprise the post-processing module that links to each other with the real time high-speed bus, be used for the data processing of real time high-speed bus.
10. multistage bus system as claimed in claim 1 is characterized in that: said non real-time high-speed bus input/output module is an ethernet module, is used for the mutual of said multistage bus system and remote user end.
11. multistage bus system as claimed in claim 1 is characterized in that: said real time high-speed bus input and output module is to support the input/output module or the DVI standard interface of HDMI standard.
12. multistage bus system as claimed in claim 1 is characterized in that: said HSM is DDR3 SDRAM or DDR2 SDRAM.
13. multistage bus system as claimed in claim 1 is characterized in that: non real-time low speed bus input/output module is GPIO interface or UART interface.
14. multistage bus system as claimed in claim 1 is characterized in that: the real time high-speed bus is the AXI bus.
15. multistage bus system as claimed in claim 1 is characterized in that: the non real-time high-speed bus is the AXI bus.
16. multistage bus system as claimed in claim 1 is characterized in that: also comprise a plurality of expansion modules, said real time high-speed bus, non real-time high-speed bus, non real-time low speed bus link to each other with some extension process modules respectively.
17. multistage bus system as claimed in claim 1 is characterized in that: also comprise a plurality of expansion bus and a plurality of expansion bus interconnect module, said expansion bus interconnects through said expansion bus interconnect module, and links to each other with the non real-time low speed bus.
18. multistage bus system as claimed in claim 1 is characterized in that: said low speed bus interconnecting modules can be realized software programmable through configuration register, to adapt to the different application scene.
19. multistage bus system as claimed in claim 1 is characterized in that: said high-speed bus interconnecting modules can be realized software programmable through configuration register, to adapt to the different application scene.
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