CN109089029B

CN109089029B - FPGA-based Gige Vision interface image transmission system and method

Info

Publication number: CN109089029B
Application number: CN201811029173.0A
Authority: CN
Inventors: 易清明; 陈若峰; 石敏
Original assignee: Jinan University
Current assignee: Jinan University
Priority date: 2018-09-05
Filing date: 2018-09-05
Publication date: 2020-11-13
Anticipated expiration: 2038-09-05
Also published as: CN109089029A

Abstract

The invention discloses a system and a method for image transmission of a Gige Vision interface based on FPGA, comprising an image sensor, an upper computer, a local gigabit Ethernet and an embedded image acquisition device based on a Gige interface, wherein the embedded image acquisition device based on the Gige interface is a core device of the system and comprises an FPGA chip and a PHY chip; the FPGA signal input end is connected with the image sensor output signal end; the FPGA is in signal connection with the PHY chip; the PHY chip is connected with the RJ45 interface, and the RJ45 interface is connected with the PC upper computer through a network cable. The image acquisition embedded system based on the FPGA and the Gige interface has high transmission efficiency and long transmission distance, and has the advantages of less occupied logic resources, lower hardware requirement and the like compared with the similar IP core in the industry.

Description

FPGA-based Gige Vision interface image transmission system and method

Technical Field

The invention relates to the technical field of digital image processing, in particular to a system and a method for image transmission of a Gige Vision interface based on an FPGA.

Background

With the continuous development of computer network communication and multimedia technology, the progress and maturity of image processing technology, the application of image processing systems is more and more extensive in the fields of medical treatment, biological feature recognition, machine vision, military, remote sensing monitoring and the like, and in any field, the data transmission research in the image processing systems is one of the key points of research. Compared with the traditional transmission technology, such as a hundred-mega Ethernet technology, an RS232 interface and other interfaces aiming at transmitting simple information, the bandwidth provided by the existing high-speed interface technology, such as a USB interface, a Camera Link interface, an IEEE 1394 interface, a GigE gigabit Ethernet interface and the like, is larger, and the large data requirement required by high-definition and large data can be met. Compared with other interfaces, the gigabit Ethernet interface has the advantages of large bandwidth, long transmission distance and capability of being seamlessly upgraded to the gigabit Ethernet in image transmission. The FPGA has the inherent characteristics of strong parallel data processing capacity, online programmability, static programmability of dynamic system reconstruction and the like, so that the FPGA has wide application in the field of image transmission.

Disclosure of Invention

The invention mainly aims to overcome the defects in the prior art, and provides a Gige Vision interface image transmission system based on an FPGA (field programmable gate array), which combines a gigabit Ethernet and the FPGA and adopts Gige Vision as a transmission protocol, so that the problems of high hardware cost, short transmission distance and high running power consumption in the traditional embedded image transmission can be effectively solved.

The invention also aims to provide a method for image transmission of the Gige Vision interface based on the FPGA.

The purpose of the invention is realized by the following technical scheme:

an FPGA-based Gige Vision interface image transmission system, comprising: the image acquisition system comprises an image sensor, an upper computer, a local gigabit Ethernet and an embedded image acquisition device based on a Gige interface, wherein the embedded image acquisition device based on the Gige interface is a core device of the system and comprises an FPGA chip and a PHY chip; the signal input end of the FPGA chip is connected with the signal output end of the image sensor; the FPGA chip and the PHY chip are in signal connection with each other; the PHY chip is connected with an upper computer;

the FPGA chip includes: the system comprises an image acquisition module (1), an image format processing module (2), a GVCP control module (3), an Ethernet protocol stack module (4) and an Ethernet control module (5);

the working process of the system comprises the following steps:

1) the camera, the embedded image acquisition equipment and the upper computer are connected into the same local area network, the system is electrified and initialized, the upper computer reads the equipment state, configures the equipment parameters and automatically sends a discovery instruction and a starting instruction, and the system starts to work;

2) the camera acquires image data, transmits the image data to the embedded image acquisition equipment, performs format encapsulation after analysis and pretreatment according to the acquired data packet corresponding to the embedded image acquisition equipment, and uploads the data and parameters to the upper computer after the signaling interaction between the upper computer and the equipment is completed;

3) and the upper computer displays the selected camera image and the image parameters in real time.

Preferably, the image acquisition module (1) is used for connecting the embedded image acquisition equipment with the image sensor and is responsible for carrying out equipment configuration and image data acquisition on the CMOS image sensor;

the image format processing module (2) is used for preprocessing the image acquired by the image sensor, and the realization functions comprise packet cutting and format packaging of the input image data so as to enable the input image data to meet the transmission standard of a GVSSP (global positioning system protocol) data stream protocol;

the GVCP control module (3) is responsible for interacting with a GVCP control protocol sent by an upper computer;

the Ethernet protocol stack module (4) is responsible for carrying out Ethernet grid type encapsulation on data sent by the upstream module so that the Ethernet protocol stack module meets the requirement of a gigabit Ethernet transmission format, has the automatic response functions of ARP and ICMP protocols, can analyze ARP request datagram sent by the upper computer, automatically sends corresponding ARP and ICMP response data packets for response, and caches the input MAC address and IP address of the upper computer into the static cache list module;

and the Ethernet control module (5) realizes control and signal interaction on the PHY chip, and comprises the addition of a lead code and a CRC check code, so that the data meets the transmission requirement of a physical layer.

Specifically, the image acquisition module (1) comprises a camera parameter table module (1.1), a camera configuration module (1.2), a camera interface module (1.3) and an image acquisition interface module (1.4);

the image format processing module (2) is a single module;

the GVCP control module (3) comprises an equipment discovery configuration module (3.1), an equipment register read-write module (3.2), an equipment memory read-write module (3.3) and a GVCP message convergence module (3.4);

the Ethernet protocol stack module (4) comprises an ARP _ IP gathering and analyzing module (4.1), an ARP analyzing module (4.2), an ARP sending module (4.3), a static list caching module (4.4), an IP analyzing module (4.5), an ICMP analyzing module (4.6), a UDP analyzing module (4.7), an ICMP sending module (4.8), a message converging module (4.9), a UDP sending module (4.10) and a UDP packet cutting module (4.11);

the Ethernet control module (5) comprises a MAC control module (5.1), a MAC interface module (5.2), a MAC configuration module (5.3) and a PLL module (5.4).

Preferably, the real-time processing of the upper computer under the embedded image acquisition equipment comprises reading an XML file, analyzing the XML file, discovering equipment, generating a configuration interface, signaling interaction, image caching and displaying.

A method for image transmission of a Gige Vision interface based on FPGA comprises the following steps:

a) the camera, the embedded image acquisition equipment and the upper computer are connected into the same local area network, and the system is electrified and initialized;

b) the upper computer sends a signaling message GVCP, performs information interaction with the FPGA through a gigabit Ethernet interface, negotiates and configures a general boot register and a user register in the equipment;

c) after the upper computer finishes the basic equipment read-write register operation, reading an equipment XML description file in a signaling message form;

d) the upper computer software automatically analyzes the XML file, if the analysis is successful, the next step is carried out, otherwise, the software reports errors and returns to the step c);

e) the upper computer generates a configuration interface and a transmission channel;

f) enabling image equipment to collect according to a user-defined register, and starting image collection operation;

g) carrying out format encapsulation and Ethernet transmission on the acquired image;

h) and shutting down and finishing the operation.

Preferably, the signaling message flow interaction process between the upper computer and the embedded image acquisition device includes:

receiving a signaling message: the PC sends a signaling message and is connected with the PHY chip through a network cable; the gigabit Ethernet PHY chip transmits the GVCP signaling message to an Ethernet control module (5), the Ethernet control module removes a lead code from the message, and transmits the message to an Ethernet protocol stack module (4) after CRC (cyclic redundancy check); in an Ethernet protocol stack module, data is firstly transmitted to an ARP _ IP total analysis module (4.1), MAC address verification is carried out on input data, after an MAC header format is removed, a GVCP signaling message is sent to an IP data stream according to an IP type segment in the data, and the GVCP signaling message is transmitted to an IP analysis module (4.5); the IP analysis module (4.5) can carry out IP address verification and header error detection code verification on the input data stream, extract IP address information from the data segment for caching, remove the IP header of the signaling message and transmit the signaling message data to the UDP analysis module (4.7) for analysis according to the type of the data stream; the UDP analysis module can carry out checksum calculation processing on the input data, filter messages with checksum errors and send the rest data to the GVCP control module (3) after the UDP head is removed; the GVCP control module performs reading, checking and protocol processing operations according to the received signaling message and generates internal instruction operation equipment according to the signaling message;

and (3) signaling message sending: and after receiving and processing the signaling message, the GVCP control module sends a response message to the upper computer. Firstly, the GVCP generates corresponding response messages according to different signaling types, the response messages are dispatched by a GVCP message convergence module (3.4) and then sent to a UDP packet cutting module (4.11), and whether packet cutting is needed or not and the length of the cut packets is determined according to the length requirement of the sent messages.

Specifically, the data is sent to a UDP sending module (4.10) after passing through a packet cutting module, MAC head encapsulation and IP encapsulation are carried out on the input data, UDP check sums are calculated according to a data part and a head format part, UDP head encapsulation is carried out, and then complete data is sent to a message aggregation module (4.9) for FIFO cache; the Ethernet control module (5) reads data according to the empty and full state of the data FIFO stored in the message aggregation module, adds a lead code and CRC to a reply message, and finally sends the reply message to a PC upper computer for interaction through a network twisted pair.

Specifically, the structure of the bale cutting module is as follows: the data input end needs to input information including a data part, head and tail indication signals sop and eop of data, a data valid signal vld, and a destination IP address, a destination physical address, a destination port and a source port which need to be sent; the port information and the address information are respectively sent to the corresponding FIFO modules for caching; the data part is added with two counters cnt _1472 and cnt _18 before the FIFO buffer, and the FIFO output end is also double counter logic which is cnt _1 and cnt _ 2; the cnt _1472 calculates the input data when data are input, and adds a condition of din _ vld signal, and the cnt _18 starts counting only when the length of the input data exceeds 1454 bytes, namely the count of the cnt _1472 is finished, and stores the counting length into the information FIFO; and at the output end of the FIFO, the cnt _2 is responsible for counting the number of stages, if the data length is too long, the data is transmitted by two ends, and the cnt _1 is responsible for counting the actual number of output bytes.

Preferably, after the upper computer and the embedded image acquisition equipment complete the interaction of the signaling message, the upper computer will automatically send an image acquisition starting command to start image acquisition, wherein the sending process of the image data stream GVSP is as follows: the image acquisition module (1) acquires image data according to the image acquisition time sequence requirement of the image sensor and transmits the image data to the image format processing module (2); after being subjected to packet cutting and packaging by the image format processing module, the image data is sent to a message convergence module (4.9) of the Ethernet protocol stack module to be dispatched and transmitted by the Ethernet control module; and after a lead code and CRC are added in the Ethernet control module, the Ethernet control module is sent to an upper computer for displaying through a PHY chip.

Specifically, the image format processing module encapsulates the input data into a form of MAC + IP + UDP + GVSP + data and transmits the data.

Specifically, the image format processing module further needs to adjust length input to perform packet cutting transmission on a frame of image data according to the size of the acquired image, and the length of the length is the length set by the SCPS register when the upper computer signals are interacted.

Compared with the prior art, the invention has the following advantages and beneficial effects:

(1) based on the FPGA chip, the invention realizes the logical module structure and data flow of image acquisition by designing each part of logical modules (comprising five large modules, namely an image acquisition module, an image format processing module, a GVCP control module, an Ethernet protocol stack module and an Ethernet control module, wherein each module is composed of a plurality of small modules) in the FPGA chip, thereby effectively reducing the hardware cost, the operation power consumption and the volume on one hand, and effectively increasing the data processing capacity, the data processing efficiency and the energy efficiency ratio on the other hand. The invention can be widely applied to industrial field monitoring based on machine vision.

(2) The invention contains protocol stack supporting ICMP, ARP, UDP, IP protocol analysis and transmission in the scheme realization, and the protocol stack has high performance packet cutting module, compared with the protocol stack of the same type, it can improve the bandwidth utilization rate of gigabit Ethernet and the encapsulation of the protocol stack, and is convenient for the user to use.

Drawings

FIG. 1 is a flowchart of the overall operation of the embodiment.

Fig. 2 is a signaling interaction flow diagram of an embodiment.

Fig. 3 is a diagram of the UDP cut-off module.

Fig. 4 is a diagram showing the structure of an image format processing module.

Fig. 5 is a state transition diagram of the image format processing module.

Fig. 6 is a block diagram of system modules of an embodiment.

Detailed Description

The present invention will be described in further detail with reference to examples and drawings, but the present invention is not limited thereto.

Example 1

In order to overcome the defects of large logic resource consumption, high hardware cost and the like of the traditional Gige IP core, the invention simplifies the Protocol according to the content of the Gige Vision Protocol and the requirement of an Ethernet transmission format to design an IP core which supports a Control Message Protocol (Internet Control Message Protocol, ICMP), an Address Resolution Protocol (ARP), a User Datagram Protocol (UDP), a gigabit Ethernet visual Control Protocol (GVCP), a gigabit Ethernet visual data Stream Protocol (GVCP) and packet analysis, and transmits image data to an upper computer for real-time display according to the requirement of the Gige Vision Protocol by utilizing the parallel processing property of the FPGA.

The image transmission system comprises a CMOS image sensor, a PC upper computer, a local gigabit Ethernet and an embedded image acquisition device based on a Gige interface, wherein the embedded image acquisition device based on the Gige interface is a core device of the system and comprises an FPGA chip, a PHY chip and an RJ45 interface. The FPGA signal input end is connected with the output signal end of the CMOS image sensor; the FPGA is in signal connection with the PHY chip; the PHY chip is connected with the RJ45 interface, and the RJ45 interface is connected with a PC upper computer through a network cable. Logic modules of all parts are designed in the FPGA chip, and the logic modules comprise: the image acquisition module (1), the image format processing module (2), the GVCP control module (3), the Ethernet protocol stack module (4) and the Ethernet control module (5) are realized by using a hardware description language Verilog, meet the requirements of a Gige Vision transmission protocol and an Ethernet transmission protocol format and conform to a GMII interface specification.

Wherein:

s1, the image acquisition module (1) comprises a camera parameter list module (1.1), a camera configuration module (1.2), a camera interface module (1.3) and an image acquisition interface module (1.4);

s2, the image format processing module (2) is a single module;

s3, GVCP control module (3) includes device discovery configuration module (3.1), device register read-write module (3.2), device memory read-write module (3.3), GVCP message convergence module (3.4);

s4, the Ethernet protocol stack module (4) comprises an ARP _ IP gathering and analyzing module (4.1), an ARP analyzing module (4.2), an ARP sending module (4.3), a static list caching module (4.4), an IP analyzing module (4.5), an ICMP analyzing module (4.6), a UDP analyzing module (4.7), an ICMP sending module (4.8), a message converging module (4.9), a UDP sending module (4.10) and a UDP packet cutting module (4.11);

s5, the Ethernet control module (5) comprises a MAC control module (5.1), a MAC interface module (5.2), a MAC configuration module (5.3) and a PLL module (5.4).

And the image acquisition module (1) is used for connecting the embedded acquisition equipment with the image sensor and is responsible for carrying out equipment configuration and image data acquisition on the CMOS image sensor.

And the image format processing module (2) is responsible for preprocessing the image acquired by the image sensor, is realized by adopting a single module on the realization of the logic module, and has the functions of packet cutting, format packaging and the like on the input image data so as to ensure that the input image data meets the transmission standard of a GVSSP (global video protocol for short) data stream protocol.

The GVCP control module (3) is divided into three sub-modules on the division of a logic structure and comprises an equipment discovery module, an equipment register read-write module and an equipment memory read-write module, and the control module is responsible for interacting with a GVCP control protocol sent by an upper computer.

The Ethernet protocol stack module (4) is divided into a plurality of modules on the logic structure for realization, is mainly responsible for carrying out Ethernet grid type encapsulation on data sent by an upstream module so that the Ethernet protocol stack module meets the requirement of a gigabit Ethernet transmission format, has automatic response functions of ARP and ICMP protocols, can analyze ARP request datagram sent by an upper computer, automatically sends corresponding ARP and ICMP response data packets for response, and caches the input MAC address and IP address of the upper computer in the static cache list module.

The Ethernet control module (5) is divided into four modules on the logic structure for realization, and comprises control and signal interaction on a PHY chip, addition of a lead code and a CRC check code and the like, so that data can meet the transmission requirement of a physical layer.

The real-time processing of the lower computer of the embedded acquisition equipment by the computer as the upper computer comprises reading an XML file, analyzing the XML file, finding the equipment, generating a configuration interface, interacting signaling, caching and displaying images. The working process of the system is as follows:

1) the camera, the embedded image acquisition equipment and the computer are connected into the same local area network, the system is electrified and initialized, the upper computer reads the equipment state, configures the equipment parameters and automatically sends a discovery instruction and a starting instruction, and the system starts to work;

The FPGA in the embedded image acquisition equipment adopts Altera's CYCLONE IV series model number as EP4CE15F17C 8.

The ethernet PHY in the embedded image capture device is selected from RTL8211EG from Realtek corporation.

The upper computer display software in the embedded image acquisition system is Halcon of MVtec company.

Example 2

Referring to fig. 1, a Gige Vision interface image transmission implementation method based on an FPGA includes the following general operation flows:

a) the camera, the embedded image acquisition equipment and the computer are connected to the same local area network, and the system is electrified and initialized;

h) and shutting down and finishing the operation.

Referring to fig. 2, a signaling message flow interaction process between the upper computer and the embedded image acquisition device:

receiving a signaling message: the PC sends a signaling message and is connected with the PHY chip through a network cable; the gigabit Ethernet PHY chip transmits the GVCP signaling message to an Ethernet control module (5), the Ethernet control module removes a lead code from the message, and transmits the message to an Ethernet protocol stack module (4) after CRC (cyclic redundancy check); in an Ethernet protocol stack module, data is firstly transmitted to an ARP _ IP total analysis module (4.1), MAC address verification is carried out on input data, after an MAC header format is removed, a GVCP signaling message is sent to an IP data stream according to an IP type segment in the data, and the GVCP signaling message is transmitted to an IP analysis module (4.5); the IP analysis module (4.5) can carry out IP address verification and header error detection code verification on the input data stream, extract IP address information from the data segment for caching, remove the IP header of the signaling message and transmit the signaling message data to the UDP analysis module (4.7) for analysis according to the type of the data stream; the UDP analysis module can carry out checksum calculation processing on the input data, filter messages with checksum errors and send the rest data to the GVCP control module (3) after the UDP head is removed; the GVCP control module performs reading, checking and protocol processing operations according to the received signaling message and generates internal instruction operation equipment according to the signaling message.

Referring to fig. 3, the structure diagram of the UDP packet cutting module is different from that of the conventional packet cutting module, and the addition of the packet cutting module can reduce the condition that zero padding is required due to the existence of a large number of short packets in the gigabit ethernet network, thereby improving the utilization rate of the network bandwidth. The module structure is as follows: the data input end needs to input the data part, the head and tail indication signals sop and eop of the data, the data valid signal vld, and the information of the destination IP address, the destination physical address, the destination port, the source port, etc. which need to be sent. The port information and the address information are respectively sent to the corresponding FIFO modules for caching; in the data part, in order to reduce the situation that the input message is too small and needs to be supplemented with 0, two counters cnt _1472 and cnt _18 are added in front of the FIFO cache, and the FIFO output end is also double-counter logic which is cnt _1 and cnt _ 2; cnt _1472 counts the input data when data is input, plus a din _ vld signal, and cnt _18 starts counting and stores the count length in the information FIFO only when the input data length exceeds 1454 bytes, i.e., the count of cnt _1472 ends. And at the output end of the FIFO, the cnt _2 is responsible for counting the number of stages, if the data length is too long, the data is transmitted by two ends, and the cnt _1 is responsible for counting the actual number of output bytes.

The data is sent to a UDP sending module (4.10) after passing through a packet cutting module, MAC head encapsulation and IP encapsulation are carried out on the input data, UDP check sums are calculated according to the data part and the head format part, UDP head encapsulation is carried out, and then the complete data is sent to a gathering module (4.9) for FIFO cache; the Ethernet control module (5) reads data according to the empty and full state of the data FIFO stored in the convergence module, adds a lead code and CRC to the reply message, and finally sends the reply message to a PC upper computer for interaction through a network twisted pair.

The PHY management interface signals of the Ethernet control module are MDC and MDIO signals.

The GMII interaction signal of the Ethernet control module is a 125M working clock.

After the upper computer and the embedded image acquisition equipment complete the interaction of the signaling message, the PC upper computer software can automatically send an image acquisition starting command to start image acquisition, wherein the sending flow of the image data stream GVPP is as follows: the image acquisition module (1) acquires image data according to the image acquisition time sequence requirement of the image sensor and transmits the image data to the image format processing module (2).

The structural diagram of the image format processing module refers to fig. 4. And encapsulating the input data into a form of MAC + IP + UDP + GVSSP + data for transmission, wherein checksum calculation is required during UDP encapsulation, Image format is adopted for GVSSP encapsulation, and state conversion refers to FIG. 5.

The image format processing module also needs to adjust length input to perform Packet cutting transmission on a frame of image data according to the size of the acquired image, wherein the length of the length is set by an SCPS (stream Channel Packet size) register when the signaling of the upper computer is interacted.

After being subjected to packet cutting and packaging by the image format processing module, the image data is sent to a message convergence module (4.9) of the Ethernet protocol stack module to be dispatched and transmitted by the Ethernet control module; and after a lead code and CRC are added in the Ethernet control module, the Ethernet control module is sent to an upper computer for display through a PHY chip and RJ 45.

After the upper computer receives the Ethernet transmission data, Halcon software can carry out imaging display on the acquired data.

The above embodiments are preferred embodiments of the present invention, but the present invention is not limited to the above embodiments, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be construed as equivalents thereof, and all such changes, modifications, substitutions, combinations, and simplifications are intended to be included in the scope of the present invention.

Claims

1. A kind of Gige Vision interface image transmission system based on FPGA, characterized by that, including: the image acquisition system comprises an image sensor, an upper computer, a local gigabit Ethernet and an embedded image acquisition device based on a Gige interface, wherein the embedded image acquisition device based on the Gige interface is a core device of the system and comprises an FPGA chip and a PHY chip; the signal input end of the FPGA chip is connected with the signal output end of the image sensor; the FPGA chip and the PHY chip are in signal connection with each other; the PHY chip is connected with an upper computer;

the working process of the system comprises the following steps:

3) the upper computer displays the selected camera image and the image parameters in real time;

the image acquisition module (1) is used for connecting the embedded image acquisition equipment with the image sensor and is responsible for carrying out equipment configuration and image data acquisition on the CMOS image sensor;

2. The FPGA-based Gige Vision interface image transmission system of claim 1, wherein the image acquisition module (1) comprises a camera parameter table module (1.1), a camera configuration module (1.2), a camera interface module (1.3) and an image acquisition interface module (1.4);

the image format processing module (2) is a single module;

3. The FPGA-based Gige Vision interface image transmission system of claim 1, wherein the real-time processing of the upper computer under the embedded image acquisition device comprises reading XML files, parsing XML files, discovering devices, generating configuration interfaces, signaling interaction, image caching and display.

4. A Gige Vision interface image transmission method based on the system of claim 2, comprising the steps of:

h) and shutting down and finishing the operation.

5. The Gige Vision interface image transmission method of claim 4, wherein the signaling message flow interaction process between the upper computer and the embedded image acquisition device comprises:

and (3) signaling message sending: after receiving and processing the signaling message, the GVCP control module sends a response message to the upper computer; firstly, the GVCP generates corresponding response messages according to different signaling types, the response messages are dispatched by a GVCP message convergence module (3.4) and then sent to a UDP packet cutting module (4.11), and whether packet cutting is needed or not and the length of the cut packets is determined according to the length requirement of the sent messages.

6. The Gige Vision interface image transmission method of claim 5, wherein the data is sent to a UDP sending module (4.10) after passing through a packetization module, the input data is subjected to MAC header encapsulation and IP encapsulation, and UDP checksum is calculated according to the data portion and the header format portion, and then UDP header encapsulation is performed, and then the complete data is sent to a message aggregation module (4.9) for FIFO buffering; the Ethernet control module (5) reads data according to the empty and full state of the data FIFO stored in the message aggregation module, adds a lead code and CRC to a reply message, and finally sends the reply message to a PC upper computer for interaction through a network twisted pair.

7. The Gige Vision interface image transmission method of claim 6, wherein the cut-and-wrap module is configured as follows: the data input end needs to input information including a data part, head and tail indication signals sop and eop of data, a data valid signal vld, and a destination IP address, a destination physical address, a destination port and a source port which need to be sent; the port information and the address information are respectively sent to the corresponding FIFO modules for caching; the data part is added with two counters cnt _1472 and cnt _18 before the FIFO buffer, and the FIFO output end is also double counter logic which is cnt _1 and cnt _ 2; the cnt _1472 calculates the input data when data are input, and adds a condition of din _ vld signal, and the cnt _18 starts counting only when the length of the input data exceeds 1454 bytes, namely the count of the cnt _1472 is finished, and stores the counting length into the information FIFO; and at the output end of the FIFO, the cnt _2 is responsible for counting the number of stages, if the data length is too long, the data is transmitted by two ends, and the cnt _1 is responsible for counting the actual number of output bytes.

8. The Gige Vision interface image transmission method of claim 4, wherein after the upper computer and the embedded image acquisition device complete the interaction of the signaling messages, the upper computer automatically sends an image acquisition start command to start image acquisition, wherein the sending process of the image data stream GVSP is as follows: the image acquisition module (1) acquires image data according to the image acquisition time sequence requirement of the image sensor and transmits the image data to the image format processing module (2); after being subjected to packet cutting and packaging by the image format processing module, the image data is sent to a message convergence module (4.9) of the Ethernet protocol stack module to be dispatched and transmitted by the Ethernet control module; and after a lead code and CRC are added in the Ethernet control module, the Ethernet control module is sent to an upper computer for displaying through a PHY chip.

9. The Gige Vision interface image transmission method of claim 4, wherein the image format processing module encapsulates the input data into a form of MAC + IP + UDP + GVSP + data and transmits the data; the image format processing module also needs to adjust length input to carry out packet cutting and sending on a frame of image data according to the size of the collected image, and the length of the length is the length set by the SCPS register when the upper computer signals are interacted.