CN103294836A - PCIE (peripheral component interconnect express) based radar data acquisition displaying and controlling system and method thereof - Google Patents

PCIE (peripheral component interconnect express) based radar data acquisition displaying and controlling system and method thereof Download PDF

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CN103294836A
CN103294836A CN2013101921733A CN201310192173A CN103294836A CN 103294836 A CN103294836 A CN 103294836A CN 2013101921733 A CN2013101921733 A CN 2013101921733A CN 201310192173 A CN201310192173 A CN 201310192173A CN 103294836 A CN103294836 A CN 103294836A
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module
data
interface
message
acquisition
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CN2013101921733A
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全英汇
周换
李亚超
邢孟道
陈杰
姚新东
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西安电子科技大学
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Abstract

The invention discloses a PCIE (peripheral component interconnect express) based radar data acquisition displaying and controlling system and a method thereof. The PCIE based radar data acquisition displaying and controlling system comprises an upper computer module, a PCIE interface module, an FPGA (field programmable gate array) control module, an AD acquisition module and a storage module. The upper computer module is used for setting and processing parameters, sending and processing information and displaying images. The PCIE interface module is used for sending information and transmitting data between the upper computer module and the FPGA control module. The FPGA control module completes receiving and transmitting of the data and is responsible for controlling the modules. The AD acquisition module completes data acquisition. The storage module is used for storing the data. The method includes that the acquired data are transmitted to the upper computer module by means of a TLP (thread-level parallelism) data package and then drawn into an image to be displayed on a screen by means of a double buffer technique by the upper computer module according to set displaying parameters. The PCIE based radar data acquisition displaying and controlling system and the method thereof reduce system cost, increase data transmission rate and can be applied to a radar data acquisition system, particularly a system high in data transmission rate and strong in instantaneity.

Description

基于PCIE的雷达数据采集显控系统及其方法 Display and control system and method for collecting radar data based on the PCIE

技术领域 FIELD

[0001] 本发明属于通信技术领域,更进一步涉及数字信号处理技术领域中的一种基于外设组件互连高速扩展总线(Peripheral Component Interconnect Express, PCIE)的雷达数据采集显控系统及其方法。 [0001] The present invention belongs to the field of communication technologies, and further relates to a digital signal processing technologies in high-speed expansion bus based on Peripheral Component Interconnect (Peripheral Component Interconnect Express, PCIE) radar system and method for controlling data display capture. 本发明可用于雷达数据采集系统中,特别是数据传输速率高,实时性强的系统中。 The present invention can be used in radar data acquisition system, in particular a high data transfer rate, and real time systems. 本发明利用现场可编程门阵列(Field Programmable Gate Array,FPGA)内嵌的PCIE端点模块核(Endpoint Block Plus for PCI Express)组成的基于PCIE的雷达数据采集显控系统及其方法,可以实现对雷达采集的数据进行高速处理。 Display and control system and method of the present invention using a field programmable gate array (Field Programmable Gate Array, FPGA) core modules embedded PCIE endpoint (Endpoint Block Plus for PCI Express) based on the radar data acquisition PCIE composition can be achieved on the radar high speed data acquisition process.

背景技术 Background technique

[0002] 雷达技术的迅猛发展对雷达数据采集系统不断提出更高的要求。 The rapid development of [0002] radar technology for radar data acquisition system continuously put forward higher requirements. 其数据量大、实时性强的特点,要求数据采集系统具有高采集速率和高数据吞吐能力。 Its large amount of data, and real time characteristics and requirements of the data acquisition system having a high acquisition rate and a high data throughput. 但是,目前用于PC机的数据采集显控系统大多数是基于PCI总线,其最大缺点就是数据传输速率低、实时性不强。 However, the current data collection for the PC display and control systems are mostly based on the PCI bus, its biggest drawback is the low data rate, real-time performance is not strong. 同时,以往的数据采集系统在软件、驱动和硬件方面不同程度的存在数据采集速率、数据传输速率低等若干问题,在实用性和可靠性方面无法有效推广。 Meanwhile, in the conventional data acquisition system software, drivers and hardware of the presence of different levels of data rate, data transmission rate and low number of problems can not be effectively promoted in practicality and reliability. 而且,雷达数据采集系统在提供给用户使用的过程中,因为用户显控软件的不人性化给最终系统的交付产生了很大的影响。 Moreover, the radar data acquisition system in the process available to users, since users are not user-friendly display and control software to the final delivery of the system had a great impact.

[0003] 上海易罗信息科技有限公司提出的专利申请“雷达数据采集系统及其采集方法”(专利申请号200710037078.0,公开号CN101178434A)公开了雷达数据采集系统及其采集方法。 [0003] Information Technology Co., Ltd. Shanghai Yi Luo a patent application filed "Radar Data Acquisition System and its acquisition method" (Patent Application No. 200710037078.0, Publication No. CN101178434A) discloses a radar data acquisition system and its acquisition method. 该系统包括采集控制功能装置和主机数据记录接口装置,其中系统还包括存储功能模块,主机数据记录接口装置为PCI总线控制装置,PCI总线控制装置通过PCI总线与数据记录主机连接,采集控制功能装置分别与存储功能模块、PCI总线控制装置相连。 The system comprises a collection control means and the host data recording interface means, wherein the system further comprises a storage function module, host data recording interface means is a PCI bus controller, a PCI bus control means connected to acquisition control function via the PCI bus and the data recording host apparatus storage function module respectively, PCI bus is connected to the control means. 方法包括将采集的雷达数据信号进行采样量化处理、将经过处理后的数据传至存储功能模块中、将数据从存储功能模块中取出并通过PCI总线控制装置传送至数据记录主机。 The method comprises the radar data sampling quantization signal acquisition process, the, the data out and transmitted to the host through the PCI bus data records from the storage means the control function module transmitted via the data storage function module after the treatment. 但是,该系统和方法存在的不足是,第一,由于PCI总线的数据传输速率理论上最高为132MB/S,不能满足数据高速传输,增加系统开销。 However, the present system and method is the lack of, first, since the data transfer rate of PCI bus theoretically up to 132MB / S, can not meet the high-speed data transmission, increasing system overhead. 第二,数据以压缩方式传输,不能满足大数据传输,效率较低,数据传输错误率较高。 Second, the data transmission in a compressed manner, the data transmission can not meet the large, less efficient, higher data transmission error rate. 第三,主机用户记录实现采用单任务单线程,系统的功耗高,系统利用率低,处理能力较差。 Third, the host user to realize recording of high-power single-threaded single-task system, the system utilization is low, poor processing capabilities. 第四,由于主机只有用户记录,模块功能单一,操作性和直观性差。 Fourth, since the host only user record, single function module, inferior operability and intuitive.

[0004] 而PCIE总线具备高速率、高可靠性、低成本和扩展性强等特点。 [0004] PCIE bus and includes a high-rate, high reliability, low cost, and scalability features. 在当前所有需要通过计算机I/o总线进行交互的硬件系统中,PCIE总线逐渐成为雷达数据采集显控系统实现高速传输的首选。 In the hardware system requires all currently interacting through the computer I / o bus, PCIE bus becoming the preferred data acquisition radar display and control system of high-speed transmission.

发明内容 SUMMARY

[0005] 本发明的目的在于针对上述已有技术的不足,提出一种基于PCIE的雷达数据采集显控系统及其方法,以满足大数据量、高速传输的要求,满足用户通过上层软件实施控制底层板卡,达到良好的功能效果,人性化的用户体验,同时减少系统的功耗。 [0005] The object of the present invention is the above-described deficiencies of prior art, to provide a display and control system and a method based on the radar data acquisition PCIE to meet the requirements of large amount of data, high-speed transmission, to meet the user through the upper control software embodiment the bottom of the board, to achieve good functional results, intuitive user experience, while reducing system power consumption. [0006] 为实现上述目的,本发明包括: [0006] To achieve the above object, the present invention comprises:

[0007] 一种基于PCIE的雷达数据采集显控系统,包括上位机模块,PCIE接口模块,FPGA控制模块,AD采集模块和存储模块;所述上位机模块通过PCIE接口模块与FPGA控制模块连接,AD采集模块与FPGA控制模块连接,存储模块与FPGA控制模块连接。 [0007] A radar-based data acquisition was PCIE control system, comprising a host computer module, the interface module PCIE, FPGA control module, the AD acquisition module and a storage module; the PC module through the PCIE FPGA control module and interface module, FPGA AD acquisition module and control module, a storage module and control module FPGA. 其中: among them:

[0008] 所述的上位机模块,采用多线程技术,用于设置处理参数,对FPGA模块发送处理消息,对采集的数据进行存储,对数据进行处理和图形显示。 [0008] The host computer module multithreading technique, processing for setting the parameters, the FPGA message transmission processing module, for storing acquired data, data processing and graphic display.

[0009] 所述的PCIE接口模块,是通过配置FPGA内嵌的PCIE端点模块核来实现,用于上位机模块和FPGA模块之间发送消息和传输数据。 [0009] PCIE said interface module is realized by configuring the FPGA core module PCIE end embedded, for transmitting a message and for transferring data between the host computer module and the FPGA module.

[0010] 所述的FPGA控制模块,用于接收上位机模块发送的处理消息,完成高速数据的接收、传输,负责系统各个模块之间的控制。 [0010] The FPGA control module of the control between the reception, transmission, each module is responsible for high-speed data receiving system, the host computer module for handling messages sent to complete.

[0011] 所述的AD采集模块,主要完成雷达数据的采集。 [0011] The AD of the acquisition module, mainly to complete the acquisition of the radar data.

[0012] 所述的存储模块,用于缓存AD采集的数据。 Storage module [0012] according to, for acquisition of data cache AD.

[0013] 本发明方法的具体步骤如下: [0013] In particular steps of the method of the invention is as follows:

[0014] (I)设置参数: [0014] (I) set parameters:

[0015] Ia)用户在上位机模块中,根据所需的处理方法选择采集控制、DMA (DirectMemory Access)传输、图形显不; [0015] Ia) user PC module, according to the processing method of selecting a desired acquisition and control, DMA (DirectMemory Access) transmission, no significant pattern;

[0016] Ib)用户在处理方法对应的设置窗口中,输入采集参数控制、DMA传输参数、显示控制参数。 [0016] Ib) user setting window corresponding to the processing method, the input control acquisition parameters, the DMA transfer parameters, the display control parameters.

[0017] (2)产生界面消息: [0017] (2) generates an interface message:

[0018] 由上位机模块采用在步骤(I)中所选择的操作方法,对步骤(I)设置的参数进行消息响应,生成界面消息。 [0018] The operation by the host computer module in process step (I) the selected parameters in step (I) is provided in response to a message, generating an interface message.

[0019] (3)发送界面消息: [0019] (3) Send Message Interface:

[0020] 上位机将界面消息通过高速串行总线PCIE接口发送给FPGA控制模块。 [0020] The PC interface high-speed serial bus PCIE interface message sent to the FPGA control module.

[0021] (4)判断是否收到消息: [0021] (4) determines whether a received message:

[0022] 上位机模块判断是否收到高速串行总线PCIE接口发送给FPGA控制模块的界面消息,若未收到界面消息,则执行步骤(2),重新产生界面消息;如果收到界面消息,则执行步骤(5)。 [0022] The PC interface module determines whether the received message PCIE speed serial bus interface to send to the FPGA control module, the interface message has not been received, then step (2), regenerate the message interface; if the interface receives the message, executing step (5).

[0023] (5)判断收到的界面消息是否为关闭界面消息: [0023] (5) determines whether the received message interface screen off message:

[0024] 上位机模块判断收到的界面消息是否为关闭界面消息,如果收到的界面消息为关闭界面消息,则执行步骤(13);如果收到的界面消息为采集控制、DMA传输、图形显示三种界面消息中的一种,则执行步骤(6)。 [0024] The PC interface module determines that the received message is a message to close the screen, if the received message is closed interface interface message, step (13); if the received message interface to acquire control, the DMA transfer pattern a display screen three kinds of message, step (6).

[0025] (6)消息分配: [0025] (6) assigned message:

[0026] 6a)FPGA控制模块根据收到的界面消息得到相应的操作方法和操作参数; [0026] 6a) FPGA control module to give the corresponding operating method and operating parameters of the interface according to the received message;

[0027] 6b)FPGA控制模块向AD采集模块发送采集控制相应的操作方法和操作参数。 [0027] 6b) FPGA control module sends acquisition module to control the respective AD collection operating method and operating parameters.

[0028] (7)采集数据: [0028] (7) Data collection:

[0029] 7a) AD采集模块接收FPGA控制模块发送的采集控制相应的操作方法和操作参数,根据操作方法和操作参数得到开始采集指令和处理参数; [0029] 7a) collecting AD acquisition module receives FPGA control module sends a control operation method and a corresponding operating parameters, and begin acquiring instruction processing parameters and the operation method in accordance with the operating parameters obtained;

[0030] 7b)当AD采集模块接收到开始采集指令后,根据其所接收到的处理参数,进行数据采集;[0031 ] 7c) AD采集模块采集完数据后,向FPGA控制模块发送采集结束指令。 [0030] 7b) when the AD collection module receives the acquisition start instruction, the processing parameters according to which it is received, data acquisition; [0031] 7c) AD After the data collecting module, the control module transmits acquisition end command to the FPGA .

[0032] (8) DMA 数据传输: [0032] (8) DMA data transfer:

[0033] 8a) FPGA控制模块接收AD采集模块发送的采集结束指令; [0033] 8a) collected FPGA control module receives the transmitted AD end instruction acquisition module;

[0034] 8b) FPGA控制模块接收AD采集模块采集的数据,存入存储模块中; [0034] 8b) FPGA control module receives a data acquisition module of AD, stored in the memory module;

[0035] 8c) FPGA控制模块根据步骤(5)中收到的DMA传输相应的操作方法和操作参数,将采集数据通过高速串行总线PCIE接口,发送回上位机模块。 [0035] 8c) FPGA control module in accordance with step (5) received in the corresponding DMA transfer operation method and operation parameters, data will be collected by a high speed serial bus PCIE interface, sent back to the host computer module.

[0036] (9)数据上位机存储: [0036] (9) a data storage PC:

[0037] 上位机模块将发送来的采集数据存储到上位机硬盘中。 [0037] transmitted to host computer module stores the acquired data to the PC hard disk.

[0038] (10)绘图: [0038] (10) the drawing:

[0039] 上位机模块根据步骤(5)中收到的图形显示相应的操作方法和操作参数将存储到上位机硬盘的数据读取到缓存中,采用双缓存技术进行绘图。 [0039] PC module according to step (5) received in the display pattern corresponding to the operating methods and the parameters stored in the PC hard disk data read into the cache, using the double buffer technique for drawing.

[0040] (11)显示绘图图像: [0040] (11) to display the drawing image:

[0041] 上位机模块将绘图图像显示到屏幕上。 [0041] The drawing module PC image is displayed on the screen.

[0042] (12)判断是否继续显示绘图图像: [0042] (12) determines whether to continue to display the drawing image:

[0043] 上位机模块判断是否继续显示绘图图像,如果不继续显示绘图图像,则转入执行步骤(4);若继续显示绘图图像,则执行步骤(10)。 [0043] The host computer module determines whether to continue to display the drawing image, if not to continue to display the drawing image, the process proceeds to step (4); if it continues to display the drawing image, the step is performed (10).

[0044] (13)界面关闭。 [0044] (13) off the interface.

[0045] 本发明与现有技术相比具有如下优点: [0045] The prior art and the present invention has the following advantages:

[0046] 第一,由于本发明的系统采用FPGA内嵌PCIE端点模块核实现PCIE接口,解决了现有技术采用PCI总线导致的传输速率较低的缺点,由此使得本发明数据传输的速率得到大大提闻。 [0046] First, since the system of the invention uses embedded FPGA core implementation PCIE end PCIE interface module, the prior art addresses the shortcomings of a lower transmission rate due to the PCI bus, whereby the data transmission rate of the present invention is obtained greatly improve the smell.

[0047] 第二,由于本发明的系统采用了多线程技术,实现多任务同步进行,解决了现有技术单线程在执行过程中耗时的缺点,由此使得本发明可以提高系统利用率,降低系统功耗,增强处理能力。 [0047] Second, since the present invention employs a system of multi-threading, multi-task synchronization, addresses the shortcomings of the prior art single thread during execution of time-consuming, thereby enabling the present invention can improve system utilization, reduce system power consumption, enhanced processing power.

[0048] 第三,由于本发明的方法采用了事务层数据包(Transaction Layer Packet,TLP)的方式传输数据,解决了现有技术数据压缩方式不能超大数据容量传输的缺点,由此使得本发明数据大容量传输,降低数据传输错误率。 [0048] Third, since the method of the present invention employs a transaction layer packet (Transaction Layer Packet, TLP) the transmission of data, it addresses the shortcomings of the prior art data compression can not be large-capacity data transmission, thereby making the present invention large-capacity data transmission, reducing the data transmission error rate.

[0049] 第四,由于本发明的方法采用了双缓存技术,解决了现有技术在重绘时由于过频的刷新而引起闪烁现象,由此使得本发明上位机模块功能丰富,操作性和直观性好。 [0049] Fourth, since the method of the present invention employs a double buffer technique, the prior art solves at redrawn because too frequent refresh flicker caused, thereby making the present invention is rich in PC module function, operability, and intuitive good.

附图说明 BRIEF DESCRIPTION

[0050] 图1为本发明系统的方框图; [0050] FIG. 1 is a block diagram of the system of the present invention;

[0051] 图2为本发明方法的流程图。 [0051] FIG 2 is a flowchart of a method of the present invention.

具体实施方案 Specific embodiments

[0052] 下面结合附图对本发明做进一步的描述。 [0052] The present invention will be further described in conjunction with the accompanying drawings.

[0053] 参照附图1所示,本发明的系统包括上位机模块,PCIE接口模块,FPGA控制模块,AD采集模块和存储模块;所述上位机模块通过PCIE接口模块与FPGA控制模块连接,AD采集模块与FPGA控制模块连接,存储模块与FPGA控制模块连接。 [0053] Referring to Figure 1, the system according to the present invention includes a host computer module, the interface module PCIE, FPGA control module, the AD acquisition module and a storage module; module through the host computer interface module PCIE FPGA control module, the AD FPGA acquisition module and control module, a storage module and control module FPGA. 其中:[0054] 所述的上位机模块,由具有高速串行总线PCIE接口的上位机电脑和上位机软件组成,用于设置处理参数,对FPGA控制模块发送处理消息,对采集的数据进行存储,对数据进行处理和图形显示。 Wherein: [0054] The host computer module, the computer PC and PC software PCIE bus having a high-speed serial interface, is used for setting the processing parameters, processing the FPGA control module sends a message, storing the collected data , data processing and graphic display.

[0055] 所述的PCIE接口模块,是通过配置FPGA内嵌的PCIE端点模块核来实现。 [0055] PCIE said interface module is realized by configuring the PCIE end module embedded FPGA core. 通过PCIE端点模块核可以很方便的实现端到端传输中事务层、数据链路层和物理层功能,用于上位机模块和FPGA控制模块之间发送消息和传输数据。 Nuclear can easily implement transaction layer, data link layer and physical layer functions PCIE end by end to end transmission module for transmitting messages and data transfer between the host computer module and the FPGA control module. 本发明的实施例中,PCIE端点模块核,上位机模块与端点模块核的数据传输面向PCIE事务层,更底层的数据链路层和物理层的实现不需要有用户逻辑实现。 Embodiments of the present invention, nuclear PCIE endpoint block, the host computer module and the data block nuclear transport endpoint facing PCIE transaction layer, the lower-level implement the data link and physical layers is not required to have the user logic implemented. 用户逻辑只需要实现TLP封装,按照与PCIE端点模块核的接口规范进行通信。 Users only need to implement the logic TLP packet, according to communication with the interface specification of the core module PCIE end.

[0056] 所述的FPGA控制模块,由现场可编程门阵列FPGA组成,用于接收上位机模块发送的操作方法、处理参数,负责系统各个模块之间的控制,包括=WAD采集模块读取数据,向存储模块存取数据,发送采集数据至上位机模块。 [0056] the FPGA control module, a field programmable gate array (FPGA) composition, a method for controlling the operation between the host computer receives the transmission module, process parameters, each module is responsible for the system, including the read data acquisition module = WAD access to the data storage module, transmitting data to the upper collecting machine module. 本发明的实施例中现场可编程门阵列FPGA采用Xilinx公司的Virtex系列芯片;FPGA控制模块与上位机模块通过高速串行总线PCIE接口相连接。 In embodiments of the present invention is the field programmable gate array (FPGA) using Xilinx Virtex family of chips; FPGA control module is connected with the host computer through a high speed serial bus module PCIE interface.

[0057] 所述的AD采集模块,采用满足4路IObit精度1.25Gsps采样率的芯片,主要完成雷达数据的采集;本发明的实施例中AD采集模块选用NS公司的高速AD采样芯片。 [0057] The AD of the acquisition module, using 4 IObit meet accuracy 1.25Gsps chip rate sampling, mainly to complete the acquisition of the radar data; embodiment of the present invention, the AD acquisition module selects NS's high-speed AD sampling chip.

[0058] 所述的存储模块,由一片支持最大2GB的双倍数据率同步动态随机存储器(Double Data Rate II Synchronous Dynamic Random Access Memory,DDR2SDRAM)组成,作为现场可编程门阵列FPGA内部存储器的补充,用于暂存发送给上位机的采集数据,供FPGA控制模块调用。 [0058] The storage module by a support up to 2GB Double Data Rate Synchronous Dynamic Random Access Memory (Double Data Rate II Synchronous Dynamic Random Access Memory, DDR2SDRAM) composition, as a field programmable gate array (FPGA) internal supplementary memory, for temporarily storing data transmitted to the host computer acquisition, FPGA control module for the call.

[0059] 参照附图2对本发明的方法做进一步的描述。 [0059] Referring to Figure 2 further description of the method of the present invention.

[0060] 步骤1.设置参数。 [0060] Step 1. Set parameters.

[0061] 用户在上位机模块中,根据所需的处理方法选择采集控制、DMA传输、图形显示;用户在处理方法对应的设置窗口中,输入采集参数控制、DMA传输参数、显示控制参数;对采集进行采样时钟、触发方式、采样通道和采样点数的设置;对DMA传输进行每一个TLP包的大小、每次传输TLP包的个数进行设置。 [0061] The user PC module, the processing method of choice depending on the desired collection control, the DMA transfer, a graphic display; processing method corresponding to the user setting window, enter the control acquisition parameters, the DMA transfer parameters, the display control parameter; of acquisition sampling clock, trigger mode, and number of samples of the sampling channel disposed; of DMA transfers for each TLP packet size, the number of transmissions per packet is set TLP. 对显示控制进行显示通道和显示点数的设置。 Display control and display channel display setting points.

[0062] 步骤2.产生界面消息。 [0062] Step 2. The interface message is generated.

[0063] 由上位机模块采用步骤I中所选择的操作方法,对步骤I设置的参数进行消息响应,生成界面消息。 [0063] The method of operation by the host computer module selected in step I, the parameters set in step I a message in response, generating an interface message.

[0064] 步骤3.发送界面消息。 [0064] Step 3. Send message interface.

[0065] 上位机模块将界面消息通过高速串行总线PCIE接口发送给FPGA控制模块。 [0065] The PC interface module transmits the message interface to the FPGA control module through a high speed serial bus PCIE.

[0066] 步骤4.判断是否收到消息。 [0066] Step 4 determines whether the received message.

[0067] 上位机模块判断是否收到高速串行总线PCIE接口发送给FPGA控制模块的界面消息,若未收到界面消息,则执行步骤2,重新产生界面消息;如果收到界面消息,则执行步骤5。 [0067] The PC interface module determines whether the received message is sent to a high-speed serial bus interfaces PCIE FPGA control module, the interface message has not been received, step 2, to regenerate the message interface; if the interface receives the message, is executed step 5.

[0068] 步骤5.判断收到的界面消息是否为关闭界面消息。 If [0068] Step 5. Analyzing the received message interface message to close the screen.

[0069] 上位机模块判断收到的界面消息是否为关闭界面消息,如果收到的界面消息为关闭界面消息,则执行步骤13 ;如果收到的界面消息为采集控制、DMA传输、图形显示三种界面消息中的一种,则执行步骤6。 [0069] The PC interface module determines that the received message is a message to close the screen, if the received message is closed interface interface message, execute step 13; if the received message to acquire the control interface, the DMA transfer, a graphic display three one kind of interface of two messages, step 6 is performed. [0070] 步骤6.消息分配。 [0070] Step 6. assignment message.

[0071] FPGA控制模块根据收到的界面消息得到相应的操作方法和操作参数;FPGA控制模块向AD采集模块发送采集控制相应的操作方法和操作参数。 [0071] FPGA control module to give the corresponding operating method and operating parameters of the interface according to the received message; the FPGA control module sends a corresponding operation method acquisition control and operating parameters to the AD acquisition module.

[0072] 步骤7.采集数据。 [0072] Step 7. The data acquisition.

[0073] AD采集模块接收FPGA控制模块发送的采集控制相应的操作方法和操作参数,根据操作方法和操作参数得到开始采集指令和处理参数;当AD采集模块接收到开始采集指令后,根据其所接收到的处理参数,进行数据采集;AD采集模块采集完数据后,向FPGA控制模块发送采集结束指令。 [0073] Acquisition AD acquisition module receives FPGA control module sends a control operation method and a corresponding operating parameters, and begin acquiring instruction processing parameters and the operation method according to operating parameters obtained; when receiving the start AD acquisition module acquiring instruction, according to its processing the received parameter data acquisition; AD collection module after completion of data acquisition, acquisition end command sent to the FPGA control module.

[0074] 步骤8.DMA数据传输。 [0074] Step 8.DMA data transmission.

[0075] FPGA控制模块接收AD采集模块发送的采集结束指令;FPGA控制模块接收AD采集模块采集的数据,存入存储模块中;FPGA控制模块根据步骤5中收到的DMA传输相应的操作方法和操作参数,对系统进行复位确保本次传输的数据是当前采集到的数据。 [0075] AD FPGA control module receives the transmission instruction acquisition module collecting end; FPGA control module receives the AD data acquisition module, and stored in the memory module; FPGA control module receives the DMA transfer according to step 5 and corresponding methods of operation operating parameters, reset the system to ensure that this data is transmitted to the currently acquired data. 开始传输时判断数据传输是否结束,如果传输的数据还在进行中,则启动一次DMA传输,并把数据写到上位机的缓存区中,判断上位机的缓存区是否写满,若是写满了则等待,直到空闲了继续写;若是上位机的缓存区没写满,则进行下一次数据传输。 Determine the data transfer is completed, if the data transfer is still in progress, start a DMA transfer, and the data is written to cache the host computer, the host computer to determine whether the buffer is full at the start of transmission, if filled wait until idle for continuing to write; if the host computer's cache is not full, the next data transmission is performed. FPGA控制模块将采集数据通过高速串行总线PCIE接口,发送回上位机模块。 FPGA control module will collect data through a high speed serial bus PCIE interface, sent back to the host computer module.

[0076] 步骤9.数据上位机存储。 [0076] Step 9. The data storage PC.

[0077] 上位机模块将发送来的采集数据,按照上位机模块设置的存储路径存储到上位机硬盘中,方便进一步的数据绘图处理。 [0077] PC data acquisition module is sent, the host computer module according to the storage path provided to the host computer is stored in the hard disk, to facilitate further data drawing processing.

[0078] 步骤10.绘图。 [0078] Step 10. drawing.

[0079] 上位机模块根据步骤5中收到的图形显示相应的操作方法和操作参数,将存储到上位机硬盘的数据读取到上位机缓存中,采用双缓存技术进行绘图。 [0079] PC module displays a corresponding method of operation and operating parameters, the host computer stores the read data to the host computer hard disk cache, cache technology dual graph is plotted according to the received step 5. 在上位机内存中准备一块内存区域,将要显示的图形加载到内存中,再将内存图形复制到显示设备上。 Prepare a memory area, to be displayed in the host computer memory is loaded into the graphics memory, graphics memory and then copied to the display device. 系统要满足实时性,保证绘图过程一直进行,采用while循环,直到FPGA收到通知显示的命令后终止绘图操作。 To meet real-time systems, to ensure that the drawing process has been performed using a while loop, until after the drawing operation termination notification display command received FPGA.

[0080] 步骤11.显示绘图图像。 [0080] Step 11. The display graphics image.

[0081] 上位机模块将内存中绘制好的绘图图像拷贝至显示屏上,实现绘图图形的显示。 [0081] The host computer module memory to draw a good copy of the image drawing on the display screen, to display the drawing pattern is achieved.

[0082] 步骤12.判断是否继续显示绘图图像。 [0082] Step 12 determines whether to continue to display the drawing image.

[0083] 上位机模块判断是否继续显示绘图图像,如果不继续显示绘图图像,则执行步骤4 ;若继续显示绘图图像,则执行步骤10。 [0083] The host computer module determines whether to continue to display the drawing image, if not to continue to display the drawing image, step 4 is performed; if it continues to display the drawing image, step 10 is executed.

[0084] 步骤13.界面关闭,系统退出。 [0084] Step 13. The interface turns off, the system exits.

[0085] 上位机将绘图图像显示在屏幕上,与原信号并列显示,进行对比。 [0085] The host computer graphics image is displayed on the screen display in parallel with the original signal, for comparison.

[0086] 本发明的工作原理如下: [0086] principle of the present invention is as follows:

[0087] AD采集模块完成雷达数据的采集后,通过FPGA控制模块完成雷达数据的接收、传输后,先存入FPGA内嵌缓存区,进一步存储到系统的存储模块,当进行DMA传输时,FPGA模块中的控制逻辑模块先从存储模块中把数据读取到FPGA内嵌缓存区中,然后把FPGA内嵌缓存区的数据送至PCIE端点模块核的接口,最后,数据经PCIE总线传输至上位机硬盘。 After [0087] AD data acquisition module to complete the acquisition of the radar, radar data is completed by the FPGA control module receives, after transmission, the first buffer into embedded FPGA, further to the storage module system, when the DMA transfer, FPGA control logic block module to start to read the data storage module to the buffer area embedded FPGA, the FPGA and embedded data buffer is sent to module interfaces to the core PCIE end point, and finally, the data transmitted to the host via the PCIE bus hard drive. 进行显示绘图时,上位机模块首先从上位机硬盘中把数据读取到上位机缓存区,按照设置的显示参数采用双缓存技术把上位机缓存区数据绘制成图,显示到屏幕上。 When displaying graphics, from a first module PC host computer hard drive to the host computer the read data buffer, in accordance with the set display parameters double caching data buffer to the host computer plotted, displayed on the screen. [0088] 采用了上述的数据采集显控系统及其方法,由于在本发明中采用了FPGA可编程逻辑器件,不仅提高了本发明的可移植性和通用性,而且使得本发明便于应用和开发。 [0088] The above-described data acquisition control system and method significantly, the use of programmable logic devices in the FPGA of the present invention, not only improve the portability and versatility of the present invention, but that the present invention facilitates the application and development . 同时由于使用了高速串行总线PCIE接口,从而保证了数据传输速率。 At the same time the use of a high-speed serial bus PCIE interface, thereby ensuring the data transmission rate.

Claims (4)

1.一种基于PCIE的雷达数据采集显控系统,包括上位机模块,PCIE接口模块,FPGA控制模块,AD采集模块和存储模块;所述上位机模块通过PCIE接口模块与FPGA控制模块连接,AD采集模块与FPGA控制模块连接,存储模块与FPGA控制模块连接;其中: 所述的上位机模块,采用多线程技术,用于设置处理参数,对FPGA模块发送处理消息,对采集的数据进行存储,对数据进行处理和图形显示; 所述的PCIE接口模块,是通过配置FPGA内嵌的PCIE端点模块核来实现,用于上位机模块和FPGA模块之间发送消息和传输数据; 所述的FPGA 控制模块,用于接收上位机模块发送的处理消息,完成高速数据的接收、传输,负责系统各个模块之间的控制; 所述的AD采集模块,主要完成雷达数据的采集; 所述的存储模块,用于缓存AD采集的数据。 A radar-based data acquisition was PCIE control system, comprising a host computer module, the interface module PCIE, FPGA control module, the AD acquisition module and a storage module; module through the host computer interface module PCIE FPGA control module, the AD FPGA acquisition module and control module, a memory module with the FPGA control module; wherein: said host computer module multithreading technique, processing for setting the parameters, the FPGA processing module sends a message, storing the collected data, data processing and graphics display; the PCIE interface modules is achieved by configuring the PCIE end embedded FPGA core module, for transmitting a message and for transferring data between the host computer module and the FPGA module; said control FPGA means for receiving a transmitted message processing module PC complete control between reception, transmission, each module is responsible for high-speed data system; the AD acquisition module, mainly to complete the acquisition of the radar data; the memory module, AD acquired for data cache.
2.根据权利要求1所述的基于PCIE的雷达数据采集显控系统,其特征在于,所述的PCIE接口模块,可以配置FPGA内嵌的PCIEIP核的参数;AD采集模块采用4路IObit精度1.25Gsps 采样率的芯片EV10AQ190A。 The collection of claim 1 was based on the radar data PCIE control system, characterized in that said PCIE interface module can be configured embedded FPGA core parameters PCIEIP claim; the AD acquisition modules 4 IObit accuracy 1.25 chip EV10AQ190A Gsps sampling rate.
3.一种基于PCIE的雷达数据采集显控方法,其具体步骤如下: (1)设置参数: Ia)用户在上位机模块中,根据所需的处理方法选择采集控制、DMA传输、图形显示;Ib)用户在处理方法对应的设置窗口中,输入采集参数控制、DMA传输参数、显示控制参数; (2)产生界面消息: 由上位机模块采用在步骤(I)中所选择的操作方法,对步骤(I)设置的参数进行消息响应,生成界面消息; (3)发送界面消息: 上位机将界面消息通过高速串行总线PCIE接口发送给FPGA控制模块; (4)判断是否收到消息: 上位机模块判断是否收到高速串行总线PCIE接口发送给FPGA控制模块的界面消息,若未收到界面消息,则执行步骤(2),重新产生界面消息;如果收到界面消息,则执行步骤(5); (5)判断收到的界面消息是否为关闭界面消息: 上位机模块判断收到的界面消息是否为关闭界面消息,如果收到的界面 A display control method based on the radar data acquisition PCIE, the specific steps are as follows: (1) setting parameters: Ia) the user PC module, the processing method according to the desired selection collection control, the DMA transfer, a graphic display; ib) the user in the processing method corresponding to the setting window, input acquisition parameter control, the DMA transfer parameters, the display control parameters; (2) generates an interface message: operation in step (I) is selected employed by the host computer module, for parameter step (I) is provided in response to a message, generating an interface message; (3) send message interface: PC interface message to the FPGA control module PCIE interface high-speed serial bus; (4) determines whether the received message: the host machine interface module determines whether or not a message sent to a high-speed serial bus interfaces PCIE FPGA control module, the interface message has not been received, then step (2), regenerate the message interface; if the interface message is received, step ( 5); (5) determines whether the received message interface screen off message: PC interface module determines that the received message is a message to close the screen, if the received interface 息为关闭界面消息,则执行步骤(13);如果收到的界面消息为采集控制、DMA传输、图形显示三种界面消息中的一种,则执行步骤(6); (6)消息分配: 6a)FPGA控制模块根据收到的界面消息得到相应的操作方法和操作参数; 6b)FPGA控制模块向AD采集模块发送采集控制相应的操作方法和操作参数; (7)采集数据: 7a) AD采集模块接收FPGA控制模块发送的采集控制相应的操作方法和操作参数,根据操作方法和操作参数得到开始采集指令和处理参数; 7b)当AD采集模块接收到开始采集指令后,根据其所接收到的处理参数,进行数据采集; 7c) AD采集模块采集完数据后,向FPGA控制模块发送采集结束指令; (8) DMA数据传输: 8a) FPGA控制模块接收AD采集模块发送的采集结束指令; 8b) FPGA控制模块接收AD采集模块采集的数据,存入存储模块中; 8c) FPGA控制模块根据步骤(5)中收到的DMA传输相 Close to the interface information message, step (13); if the received message to acquire the control interface, the DMA transfer, one of three graphical display interface message, step (6); (6) assigned message: 6a) FPGA control module obtained in accordance with the interface information corresponding to the received operating parameters and operating method; 6b) FPGA control module sends a corresponding operation method acquisition control and operating parameters to the AD acquisition module; (7) data collection: 7a) AD acquisition collecting sending module FPGA control module receives a corresponding method of operation and operating parameters, and begin acquiring instruction processing parameters and the operation method according to operating parameters obtained; 7B) when the AD acquisition module receiving the start acquisition command after it is received in accordance with the processing parameters for data collection; 7C) AD collecting module after data transmission acquisition end command to the FPGA control module; (8) DMA data transfer: 8a) FPGA control module receives the acquisition AD collection module sends the instruction to end; 8B) FPGA control module receives the AD data acquisition module, and stored in the memory module; 8C) FPGA control module for DMA transfer in step (5) received in 应的操作方法和操作参数,将采集数据通过高速串行总线PCIE接口,发送回上位机模块; O)数据上位机存储: 上位机模块将发送来的采集数据存储到上位机硬盘中; (10)绘图: 上位机模块根据步骤(5)中收到的图形显示相应的操作方法和操作参数将存储到上位机硬盘的数据读取到缓存中,采用双缓存技术进行绘图; (11)显示绘图图像: 上位机模块将绘图图像显示到屏幕上; (12)判断是否继续显示绘图图像: 上位机判断是否继续显示绘图图像,如果不继续显示绘图图像,则转入执行步骤(4);若继续显示绘图图像,则执行步骤(10); (13)界面关闭。 Corresponding operating methods and parameters, data will be collected by a high speed serial bus PCIE interface, sent back to the host computer module; O) a data storage PC: PC module sends the collected data to the host computer is stored in the hard disk; (10 ) drawings: PC graphical display module in step (5) received in a corresponding operating method and operating parameters are stored to the read data to the PC hard disk cache, cache technology dual plotted; (11) to display the drawing image: PC module drawing image displayed on the screen; if (12) is determined to continue to display the drawing image: determining whether the PC continues to display the drawing image, if not to continue to display the drawing image, the process proceeds to step (4); if continue displaying a drawing image, step (10); (13) off the interface.
4.根据权利要求3所述的基于PCIE的雷达数据采集显控方法,其特征在于,步骤(10)所述的双缓存技术就是指,在上位机内存中准备一块内存区域,将要显示的图形加载到内存中,再将内存图形复制到显示设备上。 4. The display and control based on radar data acquisition PCIE according to claim 3, wherein the step (10) of the double buffer technique refers to prepare a memory area in the memory of the host computer, the graphic to be displayed loaded into memory, and then copy the graphic memory to a display device.
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