CN103294836A - PCIE (peripheral component interconnect express) based radar data acquisition displaying and controlling system and method thereof - Google Patents
PCIE (peripheral component interconnect express) based radar data acquisition displaying and controlling system and method thereof Download PDFInfo
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Abstract
The invention discloses a PCIE (peripheral component interconnect express) based radar data acquisition displaying and controlling system and a method thereof. The PCIE based radar data acquisition displaying and controlling system comprises an upper computer module, a PCIE interface module, an FPGA (field programmable gate array) control module, an AD acquisition module and a storage module. The upper computer module is used for setting and processing parameters, sending and processing information and displaying images. The PCIE interface module is used for sending information and transmitting data between the upper computer module and the FPGA control module. The FPGA control module completes receiving and transmitting of the data and is responsible for controlling the modules. The AD acquisition module completes data acquisition. The storage module is used for storing the data. The method includes that the acquired data are transmitted to the upper computer module by means of a TLP (thread-level parallelism) data package and then drawn into an image to be displayed on a screen by means of a double buffer technique by the upper computer module according to set displaying parameters. The PCIE based radar data acquisition displaying and controlling system and the method thereof reduce system cost, increase data transmission rate and can be applied to a radar data acquisition system, particularly a system high in data transmission rate and strong in instantaneity.
Description
Technical field
The invention belongs to communication technical field, (Peripheral Component Interconnect Express, radar data acquisition PCIE) show control system and method thereof based on peripheral component interconnect high speed expansion bus further to relate to a kind of in the digital signal processing technique field.The present invention can be used in the radar data collection system, and message transmission rate height particularly is in the real-time system.The present invention utilizes field programmable gate array (Field Programmable Gate Array, FPGA) radar data acquisition based on PCIE of embedded PCIE endpoint module nuclear (Endpoint Block Plus for PCI Express) composition shows control system and method thereof, can realize the data of radar collection are carried out high speed processing.
Background technology
The fast development of Radar Technology constantly proposes higher requirement to radar data collection system.The characteristics that its data volume is big, real-time require data acquisition system (DAS) to have high acquisition rate and high data throughput capabilities.But the data acquisition that is used for PC at present shows control system great majority and is based on pci bus, and its disadvantage is exactly that message transmission rate is low, real-time is not strong.Simultaneously, data acquisition system (DAS) in the past software, driving and hardware aspect in various degree have some problems such as data acquisition rate, message transmission rate be low, can't effectively promote aspect practicality and the reliability.And radar data collection system has produced very big influence for the payment of final system because the user shows the not hommization of control software in the process that offers user's use.
The patented claim " radar data collection system and acquisition method thereof " (number of patent application 200710037078.0, publication number CN101178434A) that Shanghai Yiluo Information Science and Technology Co., Ltd. proposes discloses radar data collection system and acquisition method thereof.This system comprises gathers control functional device and host data record interface device, wherein system also comprises memory function module, host data record interface device is the pci bus control device, the pci bus control device is connected with the data recording main frame by pci bus, gathers the control functional device and links to each other with memory function module, pci bus control device respectively.Method comprises that the radar data signal that will gather carries out sample quantization and handles, will data after treatment reaches in the memory function module, data are taken out and is sent to the data recording main frame by the pci bus control device from memory function module.But the deficiency that this system and method exists is, the first, because the message transmission rate of pci bus is up to 132MB/S in theory, can not satisfy the data high-speed transmission, and increase system overhead.The second, data are transmitted with compress mode, can not satisfy big data transmission, and efficient is lower, and the data transmission fault rate is higher.The 3rd, the host subscriber records and realizes adopting single task single-threaded, the power consumption height of system, and system availability is low, and processing power is relatively poor.The 4th, because main frame has only user record, functions of modules is single, and operability and intuitive are poor.
And the PCIE bus possesses characteristics such as two-forty, high reliability, low cost and extendability are strong.Current all need be undertaken in the mutual hardware system by Computer I/O bus, the PCIE bus becomes radar data acquisition gradually and shows the first-selection that the control system realizes high-speed transfer.
Summary of the invention
The objective of the invention is to the deficiency at above-mentioned prior art, propose a kind of radar data acquisition based on PCIE and show control system and method thereof, to satisfy the requirement of big data quantity, high-speed transfer, satisfy the user and implement control bottom integrated circuit board by upper layer software (applications), reach the excellent function effect, the user of hommization experiences, and reduces the power consumption of system simultaneously.
For achieving the above object, the present invention includes:
A kind of radar data acquisition based on PCIE shows the control system, comprises upper computer module, PCIE interface module, FPGA control module, AD acquisition module and memory module; Described upper computer module is connected with the FPGA control module by the PCIE interface module, and the AD acquisition module is connected with the FPGA control module, and memory module is connected with the FPGA control module.Wherein:
Described upper computer module adopts multithreading, is used for the set handling parameter, and the FPGA module is sent processing messages, and the data of gathering are stored, and data is handled with figure show.
Described PCIE interface module is to examine to realize by the embedded PCIE endpoint module of configuration FPGA, is used for sending between upper computer module and the FPGA module message and transmission data.
Described FPGA control module is used for receiving the processing messages that upper computer module sends, and finishes reception, the transmission of high-speed data, is responsible for the control between each module of system.
Described AD acquisition module is mainly finished the collection of radar data.
Described memory module is used for the data that buffer memory AD gathers.
The concrete steps of the inventive method are as follows:
(1) parameter is set:
1a) user selects to gather control, DMA (Direct Memory Access) transmission, figure demonstration according to required disposal route in upper computer module;
1b) user is the arranging in the window of disposal route correspondence, the control of input acquisition parameter, DMA transmission parameter, shows the control parameter.
(2) produce interface message:
Adopt selected method of operating in step (1) by upper computer module, the parameter that step (1) arranges is carried out message response, generate interface message.
(3) send interface message:
Host computer sends to the FPGA control module with interface message by high-speed serial bus PCIE interface.
(4) judge whether to receive message:
Upper computer module judges whether to receive that high-speed serial bus PCIE interface sends to the interface message of FPGA control module, if do not receive interface message, then execution in step (2) produces interface message again; If receive interface message, execution in step (5) then.
(5) judge that whether the interface message receive is for closing interface message:
Upper computer module is judged the interface message receive whether for closing interface message, if the interface message of receiving for closing interface message, execution in step (13) then; If the interface message of receiving shows a kind of in three kinds of interface message, then execution in step (6) for gathering control, DMA transmission, figure.
(6) distribution of messages:
6a) the FPGA control module obtains corresponding method of operating and operating parameter according to the interface message of receiving;
6b) the FPGA control module sends to the AD acquisition module and gathers the corresponding method of operating of control and operating parameter.
(7) image data:
7a) corresponding method of operating and operating parameter are controlled in the collection of AD acquisition module reception FPGA control module transmission, obtain start command of acquisition and processing parameter according to method of operating and operating parameter;
7b) after the AD acquisition module receives start command of acquisition, according to its received processing parameter, carry out data acquisition;
7c) after the intact data of AD acquisition module collection, send the collection END instruction to the FPGA control module.
(8) DMA data transmission:
8a) the FPGA control module receives the collection END instruction that the AD acquisition module sends;
8b) the FPGA control module receives the data that the AD acquisition module is gathered, and deposits in the memory module;
8c) the FPGA control module is transmitted corresponding method of operating and operating parameter according to the DMA that receives in the step (5), and image data by high-speed serial bus PCIE interface, is sent it back upper computer module.
(9) data host computer storage:
Upper computer module with the acquired data storage of sending in the host computer hard disk.
(10) draw:
Upper computer module shows that according to the figure of receiving in the step (5) data read that corresponding method of operating and operating parameter will store the host computer hard disk in buffer memory, adopts two caching technologys to draw.
(11) show the drawing image:
Upper computer module is shown to the drawing image on the screen.
(12) judge whether to continue to show the drawing image:
Upper computer module judges whether to continue to show the drawing image, if do not continue to show the drawing image, then changes execution in step (4) over to; If continue to show drawing image, then execution in step (10).
(13) interface is closed.
The present invention compared with prior art has following advantage:
The first, because system of the present invention adopts the embedded PCIE endpoint module of FPGA to examine existing PCIE interface, solved the lower shortcoming of transfer rate that prior art adopts pci bus to cause, make the speed of data transmission of the present invention be greatly enhanced thus.
The second, because system of the present invention has adopted multithreading, the realization multitask is carried out synchronously, solved the single-threaded shortcoming consuming time in the process of implementation of prior art, make the present invention can improve system availability thus, reduce system power dissipation, strengthen processing power.
The 3rd, because method of the present invention has adopted affairs layer data bag (Transaction Layer Packet, TLP) mode is transmitted data, solved the shortcoming that prior art data compression mode can not the transmission of super large data capacity, make thus and the big volume transport of data of the present invention reduce the data transmission fault rate.
The 4th because method of the present invention adopted two caching technologys, solved prior art when redrawing owing to refreshing of overfrequency causes scintillation, make upper computer module feature richness of the present invention thus, operability and intuitive are good.
Description of drawings
Fig. 1 is the block scheme of system of the present invention;
Fig. 2 is the process flow diagram of the inventive method.
Specific embodiments
The present invention will be further described below in conjunction with accompanying drawing.
Shown in accompanying drawing 1, system of the present invention comprises upper computer module, PCIE interface module, FPGA control module, AD acquisition module and memory module; Described upper computer module is connected with the FPGA control module by the PCIE interface module, and the AD acquisition module is connected with the FPGA control module, and memory module is connected with the FPGA control module.Wherein:
Described upper computer module, formed by host computer computer and upper computer software with high-speed serial bus PCIE interface, be used for the set handling parameter, the FPGA control module is sent processing messages, data to collection are stored, and data are handled with figure show.
Described PCIE interface module is to examine to realize by the embedded PCIE endpoint module of configuration FPGA.Endorse to realize very easily transaction layer, data link layer and physical layer function in the end-to-end transmission by the PCIE endpoint module, be used for sending between upper computer module and the FPGA control module message and transmission data.In the embodiments of the invention, PCIE endpoint module nuclear, the data transmission of upper computer module and endpoint module nuclear is towards the PCIE transaction layer, and more the realization of the data link layer of bottom and Physical layer realizes without the need for user logic.User logic only need be realized the TLP encapsulation, communicates according to the interface specification with PCIE endpoint module nuclear.
Described FPGA control module, formed by on-site programmable gate array FPGA, be used for receiving method of operating, the processing parameter that upper computer module sends, control between each module of the system of being responsible for, comprise: read data from the AD acquisition module, to the memory module access data, send image data to upper computer module.On-site programmable gate array FPGA adopts the Virtex family chip of Xilinx company in the embodiments of the invention; The FPGA control module is connected by high-speed serial bus PCIE interface with upper computer module.
Described AD acquisition module adopts the chip that satisfies 4 road 10bit precision 1.25Gsps sampling rates, mainly finishes the collection of radar data; The AD acquisition module is selected the high-speed AD sampling A of NS company for use in the embodiments of the invention.
Described memory module, supported double data rate synchronous DRAM (the Double Data Rate II Synchronous Dynamic Random Access Memory of maximum 2GB by a slice, DDR2SDRAM) form, as replenishing of on-site programmable gate array FPGA internal storage, be used for the temporary image data that sends to host computer, call for the FPGA control module.
Be further described with reference to 2 pairs of methods of the present invention of accompanying drawing.
Step 1. arranges parameter.
The user selects to gather control, DMA transmission, figure demonstration according to required disposal route in upper computer module; The user arranges in the window the disposal route correspondence, the control of input acquisition parameter, DMA transmission parameter, demonstration control parameter; Collection is carried out the setting of sampling clock, triggering mode, sampling channel and sampling number; To DMA transmission carry out the size of each TLP bag, the number of at every turn transmitting the TLP bag arranges.Carry out display channel and show the setting of counting showing control.
Step 2. produces interface message.
Adopt selected method of operating in the step 1 by upper computer module, the parameter that step 1 arranges is carried out message response, generate interface message.
Step 3. sends interface message.
Upper computer module sends to the FPGA control module with interface message by high-speed serial bus PCIE interface.
Step 4. judges whether to receive message.
Upper computer module judges whether to receive that high-speed serial bus PCIE interface sends to the interface message of FPGA control module, if do not receive interface message, then execution in step 2, produce interface message again; If receive interface message, then execution in step 5.
Step 5. judges that whether the interface message of receiving is for closing interface message.
Upper computer module is judged the interface message receive whether for closing interface message, if the interface message of receiving for closing interface message, then execution in step 13; If the interface message of receiving shows a kind of in three kinds of interface message for gathering control, DMA transmission, figure, then execution in step 6.
Step 6. distribution of messages.
The FPGA control module obtains corresponding method of operating and operating parameter according to the interface message of receiving; The FPGA control module sends to the AD acquisition module and gathers the corresponding method of operating of control and operating parameter.
Step 7. image data.
The AD acquisition module receives the collection of FPGA control module transmission and controls corresponding method of operating and operating parameter, obtains start command of acquisition and processing parameter according to method of operating and operating parameter; After the AD acquisition module receives start command of acquisition, according to its received processing parameter, carry out data acquisition; After the intact data of AD acquisition module collection, send the collection END instruction to the FPGA control module.
Step 8.DMA data transmission.
The FPGA control module receives the collection END instruction that the AD acquisition module sends; The FPGA control module receives the data that the AD acquisition module is gathered, and deposits in the memory module; The FPGA control module is transmitted corresponding method of operating and operating parameter according to the DMA that receives in the step 5, is current data that collect to system's data of guaranteeing this transmission that reset.Whether the judgment data transmission finishes when beginning to transmit, if the data of transmission are also underway, then starts a DMA transmission, and data are write in the buffer area of host computer, whether the buffer area of judging host computer is write full, wait for if write to have expired then, up to the free time continue to write; If the buffer area of host computer is not write full, then carry out data transmission next time.The FPGA control module by high-speed serial bus PCIE interface, sends it back upper computer module with image data.
The storage of step 9. data host computer.
Upper computer module is the image data of sending, and stores in the host computer hard disk according to the store path of upper computer module setting, and convenient further data are drawn and handled.
Step 10. is drawn.
Upper computer module shows corresponding method of operating and operating parameter according to the figure of receiving in the step 5, in the host computer buffer memory, adopts two caching technologys to draw the data read that stores the host computer hard disk into.Prepare a region of memory in the host computer internal memory, the figure that will show is loaded in the internal memory, the internal memory figure is copied on the display device again.System will satisfy real-time, guarantees that drawing course carries out always, adopts the while circulation, stops mapping operation after the order of the notified demonstration of FPGA.
Step 11. shows the drawing image.
Upper computer module realizes the demonstration of graphics with drawing good drawing image copy in the internal memory to display screen.
Step 12. judges whether to continue to show the drawing image.
Upper computer module judges whether to continue to show the drawing image that if do not continue to show the drawing image, then execution in step 4; If continue to show the drawing image, then execution in step 10.
Step 13. interface is closed, and system withdraws from.
Host computer is presented at the drawing image on the screen, shows side by side with original signal, compares.
Principle of work of the present invention is as follows:
After the AD acquisition module is finished the collection of radar data, by the FPGA control module finish radar data reception, the transmission after, deposit the embedded buffer area of FPGA earlier in, further store the memory module of system into, when carrying out DMA when transmission, the steering logic module in the FPGA module earlier from memory module data read in the embedded buffer area of FPGA, then the data of the embedded buffer area of FPGA are delivered to the interface of PCIE endpoint module nuclear, at last, data through the PCIE bus transfer to the host computer hard disk.Show when drawing, upper computer module at first from the host computer hard disk data read to the host computer buffer area, adopt two caching technologys host computer buffer area data drafting pattern according to the display parameter that arrange, be shown on the screen.
Adopt above-mentioned data acquisition to show control system and method thereof, owing to adopted the FPGA programmable logic device (PLD) in the present invention, not only improved portability of the present invention and versatility, and made the present invention be convenient to use and exploitation.Simultaneously owing to used high-speed serial bus PCIE interface, thereby guaranteed message transmission rate.
Claims (4)
1. the radar data acquisition based on PCIE shows the control system, comprises upper computer module, PCIE interface module, FPGA control module, AD acquisition module and memory module; Described upper computer module is connected with the FPGA control module by the PCIE interface module, and the AD acquisition module is connected with the FPGA control module, and memory module is connected with the FPGA control module; Wherein:
Described upper computer module adopts multithreading, is used for the set handling parameter, and the FPGA module is sent processing messages, and the data of gathering are stored, and data is handled with figure show;
Described PCIE interface module is to examine to realize by the embedded PCIE endpoint module of configuration FPGA, is used for sending between upper computer module and the FPGA module message and transmission data;
Described FPGA control module is used for receiving the processing messages that upper computer module sends, and finishes reception, the transmission of high-speed data, is responsible for the control between each module of system;
Described AD acquisition module is mainly finished the collection of radar data;
Described memory module is used for the data that buffer memory AD gathers.
2. the radar data acquisition based on PCIE according to claim 1 shows the control system, it is characterized in that described PCIE interface module can dispose the parameter that the embedded PCIEIP of FPGA examines; The AD acquisition module adopts the chip EV10AQ190A of 4 road 10bit precision 1.25Gsps sampling rates.
3. the radar data acquisition based on PCIE shows control method, and its concrete steps are as follows:
(1) parameter is set:
1a) user selects to gather control, DMA transmission, figure demonstration according to required disposal route in upper computer module;
1b) user is the arranging in the window of disposal route correspondence, the control of input acquisition parameter, DMA transmission parameter, shows the control parameter;
(2) produce interface message:
Adopt selected method of operating in step (1) by upper computer module, the parameter that step (1) arranges is carried out message response, generate interface message;
(3) send interface message:
Host computer sends to the FPGA control module with interface message by high-speed serial bus PCIE interface;
(4) judge whether to receive message:
Upper computer module judges whether to receive that high-speed serial bus PCIE interface sends to the interface message of FPGA control module, if do not receive interface message, then execution in step (2) produces interface message again; If receive interface message, execution in step (5) then;
(5) judge that whether the interface message receive is for closing interface message:
Upper computer module is judged the interface message receive whether for closing interface message, if the interface message of receiving for closing interface message, execution in step (13) then; If the interface message of receiving shows a kind of in three kinds of interface message, then execution in step (6) for gathering control, DMA transmission, figure;
(6) distribution of messages:
6a) the FPGA control module obtains corresponding method of operating and operating parameter according to the interface message of receiving;
6b) the FPGA control module sends to the AD acquisition module and gathers the corresponding method of operating of control and operating parameter;
(7) image data:
7a) corresponding method of operating and operating parameter are controlled in the collection of AD acquisition module reception FPGA control module transmission, obtain start command of acquisition and processing parameter according to method of operating and operating parameter;
7b) after the AD acquisition module receives start command of acquisition, according to its received processing parameter, carry out data acquisition;
7c) after the intact data of AD acquisition module collection, send the collection END instruction to the FPGA control module;
(8) DMA data transmission:
8a) the FPGA control module receives the collection END instruction that the AD acquisition module sends;
8b) the FPGA control module receives the data that the AD acquisition module is gathered, and deposits in the memory module;
8c) the FPGA control module is transmitted corresponding method of operating and operating parameter according to the DMA that receives in the step (5), and image data by high-speed serial bus PCIE interface, is sent it back upper computer module;
(9) data host computer storage:
Upper computer module with the acquired data storage of sending in the host computer hard disk;
(10) draw:
Upper computer module shows that according to the figure of receiving in the step (5) data read that corresponding method of operating and operating parameter will store the host computer hard disk in buffer memory, adopts two caching technologys to draw;
(11) show the drawing image:
Upper computer module is shown to the drawing image on the screen;
(12) judge whether to continue to show the drawing image:
Host computer judges whether to continue to show the drawing image, if do not continue to show the drawing image, then changes execution in step (4) over to; If continue to show drawing image, then execution in step (10);
(13) interface is closed.
4. the radar data acquisition based on PCIE according to claim 3 shows control method, it is characterized in that, described pair of caching technology of step (10) just refers to, in the host computer internal memory, prepare a region of memory, the figure that will show is loaded in the internal memory, the internal memory figure is copied on the display device again.
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107390179A (en) * | 2017-07-17 | 2017-11-24 | 南京理工大学 | A kind of software implementation Radar Display and Control Terminal based on all-purpose computer |
| CN107908588A (en) * | 2017-10-28 | 2018-04-13 | 天津大学 | A kind of ultrasound endoscope image acquisition interface system based on PCIE synchronous transfers |
| CN109613491A (en) * | 2018-12-24 | 2019-04-12 | 上海威固信息技术股份有限公司 | A kind of high-speed signal acquisition storage and playback system based on FPGA |
| CN109856599A (en) * | 2018-12-24 | 2019-06-07 | 南京理工大学 | A kind of array radar signal processing system and method based on DSP and server |
| CN109975680A (en) * | 2019-02-14 | 2019-07-05 | 杭州长川科技股份有限公司 | The source VI measurement data acquisition display methods |
| CN110373998A (en) * | 2019-06-05 | 2019-10-25 | 长江勘测规划设计研究有限责任公司 | Support device and application method for the forming of Spatial cable systems main rope of suspension bridge |
| CN112419138A (en) * | 2020-11-18 | 2021-02-26 | 济南浪潮高新科技投资发展有限公司 | Point cloud data processing acceleration system and method |
| CN114185005A (en) * | 2022-02-14 | 2022-03-15 | 西安电子科技大学 | Integrated radar data acquisition and processing device based on server architecture |
| CN114780471A (en) * | 2022-04-20 | 2022-07-22 | 湖南艾科诺维科技有限公司 | Data acquisition and storage system and method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101178434A (en) * | 2007-02-02 | 2008-05-14 | 上海易罗信息科技有限公司 | Radar data collection system and collection method thereof |
| US20090093980A1 (en) * | 2007-10-05 | 2009-04-09 | Cardiospectra, Inc. | Real time sd-oct with distributed acquisition and processing |
-
2013
- 2013-05-13 CN CN2013101921733A patent/CN103294836A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101178434A (en) * | 2007-02-02 | 2008-05-14 | 上海易罗信息科技有限公司 | Radar data collection system and collection method thereof |
| US20090093980A1 (en) * | 2007-10-05 | 2009-04-09 | Cardiospectra, Inc. | Real time sd-oct with distributed acquisition and processing |
Non-Patent Citations (3)
| Title |
|---|
| 代少升等: "红外图像实时显示技术研究", 《半导体光电》 * |
| 杨会玲等: "基于PCIExpress总线的高帧频CMOS相机图像采集系统设计", 《测控技术与仪器仪表》 * |
| 王伟等: "基于PCIe总线的超高速信号采集卡的设计", 《电子设计工程》 * |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107390179A (en) * | 2017-07-17 | 2017-11-24 | 南京理工大学 | A kind of software implementation Radar Display and Control Terminal based on all-purpose computer |
| CN107908588A (en) * | 2017-10-28 | 2018-04-13 | 天津大学 | A kind of ultrasound endoscope image acquisition interface system based on PCIE synchronous transfers |
| CN109613491A (en) * | 2018-12-24 | 2019-04-12 | 上海威固信息技术股份有限公司 | A kind of high-speed signal acquisition storage and playback system based on FPGA |
| CN109856599A (en) * | 2018-12-24 | 2019-06-07 | 南京理工大学 | A kind of array radar signal processing system and method based on DSP and server |
| CN109613491B (en) * | 2018-12-24 | 2024-02-09 | 上海威固信息技术股份有限公司 | High-speed signal acquisition, storage and playback system based on FPGA |
| CN109975680A (en) * | 2019-02-14 | 2019-07-05 | 杭州长川科技股份有限公司 | The source VI measurement data acquisition display methods |
| CN110373998A (en) * | 2019-06-05 | 2019-10-25 | 长江勘测规划设计研究有限责任公司 | Support device and application method for the forming of Spatial cable systems main rope of suspension bridge |
| CN110373998B (en) * | 2019-06-05 | 2024-04-12 | 长江勘测规划设计研究有限责任公司 | Supporting device for forming main cable of suspension bridge of space cable system and using method |
| CN112419138A (en) * | 2020-11-18 | 2021-02-26 | 济南浪潮高新科技投资发展有限公司 | Point cloud data processing acceleration system and method |
| CN114185005A (en) * | 2022-02-14 | 2022-03-15 | 西安电子科技大学 | Integrated radar data acquisition and processing device based on server architecture |
| CN114780471A (en) * | 2022-04-20 | 2022-07-22 | 湖南艾科诺维科技有限公司 | Data acquisition and storage system and method |
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Application publication date: 20130911 |