CN201378851Y - CCD image data collecting device - Google Patents
CCD image data collecting device Download PDFInfo
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- CN201378851Y CN201378851Y CN200820161204U CN200820161204U CN201378851Y CN 201378851 Y CN201378851 Y CN 201378851Y CN 200820161204 U CN200820161204 U CN 200820161204U CN 200820161204 U CN200820161204 U CN 200820161204U CN 201378851 Y CN201378851 Y CN 201378851Y
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Abstract
The utility model relates to a CCD image data collecting device, which comprises a CCD camera, a Camera Link interface transforming chip, a FPGA, an SDRAM cashe chip and a PCI interface chip, wherein the data of the CCD camera is collected through the Camera Link interface, and the Camera Link interface transforming chip transforms the collected data of the CCD camera to be inputted into the FPGA; three module units, i.e. a FIFO buffering unit, an SDRAM controller unit and a PCI interface module are arranged inside the FPGA. The SDRAM controller unit is used for controlling the read-write of the SDRAM chip and realizes the cashe of the CCD image data of an entire frame; the PCI interface module unit is connected with the PCI interface chip and is used for conveying the data which is outputted by the SDRAM cashe to a computer so as to realize the collection of the CCD image data. The CCD image data collecting device has the advantages of good real-time and is applicable to different CCD cameras with different resolution factors.
Description
Technical field
The utility model relates to the real time image collection field, especially a kind of ccd image data acquisition unit.
Background technology
At the real-time acquisition process occasion of CCD, designed a ccd image data acquisition unit.At present, common coffret has USB interface, 1394 interfaces and LVDS (Low Voltage DifferentialSignaling) interface.Wherein the LVDS interface is again with its low-power consumption, and the advantage of low noise and long transmission distance is that various real time data processing occasions are commonly used.But in the occasion of Large Volume Data high-speed transfer, the transmission speed of above-mentioned interface can't requirement of real time.
The utility model content
In order to solve the unmatched problem of CCD camera transmission rate of the high frame frequency of high-resolution, the utility model proposes a kind of ccd image data acquisition unit.This device can be realized high-resolution, the real-time collection transmission of the CCD camera of high frame frequency, and it is fast to have transmission rate, the advantage that real-time is good.
Ccd image data acquisition unit of the present utility model, this device comprises the CCD camera, Camera Link interface conversion chip, FPGA, SDRAM cache chip and pci interface chip.Wherein, the CCD camera is gathered the CCD camera data by Camera Link interface, and Camera Link interface conversion chip realizes that the CCD camera data that will gather carries out inputing to FPGA after the interface conversion.To inputing to the ccd data of FPGA, mainly realize three modular units in FPGA inside: FIFO buffer cell, sdram controller unit and pci interface modular unit.The FIFO buffer cell is realized the buffering to original ccd image, solves CCD camera output speed and the unmatched problem of FPGA input rate; The sdram controller unit links to each other with the SDRAM cache chip, realizes the buffer memory to whole frame ccd image data; The pci interface modular unit links to each other with pci interface chip, realizes the dateout from the SDRAM buffer memory is passed through pci bus, is transferred on the PC fast.
This device links to each other with high speed Camera Link interface by the CCD camera, realizes the high-speed transfer of CCD camera data.After decoding by Camera Link decoding chip, transfer to FPGA from the data of Camera Link interface output.Because the input rate of decoded CCD camera speed and FPGA is inequality, therefore, realize buffering to the CCD camera data of reading at first by FIFO (first in first out) unit of FPGA inside.Then, the CCD camera data after the FIFO buffering inputs to the buffer memory that SDRAM puts in order the Frame view data.Because SDRAM is the State Control machine of a complexity, therefore the structure sdram controller is realized the read-write of SDRAM is controlled in FPGA.Here, sdram controller links to each other with the SDRAM chip.At last, the dateout behind the SDRAM buffer memory is inputed to the pci interface modular unit of constructing in the FPGA, this unit by and being connected of pci interface chip, the final realization passed through pci bus to the dateout from the SDRAM buffer memory, is transferred on the PC fast.
The utility model has been realized the real-time collection transmission for the CCD camera data of the high frame frequency of high-resolution, has the good advantage of real-time and all suitable to different resolution CCD camera.
Description of drawings
The utility model will illustrate by example and with reference to the mode of accompanying drawing, wherein:
Fig. 1 is a principle schematic of the present utility model.
Fig. 2 is the read/write state transition diagram of SDRAM.
Embodiment
Fig. 1 is a principle schematic of the present utility model, and this device comprises CCD camera, Camera Link interface conversion chip, FPGA, SDRAM cache chip and pci interface chip.Wherein, the CCD camera is gathered the CCD camera data by the CameraLink interface, and Camera Link interface conversion chip realizes that the CCD camera data that will gather carries out inputing to FPGA after the interface conversion.Inner main three modular units of realizing of FPGA: FIFO buffer cell, sdram controller unit and pci interface modular unit.The FIFO buffer cell is realized the buffering to original ccd image, solves CCD camera output speed and the unmatched problem of FPGA input rate; The sdram controller unit links to each other with the SDRAM cache chip, is used to control the read-write of SDRAM, realizes the buffer memory to whole frame ccd image data; The pci interface modular unit links to each other with pci interface chip, passes through pci bus from the dateout of SDRAM buffer memory, is transferred on the PC fast.
The CCD camera links to each other with high speed Camera Link interface, realizes the high-speed transfer of CCD camera data.After decoding by Camera Link decoding chip DS90CR288A, transfer to FPGA from the data of Camera Link interface output.Because the input rate of decoded CCD camera data speed and FPGA is inequality, therefore, realize buffering to the CCD camera data of reading at first by FIFO (first in first out) unit of FPGA inside.Then, the CCD camera data after the FIFO buffering inputs to the buffer memory that SDRAM puts in order frame image data.Because SDRAM is the State Control machine of a complexity, therefore the structure sdram controller is realized the read-write of SDRAM is controlled in FPGA.Here, sdram controller links to each other with the SDRAM chip.At last, dateout behind the SDRAM buffer memory is inputed to the pci interface modular unit of constructing in the FPGA, this pci interface modular unit by and being connected of pci interface chip PCI9054, the final realization passed through pci bus from the dateout of SDRAM buffer memory, is transferred on the PC fast.
Function and designing requirement according to device have proposed the hardware platform based on programmable logic device (FPGA).Because it is very high that this device real-time requires, and simultaneously, need carry out handle up (up to the 80MHz) of mass data, for existing processor, it is very difficult carrying out the data of big throughput like this and handling in real time.Therefore, select the special processing unit of FPGA structure in the device for use, can utilize the abundant I/O pin of device to finish data throughput on the one hand, can utilize it to improve real-time on the other hand; Simultaneously, utilize the superiority of FPGA aspect complex logic control, structure sdram controller and pci interface module realize the complex logic sequencing control to SDRAM chip and pci interface chip in FPGA.
At first, the exchanges data between CCD camera and Camera Link interface.Current, most digital video solutions are counted as the LVDS communication technology.Though LVDS has had improvement than RS-422, it still needs jumbo cable, and is also restricted aspect transmission rate.In order to address this problem, National Semiconductor company based on Channel Link technical development Camera Link standard.Channel Link is based on the LVDS technical development and comes, and it is a kind of new technology that is used for transmitting video data.Channel Link uses one and change string driver and a string changes and receiver transmission data, and its flank speed can reach 2.38G.Channel Link driver is four LVDS data flow with 28 CMOS/TTL conversion of signals.A phase-locked loop passes steals clock by the 5th LVDS link and other LVDS data flow parallel transmission.In each cycle of transfer clock, 28 input data are sampled and transmit.28 CMOS/TTL parallel data changed back data flow by Channel Link receiver.
In Camera Link standard, camera signal is divided into 4 kinds:
1. high speed camera control signal: the 4 pairs of LVDS differential signals are as the camera control signal of routine.They are respectively external synchronization signal (EXSYNC), reset signal (PRIN), go-ahead signal (FORWARD) and stick signal (Future Use).
2. video data: the 4 pairs of LVDS data-signals (X0, X1, X2, X3) and pair of L VDS clock signal (XCLK)
3. power supply: the cable by special use transmits.
4. low-speed serial communication: two pairs of LVDS signals are as asynchronous communication signal between camera and the integrated circuit board.Serial-To-Frame-Grabbers (SerTFG) is the signal of communication of being received by the clamping of camera output board; Serial-To-Camera (SerTC) then is the signal of communication that is received by integrated circuit board output camera.Communication protocol is observed asynchronous communications protocol RS232 agreement just.Minimum 9600bps is used in Camera Link standard recommendation, 1 start bit, and 8 bit data positions, 1 position of rest does not have the form of the no parity check of shaking hands.
As seen, the CCD digital camera is by the connection of Camera Link interface, and the data line transitions that realizes the multidigit high-speed parallel is serial data line output.Simultaneously, the dash receiver cartoon is crossed receiving chip DS90CR288A and is realized the serial data of CCD camera output is reduced to original parallel data output, and corresponding C CD camera communication signal and effective control signal are provided simultaneously.
Then, the CCD camera data to DS90CR288A decoding output inputs to FPGA.In FPGA inside mainly by following three processing units: FIFO buffer cell, sdram controller unit and pci interface modular unit.
The FIFO buffer cell is mainly realized the CCD camera data speed of exporting from the DS90CR288A decoding and the coupling of FPGA speed.
The buffer memory to original image is realized by at FPGA internal structure sdram controller in the sdram controller unit.Here, the sdram controller unit links to each other with the SDRAM memory chip.The SDRAM memory has been chosen the HY57V281620HCT that HYNIX company produces, and the internal structure of its sync cap and complete streamline makes it have great data rate, is fit to very much the storage of big throughput.
Sdram controller adopts state machine to realize.This state machine comprises following state: init state, idle condition, read-write state, precharging state, Flushing status, state of activation.Behind system power-on reset, at first finish the initialization of SDRAM.Initialization comprises the initialization time-delay, and initialization precharge, initialization refresh and the setting of initialize mode register.Consider efficiency, the mode register working method is the full page burst, and fixation of C AS (read command is input to data output time-delay) is 2 clock cycle.After initialization finished, SDRAM entered idle condition.When idle condition, as sending read-write requests to SDRAM, sdram controller enters the line activating state, laggardly goes into the read/write state and just can read and write SDRAM through two clock cycle.
After SDRAM entered the write data state, owing to adopt full page burst working method, then a write operation can have been write data line.It is noted that at last once write operation and finish before next write operation, current line must be closed and carry out the preliminary filling order.Behind the precharging state, after two clock cycle, could activate next line again and carry out write operation next time.Because all there is the periodic refreshing problem in dynamic memory, behind the data write storage unit, want data and do not lose, need in given interval, to refresh, promptly enter Flushing status.As seen, under the control of SDRAM high-frequency clock speed,, can finish image data transmission at line blanking period fully to delegation for the video image of gathering by full page burst write operations mode.When receiving the next line view data, repeat aforesaid operations, all write SDRAM until the entire image data.
After SDRAM entered the read data state, after the time, the SDRAM data terminal can sense data through CAS (read command is input to data output time-delay) for palpus.Because the full page burst mode is all adopted in the SDRAM read/write operation, therefore after SDRAM runs through data line, then finished single reading according to operation.Carry out the preliminary filling order current line is closed this moment.Behind precharging state, need again after two clock cycle, could activate next line again.Because SDRAM adopts the capacitance stores data message, and is the same with write operation, need carry out periodic refreshing to data equally.After refresh operation finishes, just can send out read command once more, all read until frame data.The state transition diagram of whole SDRAM is seen Fig. 2.
At last, the dateout behind the SDRAM buffer memory is inputed to the pci interface modular unit.The implication of PCI is peripheral component interconnect (Peripheral Component Interconnect).The PCI local bus is a kind of high performance 32/64 bus with multichannel address wire and data wire.It is used as interlocking frame between peripheral card and the processor/memory at superintegrated peripheral controllers spare.That here, the PCI chip is selected for use is the PCI9054 that U.S. PLX company releases.PCI9054 has adopted advanced PLX data pipe structure technology, and the data on the local bus are transferred on the pci bus fast.In this Interface design, we have adopted following design:
1. the selection of transmission means: PCI9054 supports main equipment, slave unit and three kinds of transmission meanss of DMA transmission as bus main control equipment.
The main equipment mode is meant that native processor is used for the pci bus control and initiates bus transfer.
The slave unit mode refers to that the main equipment on the pci bus has the pci bus control, initiates bus transfer, and local side is operated.
The DMA transmission means is that this bus main control equipment is distinctive, supports the transmission of both direction.
According to the actual requirements, mainly used the high speed storing that the slave unit mode realizes system in system, it is standby to have designed dma mode in addition.
2. the selection of mode of operation: PCI9054 supports three kinds of mode of operations: C pattern, J pattern and M pattern.The C pattern is that a kind of non-multiplex bus mode of operation can be separated address wire and data wire by logic control in the sheet.The M pattern is for the seamless link with some par-ticular processor designs, and the hardware interface simplicity of design need not any unnecessary connection.The J pattern is a kind of bus operation mode of taking, its benefit be the address date line not separately, strict sequential of imitating pci bus for the designer understands the PCI agreement and controls PCI better and communicate by letter good environment is provided, but has increased a lot of control signals,
In actual design, simple and reliable for logic control, selected the C pattern.
Pci interface modular unit by FPGA inside is controlled the sequential logic of PCI9054 interface chip, well finishes the transmission of order and parameter, has realized the dateout of SDRAM buffer memory is transferred on the PC rapidly by pci bus.
Disclosed arbitrary feature in this specification (comprising any accessory claim, summary and accompanying drawing) is unless special narration all can be replaced by other equivalences or the alternative features with similar purpose.That is, unless special narration, each feature is an example in a series of equivalences or the similar characteristics.
The above only is preferred embodiment of the present utility model; not in order to restriction the utility model; all any modifications of within spirit of the present utility model and principle, being done, be equal to and replace and improvement etc., all should be included within the protection range of the present utility model.
Claims (2)
1, a kind of ccd image data acquisition unit is characterized in that: this device comprises CCD camera, Camera Link interface conversion chip, FPGA, SDRAM cache chip and pci interface chip;
Wherein the CCD camera is gathered the CCD camera data by Camera Link interface, and Camera Link interface conversion chip carries out the CCD camera data to input to FPGA after the interface conversion;
Wherein at inner main three modular units of realizing of FPGA: FIFO buffer cell, sdram controller unit and pci interface module; The sdram controller unit links to each other with the SDRAM cache chip, by reading of SDARM controller control SDRAM cache chip, realizes the buffer memory to whole frame ccd image data; The pci interface modular unit links to each other with pci interface chip, realizes the dateout from the SDRAM buffer memory is passed through pci bus, is transferred on the PC fast.
2, a kind of ccd image data acquisition unit as claimed in claim 1 is characterized in that: described sdram controller unit adopts state machine to realize.
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| CN200820161204U CN201378851Y (en) | 2008-11-17 | 2008-11-17 | CCD image data collecting device |
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| CN200820161204U CN201378851Y (en) | 2008-11-17 | 2008-11-17 | CCD image data collecting device |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101841698A (en) * | 2010-04-22 | 2010-09-22 | 中国科学院长春光学精密机械与物理研究所 | Long-distance transfer system for video data |
| CN103049413A (en) * | 2012-12-28 | 2013-04-17 | 中国航空工业集团公司第六三一研究所 | Data conversion and transmission method based on FC (fiber channel) and Camlink buses |
| CN104065905A (en) * | 2014-07-02 | 2014-09-24 | 中国科学院长春光学精密机械与物理研究所 | Reconfigurable topology-type real time image processing system |
| CN104426851A (en) * | 2013-08-23 | 2015-03-18 | 北大方正集团有限公司 | Image signal transmission system and method |
| CN107809635A (en) * | 2011-11-14 | 2018-03-16 | 深圳迈辽技术转移中心有限公司 | Information carrying means |
| CN108417233A (en) * | 2017-02-09 | 2018-08-17 | 爱思开海力士有限公司 | Storage device and its write-in and read method and storage system |
-
2008
- 2008-11-17 CN CN200820161204U patent/CN201378851Y/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101841698A (en) * | 2010-04-22 | 2010-09-22 | 中国科学院长春光学精密机械与物理研究所 | Long-distance transfer system for video data |
| CN107809635A (en) * | 2011-11-14 | 2018-03-16 | 深圳迈辽技术转移中心有限公司 | Information carrying means |
| CN103049413A (en) * | 2012-12-28 | 2013-04-17 | 中国航空工业集团公司第六三一研究所 | Data conversion and transmission method based on FC (fiber channel) and Camlink buses |
| CN103049413B (en) * | 2012-12-28 | 2015-12-09 | 中国航空工业集团公司第六三一研究所 | Based on data conversion and the transmission method of FC and Camlink bus |
| CN104426851A (en) * | 2013-08-23 | 2015-03-18 | 北大方正集团有限公司 | Image signal transmission system and method |
| CN104065905A (en) * | 2014-07-02 | 2014-09-24 | 中国科学院长春光学精密机械与物理研究所 | Reconfigurable topology-type real time image processing system |
| CN108417233A (en) * | 2017-02-09 | 2018-08-17 | 爱思开海力士有限公司 | Storage device and its write-in and read method and storage system |
| CN108417233B (en) * | 2017-02-09 | 2021-12-07 | 爱思开海力士有限公司 | Storage device, writing and reading method thereof, and storage system |
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Granted publication date: 20100106 Termination date: 20101117 |