CN113986192B - Method for converting CoaXPress interface data and Cameralink interface data - Google Patents
Method for converting CoaXPress interface data and Cameralink interface data Download PDFInfo
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
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Abstract
The invention belongs to the technical field of high-speed data transmission, and particularly relates to a method for mutually converting CoaXPress interface data and Cameralink interface data. The method comprises the following steps: step 1: the upper computer software configures the converted working mode through RS 232; step 2: converting the Camellink interface data into CoaXPress interface data; step 3: coaXPress the interface data is converted into Camelline interface data. According to the method, the working mode is configured by the upper computer, the logic control between different interface time sequences is realized by the FPGA, the data conversion of different rates between the input equipment of the CoaXPress interface and the output equipment of the Camelline interface can be realized, or the data conversion of different rates between the input equipment of the Camelline interface and the output equipment of the CoaXPress interface can be realized, and the interconnection and intercommunication between the two interfaces can be realized.
Description
Technical Field
The invention belongs to the technical field of high-speed data transmission, and particularly relates to a method for mutually converting CoaXPress interface data and Cameralink interface data.
Background
With the requirements of the machine vision field for high-speed signal processing, particularly the development of high-resolution, large-area array CCD and CMOS devices, the bandwidth requirements for data transmission are increasing. In recent 20 years, most high-resolution cameras and photoelectric acquisition devices adopt a Cameralink transmission standard, the maximum transmission bandwidth of a Full mode is 6.8Gbps, and the maximum transmission distance of wires is 10 meters. For optoelectronic devices with higher requirements for speed and bandwidth, the conventional Cameralink interface cannot meet the requirements. Therefore, 6 companies such as Adimec and EqcoLogic in the machine vision field jointly propose a new high-speed data transmission interface in 2008, and can realize remote transmission of large-capacity data, namely CoaXPress data transmission standard. At present, the maximum transmission rate of CoaXPress2.0 can reach 12.5Gbps, the theoretical maximum transmission distance of wires can reach 100 meters, the standard joint is Micro BNC, and meanwhile, an uplink with the transmission rate of 20Mbps is also supported for controlling and configuring a data channel.
Along with the enrichment of interface standards and the requirements of different interfaces in different application scenes, including consideration of wires, transmission distance, interconnection between boards of different interfaces, compatibility with old equipment and the like, the mutual conversion between CoaXPress and a camera link is needed. For example, some high-speed devices adopting CoaXPress interfaces need to be connected to the device of the Camellia interface; some data of the Camellia interface needs to be transmitted to a device with a longer distance on the premise of guaranteeing bandwidth and speed, and the data can be considered to be converted into CoaXPress interfaces for transmission. In response to this need, a method capable of converting two kinds of interface devices is required to be designed, so as to achieve the interconnection and timing requirements between the two kinds of interface devices.
Chinese patent CN207052613U discloses a method for acquisition using CoaXPress, cameralink, USB3.0 interface and readout using RS 422. The method can only adopt RS422 to read slowly, has low reading rate and is not suitable for occasions with high real-time requirements.
Disclosure of Invention
First, the technical problem to be solved
The invention aims to solve the technical problems that: how to solve the problem of mutual conversion of a Camellia interface and a CoaXpress interface between different photoelectric devices, how to realize the self-adaptive matching of clocks between input and output interfaces, ensure the real-time performance of data transmission, and provide a high-speed, efficient, scientific and reasonable method for realizing interface compatibility between multiple photoelectric products.
(II) technical scheme
In order to solve the above technical problems, the present invention provides a method for mutually converting CoaXPress interface data and camera link interface data, the method is implemented based on a data interface conversion system, the data interface conversion system includes: the system comprises a Cameralink interface, a Cameralink decoding driving chip, a Cameralink encoding driving chip, a main control element FPGA, coaXPress interface, a CoaXPress encoding driving chip and a CoaXPress decoding driving chip;
The method comprises the following steps:
step1: the upper computer software configures the converted working mode through RS 232;
Step 2: converting the Camellink interface data into CoaXPress interface data;
Step 3: coaXPress the interface data is converted into Camelline interface data.
In the step 1, the whole system is powered by direct current 5V; after the system is powered, the upper computer software communicates with the FPGA through an RS232 serial port, and the RS232 serial port adopts a DB9 connector;
Configuring the input and output flow directions of data on an upper computer interface; when the Camellink is selected as an input interface and CoaXPress is selected as an output interface, setting a working mode that the Camellink interface data is converted into CoaXPress interface data; when CoaXPress is selected as an input interface and a Camellink is selected as an output interface, setting a working mode to be CoaXPress interface data to Camellink interface data.
The step 2 includes the following sub-steps:
Step 21: under the condition that the working mode is that the Camellink interface data is converted into CoaXPress interface data, a Camellink interface and a Camellink decoding receiving driving chip are used for converting LVDS serial data into parallel data and transmitting the parallel data to a master control element FPGA, and the master control element FPGA extracts image data from a line field time sequence according to a Camellink protocol for the input parallel data; then the data is cached in an internal FIFO or an external DDR3SDRAM, and the write-in clock is the pixel clock of the Camellia;
step 22: for the image data with the input clock faster than the output clock, the external DDR3SDRAM can read after one image data is cached;
for image data with input clock slower than output clock, the image data can be read out after one line is buffered by the internal FIFO, and the data delay is the time of one line of data;
The main control element FPGA packs the read cache data into a data packet form according to CoaXPress protocol, adds the head and the tail, then transmits the data to the CoaXPress coding driving chip, and finally transmits the data outwards in a serial LVDS form through a CoaXPress interface.
In the step 21, for the image data with the input clock faster than the output clock, the image data is selected to be stored in an external DDR3 SDRAM memory unit for buffering; for image data with input clock slower than output clock, the image data is selected to be stored in an internal FIFO of the main control element FPGA.
In the step2, when converting the data in two interface formats, buffering is needed through FIFO or DDR3 SDRAM due to inconsistent clocks;
When the FIFO constructed by BRAM resources in the FPGA is cached, the input and output time sequences of the FIFO completely operate in a clock domain crossing mode;
When caching is carried out according to DDR3 SDRAM, two DDR3 SDRAM are required to carry out ping-pong operation, and data conversion of different protocol formats is completed; namely, when one frame of image is written into DDR3 SDRAM 1, the data of the previous frame is read out from DDR3 SDRAM 2 at the same time; when the next frame of image is written into DDR3 SDRAM 2, the data of the previous frame is read out from DDR3 SDRAM 1 at the same time, and in this way, the data delay time is one frame of data time.
Wherein in the operation mode in the step 2, the maximum bandwidth of the input end is 6.8Gbps, and the maximum bandwidth of the output end is 6.25Gbps, so that the bandwidth of the whole channel is 6.25Gbps.
Wherein, the step 3 comprises the following sub-steps:
Step 31: under the condition that the working mode is CoaXPress and interface data are converted into Camellia interface data, a CoaXPress interface and a CoaXPress decoding driving chip thereof are used for converting LVDS serial data into parallel data and transmitting the parallel data to a main control element FPGA, and the main control element FPGA analyzes the input image data according to CoaXPress protocols to remove the head and tail of the input image data and extract the image data; then the data is cached in an internal FIFO of a master control element FPGA or an external DDR3 SDRAM, and the write clock is a CoaXPress pixel clock;
Step 32: for the image data with the input clock faster than the output clock, the external DDR3SDRAM can read after one image is cached;
For data with input clock slower than output clock, reading can be performed after one line is cached by the internal FIFO, and the data delay is the time of one line of data;
And the read cache data is transmitted to a Camellia link code driving chip according to the CAMERLINK interface line field time sequence requirement, and finally is transmitted outwards through a CAMERLINK interface in a serial LVDS mode.
In the step 32, for the data with the input clock faster than the output clock, the image data is selected to be stored in the external DDR3 SDRAM memory unit for buffering; for data whose input clock is slower than the output clock, the image data is selected to be stored in the internal FIFO.
In the step2, when converting the data in two interface formats, buffering is needed through FIFO or DDR3 SDRAM due to inconsistent clocks;
When the FIFO constructed by BRAM resources in the FPGA is cached, the input and output time sequences of the FIFO completely operate in a clock domain crossing mode;
when caching is carried out according to DDR3SDRAM, two DDR3SDRAM are required to carry out ping-pong operation, and data conversion of different protocol formats is completed; namely, when one frame of image is written into DDR3SDRAM 1, the data of the previous frame is read out from DDR3SDRAM 2 at the same time; when the next frame of image is written into DDR3SDRAM 2, the data of the previous frame is read out from DDR3SDRAM 1 at the same time, and in this way, the data delay time is one frame of data time.
In the working mode of the step 3, the maximum bandwidth of the input end is 6.25Gbps, and the maximum bandwidth of the output end is 6.8Gbps, so that the bandwidth of the whole channel is 6.25Gbps.
(III) beneficial effects
Compared with the prior art, the method for mutually converting CoaXPress interface data and Cameralink interface data provided by the technical scheme of the invention can meet the interconnection and intercommunication between two kinds of interface equipment, and has the following beneficial effects:
(1) By adopting the function of converting the CoaXPress interface into the Camelline interface, coaXPress interface equipment can be connected to the photoelectric equipment of the Camelline interface, the defect of short transmission distance of the Camelline cable is overcome, and image data at a longer distance can be acquired by using the CoaXPress cable.
(2) For the camera with high frame frequency and high resolution CoaXPress, the function of converting the CoaXPress interface into the Camellia interface is adopted, so that the existing Camellia acquisition equipment can be conveniently accessed, and the interconnection and intercommunication between the equipment can be rapidly realized.
(3) The rate self-adaptive matching between the two interfaces is realized by a scheme of controlling CoaXPress and a Camellia link interface driving chip by the FPGA and a smaller FPGA resource utilization rate.
Drawings
Fig. 1 and 4 are overall block diagrams of a system in which a Cameralink data interface and CoaXPress data interfaces are converted into each other.
FIG. 2 is a data flow diagram of a ping pong operation of DDR3 SDRAM.
Fig. 3 is a flowchart for configuring an operation mode through an RS232 serial port.
Detailed Description
For the purposes of clarity, content, and advantages of the present invention, a detailed description of the embodiments of the present invention will be described in detail below with reference to the drawings and examples.
In order to solve the above technical problems, the present invention provides a method for mutually converting CoaXPress interface data and camera link interface data, the method is implemented based on a data interface conversion system, the data interface conversion system includes: the system comprises a Cameralink interface, a Cameralink decoding driving chip, a Cameralink encoding driving chip, a main control element FPGA, coaXPress interface, a CoaXPress encoding driving chip and a CoaXPress decoding driving chip;
The method comprises the following steps:
step1: the upper computer software configures the converted working mode through RS 232;
Step 2: converting the Camellink interface data into CoaXPress interface data;
Step 3: coaXPress the interface data is converted into Camelline interface data.
In the step 1, the whole system is powered by direct current 5V; after the system is powered, the upper computer software communicates with the FPGA through an RS232 serial port, and the RS232 serial port adopts a DB9 connector;
Configuring the input and output flow directions of data on an upper computer interface; when the Camellink is selected as an input interface and CoaXPress is selected as an output interface, setting a working mode that the Camellink interface data is converted into CoaXPress interface data; when CoaXPress is selected as an input interface and a Camellink is selected as an output interface, setting a working mode to be CoaXPress interface data to Camellink interface data.
The step 2 includes the following sub-steps:
Step 21: under the condition that the working mode is that the Camellink interface data is converted into CoaXPress interface data, a Camellink interface and a Camellink decoding receiving driving chip are used for converting LVDS serial data into parallel data and transmitting the parallel data to a master control element FPGA, and the master control element FPGA extracts image data from a line field time sequence according to a Camellink protocol for the input parallel data; then the data is cached in an internal FIFO or an external DDR3SDRAM, and the write-in clock is the pixel clock of the Camellia;
step 22: for the image data with the input clock faster than the output clock, the external DDR3SDRAM can read after one image data is cached;
for image data with input clock slower than output clock, the image data can be read out after one line is buffered by the internal FIFO, and the data delay is the time of one line of data;
The main control element FPGA packs the read cache data into a data packet form according to CoaXPress protocol, adds the head and the tail, then transmits the data to the CoaXPress coding driving chip, and finally transmits the data outwards in a serial LVDS form through a CoaXPress interface.
In the step 21, for the image data with the input clock faster than the output clock, the image data is selected to be stored in an external DDR3 SDRAM memory unit for buffering; for image data with input clock slower than output clock, the image data is selected to be stored in an internal FIFO of the main control element FPGA.
In the step2, when converting the data in two interface formats, buffering is needed through FIFO or DDR3 SDRAM due to inconsistent clocks;
When the FIFO constructed by BRAM resources in the FPGA is cached, the input and output time sequences of the FIFO completely operate in a clock domain crossing mode;
when caching is carried out according to DDR3SDRAM, two DDR3SDRAM are required to carry out ping-pong operation, and data conversion of different protocol formats is completed; namely, when one frame of image is written into DDR3SDRAM 1, the data of the previous frame is read out from DDR3SDRAM 2 at the same time; when the next frame of image is written into DDR3SDRAM 2, the data of the previous frame is read out from DDR3SDRAM 1 at the same time, and in this way, the data delay time is one frame of data time.
Wherein in the operation mode in the step 2, the maximum bandwidth of the input end is 6.8Gbps, and the maximum bandwidth of the output end is 6.25Gbps, so that the bandwidth of the whole channel is 6.25Gbps.
Wherein, the step 3 comprises the following sub-steps:
Step 31: under the condition that the working mode is CoaXPress and interface data are converted into Camellia interface data, a CoaXPress interface and a CoaXPress decoding driving chip thereof are used for converting LVDS serial data into parallel data and transmitting the parallel data to a main control element FPGA, and the main control element FPGA analyzes the input image data according to CoaXPress protocols to remove the head and tail of the input image data and extract the image data; then the data is cached in an internal FIFO of a master control element FPGA or an external DDR3 SDRAM, and the write clock is a CoaXPress pixel clock;
Step 32: for the image data with the input clock faster than the output clock, the external DDR3 SDRAM can read after one image is cached;
For data with input clock slower than output clock, reading can be performed after one line is cached by the internal FIFO, and the data delay is the time of one line of data;
And the read cache data is transmitted to a Camellia link code driving chip according to the CAMERLINK interface line field time sequence requirement, and finally is transmitted outwards through a CAMERLINK interface in a serial LVDS mode.
In the step 32, for the data with the input clock faster than the output clock, the image data is selected to be stored in the external DDR3 SDRAM memory unit for buffering; for data whose input clock is slower than the output clock, the image data is selected to be stored in the internal FIFO.
In the step2, when converting the data in two interface formats, buffering is needed through FIFO or DDR3 SDRAM due to inconsistent clocks;
When the FIFO constructed by BRAM resources in the FPGA is cached, the input and output time sequences of the FIFO completely operate in a clock domain crossing mode;
when caching is carried out according to DDR3SDRAM, two DDR3SDRAM are required to carry out ping-pong operation, and data conversion of different protocol formats is completed; namely, when one frame of image is written into DDR3SDRAM 1, the data of the previous frame is read out from DDR3SDRAM 2 at the same time; when the next frame of image is written into DDR3SDRAM 2, the data of the previous frame is read out from DDR3SDRAM 1 at the same time, and in this way, the data delay time is one frame of data time.
In the working mode of the step 3, the maximum bandwidth of the input end is 6.25Gbps, and the maximum bandwidth of the output end is 6.8Gbps, so that the bandwidth of the whole channel is 6.25Gbps.
Example 1
The embodiment aims to solve the problem of mutual conversion between CoaXPress interfaces and a Cameralink, and realize interconnection and intercommunication and real-time transmission between different interface devices. A Xilinx Kintex-7 series FPGA is used as a main control logic element to logically control the receiving and sending of the two interfaces. The CoaXPress decoding chip is responsible for converting and receiving LVDS data into parallel data, and the CoaXPress encoding chip is responsible for converting and transmitting the parallel data into LVDS serial data; the Camelline decoding chip is responsible for converting and receiving LVDS data into parallel data, and the Camelline encoding chip is responsible for converting and transmitting parallel data into LVDS serial data. The invention can realize the conversion from CoaXPress interface input data to Camelline interface output data, or realize the conversion from Camelline interface input data to CoaXPress interface output data, or realize the two-way independent transmission of two interfaces at the same time. An infrared image with a resolution of 1000 frames 640 x 512 per second can be transmitted in real time, calculated according to the maximum data throughput of 6.25 Gbps.
When the function of the Camelline input interface to CoaXPress output interfaces is used in combination with FIGS. 1 and 4, the Camelline interfaces 1 and 2 are connected to form CAMERALINK FULL input mode. LVDS differential data is input through a Camellia interface, two paths of Camellia decoding and receiving driving chips finish conversion from serial data to parallel data, and meanwhile, the FPGA main control logic caches the data into the FIFO 1 or the DDR3 SDRAM, and the write-in clock is the pixel clock of the Camellia. And the FPGA main control logic reads the data from the cache, packages the data according to a CoaXPress protocol format, adds head and tail information, sends the data to a CoaXPress coding chip for 8b/10b coding and equalization, and sends the data to a CoaXPress connector Micro BNC 1 in an LVDS mode. With this function, the maximum bandwidth of the input is 6.8Gbps and the maximum bandwidth of the output is 6.25Gbps, so the bandwidth of the entire path is 6.25Gbps.
When CoaXPress input interfaces are used to convert the functions of the Camelline output interfaces in combination with FIG. 1, the Camelline interfaces 3 and 4 are connected to form CAMERALINK FULL output modes. LVDS differential data is input through a CoaXPress interface Micro BNC 2, a CoaXPress decoding and receiving driving chip is used for completing conversion from serial data to parallel data, the head part and the tail part are removed according to a CoaXPress protocol, image data are extracted, then the data are cached in a FIFO 2 or DDR3 SDRAM, and the pixel clock of which the writing clock is CoaXPress. And the FPGA main control logic reads out the data from the cache, packages the data according to a line field format of a Camellia link protocol, sends the data to two paths of Camellia link sending chips for coding, and sends the data to Camellia link connectors Camellia link interfaces 3 and 4 in an LVDS mode. With this function, the maximum bandwidth of the input is 6.25Gbps, and the maximum bandwidth of the output is 6.8Gbps, so the bandwidth of the entire path is 6.25Gbps.
In connection with fig. 2, when converting data in two interface formats, buffering is required by FIFO or DDR3 SDRAM due to inconsistent clocks. The FIFO constructed by BRAM resources in the FPGA is cached, and the input and output time sequence of the FIFO is completely operated according to the FIFO cross-clock domain mode. When caching is carried out according to DDR3 SDRAM, two pieces of ping-pong operation are needed to finish data conversion of different protocol formats. When one frame of image is written into DDR3 SDRAM 1, the data of the previous frame is read out from DDR3 SDRAM 2 at the same time; when the next frame image is written into the DDR3 SDRAM 2, the previous frame data is read out from the DDR3 SDRAM 1 at the same time. In this way, the data delay time is one frame data time.
With reference to fig. 3, after the system is started, an RS232 serial port can be used to select the input/output interface mode of the system, typical 4 video formats are built in the system, and after the typical format is selected, the system performs conversion according to the format. For the unusual video format, the input and output clock, the resolution ratio, the working time sequence of the two interfaces and the like of the unusual video format can be configured through the serial port, the unusual video format is sent to the FPGA, and then the corresponding working mode is started. The communication mode of the RS232 serial port is baud rate 115200, 8 bits of data and even check.
Example 2
The embodiment provides a mutual conversion method of a Cameralink data interface and a CoaXpress data interface, which comprises the following steps:
step 1: the upper computer software configures the conversion mode through RS 232;
Step 2: converting the Camellink interface data into CoaXPress interface data;
Step 3: coaXPress the interface data is converted into Camelline interface data.
Wherein said step1 comprises the sub-steps of:
The whole system is powered by direct current 5V. After the system is powered, the upper computer software communicates with the FPGA through an RS232 serial port, and the RS232 adopts a DB9 connector. Configuring the input and output flow directions of data on an upper computer interface, selecting CoaXPress as an input interface and adopting a Camellia link as an output interface, and setting the working mode to be CoaXPress to be Camellia link; and selecting the Camelline as an input interface and CoaXPress as an output interface, and setting the working mode as Camelline to CoaXPress. The configuration of the input interface adopts a clock and the output clock of the output interface, so that data with different rates can be converted between two decoupling modes. The data interface conversion system is internally provided with a typical video format working mode, and can be adaptively matched with an input/output interface mode to realize seamless joint and input/output; for unusual working modes, the specific working mode of the system can be configured through the upper computer.
Wherein said step2 comprises the sub-steps of:
2.1 converting LVDS serial data into parallel data by using a Camellia interface and a corresponding receiving driving chip thereof, transmitting the parallel data to a master control element FPGA, and extracting image data from line field time sequences by the FPGA according to a Camellia protocol on the input data. For data with input clock faster than output clock, selecting to store image data into external DDR3 SDRAM storage unit for buffering; for data whose input clock is slower than the output clock, selecting to store the image data into the internal FIFO;
2.2 data with an input clock faster than an output clock can be read after an external DDR3 SDRAM caches an image; the data with input clock slower than output clock can be read out after one line is buffered by the internal FIFO, and the data delay is the time of one line of data. The read cache data is packaged into a data packet form according to CoaXPress protocol, the head and the tail are added, then the data is transmitted to a CoaXPress coding transmission driver chip, and finally the data is transmitted outwards in a serial LVDS form;
2.3 pairs CAMERLINK of input to CoaXPress of output, the core of the invention is that the self-adaptive matching can be carried out according to different clock rates, and the automatic conversion of different rates can be completed. According to the difference between CAMERLINK input clocks and CoaXPress output clocks, an internal clock matching scheme is automatically completed, the delay of a pixel clock level between two interfaces can be realized by adopting a FIFO buffer memory in the FPGA, and the conversion from a slow clock to a fast clock is completed; the external DDR3SDRAM is adopted to realize the caching of an image, and the conversion from a fast clock to a slow clock is completed; the maximum bandwidth of the input data is 6.8Gbps.
Wherein, the step 3 comprises the following substeps:
And 3.1, converting LVDS serial data into parallel data by using CoaXPress interfaces and corresponding receiving driving chips, transmitting the parallel data to a master control element FPGA, analyzing the head and tail of the input data by the FPGA according to CoaXPress protocol, and extracting image data. For data with input clock faster than output clock, selecting to store image data into external DDR3 SDRAM storage unit for buffering; for data whose input clock is slower than the output clock, selecting to store the image data into the internal FIFO;
3.2, inputting data with a clock faster than an output clock, and reading out after the external DDR3 SDRAM finishes caching an image; the data with input clock slower than output clock can be read out after one line is buffered by the internal FIFO, and the data delay is the time of one line of data. The read cache data is transmitted to a Camellia link code transmission driver chip according to CAMERLINK interface line field time sequence requirements, and finally is transmitted outwards in a serial LVDS mode;
3.3 to CoaXPress to CAMERLINK, the core of the invention is that the invention can adaptively match according to different clock rates to finish the automatic conversion of different rates. According to the difference between CoaXPress input clocks and CAMERLINK output clocks, an internal clock matching scheme is automatically completed, the delay of a pixel clock level between two interfaces can be realized by adopting a FIFO buffer memory in the FPGA, and the conversion from a slow clock to a fast clock is completed; the external DDR3SDRAM is adopted to realize the caching of an image, and the conversion from a fast clock to a slow clock is completed; the maximum bandwidth of the input data is 6.25Gbps.
In the data interface conversion system, coaXPress is converted into a main element FPGA of conversion logic adopted by a Camellink data interface, and Xilinx XC7K325T is adopted to realize logic time sequence control of the two interfaces; coaXPress the receiving and decoding chip adopts a CoaXPress2.0 chip EQCO X40 of Microchip company to realize high-speed LVDS data serial-parallel conversion, and the interface connector adopts a Micro BNC; the Camelline coding transmission chip adopts two DS90CR287 chips of National Semiconductor to form CAMERALINK FULL mode, and realizes conversion from parallel data to serial LVDS data, and the interface connector adopts two SDR26.
In the data interface conversion system, a main element FPGA of the conversion logic of the Camellia link to CoaXPress data interfaces adopts the same piece of FPGA with the functions, so that logic time sequence control of two interfaces is realized; the Camelline encoding and decoding receiving chip adopts two DS90CR288 chips of National Semiconductor company to form CAMERALINK FULL mode, and realizes the conversion from serial LVDS data to parallel data, and the interface connector adopts two paths of SDR26; coaXPress the encoding transmission chip adopts a CoaXPress2.0 chip EQCO X40 of Microchip company to realize the conversion from parallel data to LVDS data, and the interface connector adopts Micro BNC.
Example 3
The embodiment provides a method for mutually converting high-speed CoaXPress interface data and high-speed Camellia interface data, which comprises the following steps:
step 1: the upper computer software configures the conversion mode through RS 232;
Step 2: converting the Camellink interface data into CoaXPress interface data;
Step 3: coaXPress the interface data is converted into Camelline interface data.
Wherein, the step 1 comprises the following substeps:
1.1, after the system is powered on, starting up the upper computer software, and communicating with the FPGA through RS 232;
1.2, configuring input and output flow directions of data, and selecting a corresponding interface;
1.3 for typical video formats, the mode of operation is directly initiated;
1.4 for unusual video formats, setting the pixel clock, resolution and working time sequence of the unusual video formats, and then starting the working mode;
wherein, the step2 comprises the following substeps:
2.1 converting LVDS image data into parallel data by using a Camellia interface and a corresponding receiving driving chip thereof, transmitting the parallel data to a master control element FPGA, and storing real-time image data into an internal FIFO or an external DDR3SDRAM by the FPGA for caching according to different input and output clocks;
2.2 After the FPGA reads out one row of data from the FIFO or reads out one image data from the DDR3 SDRAM, the data is packed according to CoaXPress interface time sequence and then is transmitted to a CoaXPress coding transmission driver chip, and finally, the data is transmitted outwards in an LVDS mode;
2.3 in order to realize the time sequence self-adaptive matching between different input and output clocks, when the input clock is faster than the output clock, DDR3 SDRAM is adopted to realize the caching of an image, and then the output is carried out; when the input clock is slower than the output clock, the FIFO in the FPGA is adopted to buffer one line of data, and the output can be performed.
Wherein, the step 3 comprises the following substeps:
3.1 converting LVDS data into parallel data by using CoaXPress interfaces and corresponding receiving driving chips, transmitting the parallel data to a main control element FPGA, analyzing the data according to CoaXPress protocols, and selecting real-time image data to be stored into an internal FIFO or an external DDR3 SDRAM by the FPGA for caching according to different input and output clocks;
3.2, after the FPGA reads out one line of data from the FIFO or reads out one image data from the DDR3 SDRAM, the parallel data are transmitted to a Camellia link code transmission driver chip according to CAMERLINK interface time sequence requirements, and finally, the parallel data are transmitted outwards in an LVDS mode;
3.3 in order to realize the time sequence self-adaptive matching between different input and output clocks, when the input clock is faster than the output clock, DDR3 SDRAM is adopted to realize the caching of an image, and then the output is carried out; when the input clock is slower than the output clock, a FIFO in the FPGA is adopted to buffer one line of data, so that the output can be performed;
The main element FPGA of the data interface conversion adopts Xilinx XC7K325T to realize logic control of different interface time sequences; coaXPress the receiving and decoding chip adopts a first CoaXPress2.0 chip EQCO X40 of Microchip company to realize high-speed LVDS data serial-parallel conversion, and the interface adopts Micro BNC; the Camelline encoding transmission chip adopts two National Semiconductor DS90CR287 chips to form CAMERALINK FULL mode, and realizes conversion from parallel data to serial LVDS data, and the interface adopts two SDR26.
The main element FPGA of the data interface conversion adopts the same FPGA as in claim 3, so that logic control of different interface time sequences is realized; the Camelline encoding and decoding receiving chip adopts two National Semiconductor DS90CR288 chips to form CAMERALINK FULL mode, and realizes the conversion from serial LVDS data to parallel data, and the interface adopts two paths of SDR26; coaXPress the encoding transmission chip adopts a CoaXPress2.0 chip EQCO X40 of Microchip company to realize the conversion from parallel data to LVDS data, and the interface adopts Micro BNC.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and variations could be made by those skilled in the art without departing from the technical principles of the present invention, and such modifications and variations should also be regarded as being within the scope of the invention.
Claims (8)
1. A method for interconverting CoaXPress interface data and camelink interface data, the method being implemented based on a data interface conversion system, the data interface conversion system comprising: the system comprises a Cameralink interface, a Cameralink decoding driving chip, a Cameralink encoding driving chip, a main control element FPGA, coaXPress interface, a CoaXPress encoding driving chip and a CoaXPress decoding driving chip;
The method comprises the following steps:
step1: the upper computer software configures the converted working mode through RS 232;
Step 2: converting the Camellink interface data into CoaXPress interface data;
step 3: coaXPress converting interface data into Camellia interface data;
In the step 1, the whole system is powered by direct current 5V; after the system is powered, the upper computer software communicates with the FPGA through an RS232 serial port, and the RS232 serial port adopts a DB9 connector;
Configuring the input and output flow directions of data on an upper computer interface; when the Camellink is selected as an input interface and CoaXPress is selected as an output interface, setting a working mode that the Camellink interface data is converted into CoaXPress interface data; when CoaXPress is selected as an input interface and a Camelline is selected as an output interface, setting a working mode as CoaXPress interface data to Camelline interface data;
the step 2 includes the following sub-steps:
Step 21: under the condition that the working mode is that the Camellink interface data is converted into CoaXPress interface data, a Camellink interface and a Camellink decoding receiving driving chip are used for converting LVDS serial data into parallel data and transmitting the parallel data to a master control element FPGA, and the master control element FPGA extracts image data from a line field time sequence according to a Camellink protocol for the input parallel data; then the data is cached in an internal FIFO or an external DDR3SDRAM, and the write-in clock is the pixel clock of the Camellia;
step 22: for the image data with the input clock faster than the output clock, the external DDR3SDRAM can read after one image data is cached;
for image data with input clock slower than output clock, the image data can be read out after one line is buffered by the internal FIFO, and the data delay is the time of one line of data;
The main control element FPGA packs the read cache data into a data packet form according to CoaXPress protocol, adds the head and the tail, then transmits the data to the CoaXPress coding driving chip, and finally transmits the data outwards in a serial LVDS form through a CoaXPress interface.
2. The method for converting CoaXPress interface data and cam line interface data to each other according to claim 1, wherein in step 21, for the image data whose input clock is faster than the output clock, the image data is selected to be stored in an external DDR3 SDRAM memory unit for buffering; for image data with input clock slower than output clock, the image data is selected to be stored in an internal FIFO of the main control element FPGA.
3. The method for converting CoaXPress interface data and cam interface data to each other according to claim 2, wherein in step 2, when converting the two interface formats of data, buffering is required by FIFO or DDR3SDRAM due to inconsistent clocks;
When the FIFO constructed by BRAM resources in the FPGA is cached, the input and output time sequences of the FIFO completely operate in a clock domain crossing mode;
when caching is carried out according to DDR3SDRAM, two DDR3SDRAM are required to carry out ping-pong operation, and data conversion of different protocol formats is completed; namely, when one frame of image is written into DDR3SDRAM 1, the data of the previous frame is read out from DDR3SDRAM 2 at the same time; when the next frame of image is written into DDR3SDRAM 2, the data of the previous frame is read out from DDR3SDRAM 1 at the same time, and in this way, the data delay time is one frame of data time.
4. The method for converting CoaXPress interface data and cam line interface data to each other according to claim 2, wherein in said step 2 operation mode, the maximum bandwidth of the input terminal is 6.8Gbps and the maximum bandwidth of the output terminal is 6.25Gbps, so that the bandwidth of the entire path is 6.25Gbps.
5. The method for converting CoaXPress interface data and camelink interface data into each other according to claim 1, wherein the step 3 comprises the following sub-steps:
Step 31: under the condition that the working mode is CoaXPress and interface data are converted into Camellia interface data, a CoaXPress interface and a CoaXPress decoding driving chip thereof are used for converting LVDS serial data into parallel data and transmitting the parallel data to a main control element FPGA, and the main control element FPGA analyzes the input image data according to CoaXPress protocols to remove the head and tail of the input image data and extract the image data; then the data is cached in an internal FIFO of a master control element FPGA or an external DDR3 SDRAM, and the write clock is a CoaXPress pixel clock;
Step 32: for the image data with the input clock faster than the output clock, the external DDR3SDRAM can read after one image is cached;
For data with input clock slower than output clock, reading can be performed after one line is cached by the internal FIFO, and the data delay is the time of one line of data;
And the read cache data is transmitted to a Camellia link code driving chip according to the CAMERLINK interface line field time sequence requirement, and finally is transmitted outwards through a CAMERLINK interface in a serial LVDS mode.
6. The method for converting CoaXPress interface data and Camelline interface data to each other according to claim 5, wherein in step 32, for data whose input clock is faster than the output clock, storing the image data in an external DDR3 SDRAM memory unit for buffering; for data whose input clock is slower than the output clock, the image data is selected to be stored in the internal FIFO.
7. The method for converting CoaXPress interface data and Camellia interface data to each other according to claim 5, wherein in step 2, when converting the two interface formats of data, buffering is required by FIFO or DDR3SDRAM due to inconsistent clocks;
When the FIFO constructed by BRAM resources in the FPGA is cached, the input and output time sequences of the FIFO completely operate in a clock domain crossing mode;
when caching is carried out according to DDR3SDRAM, two DDR3SDRAM are required to carry out ping-pong operation, and data conversion of different protocol formats is completed; namely, when one frame of image is written into DDR3SDRAM 1, the data of the previous frame is read out from DDR3SDRAM 2 at the same time; when the next frame of image is written into DDR3SDRAM 2, the data of the previous frame is read out from DDR3SDRAM 1 at the same time, and in this way, the data delay time is one frame of data time.
8. The method for converting CoaXPress interface data and cam line interface data to each other according to claim 5, wherein in said operation mode of step 3, the maximum bandwidth of the input is 6.25Gbps and the maximum bandwidth of the output is 6.8Gbps, so that the bandwidth of the entire path is 6.25Gbps.
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