CN113986192A - Method for mutual conversion between CoaXPress interface data and Cameralink interface data - Google Patents
Method for mutual conversion between CoaXPress interface data and Cameralink interface data Download PDFInfo
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Abstract
The invention belongs to the technical field of high-speed data transmission, and particularly relates to a method for mutually converting CoaXPress interface data and Cameralink interface data. The method comprises the following steps: step 1: the upper computer software configures the converted working mode through RS 232; step 2: converting the Cameralink interface data into CoaXPress interface data; and step 3: the CoaXPress interface data is converted into Cameralink interface data. The method configures a working mode through an upper computer, realizes logic control between different interface time sequences by an FPGA, can realize data conversion at different rates between input equipment of a CoaXPress interface and output equipment of a Cameralink interface, or realize data conversion at different rates between the input equipment of the Cameralink interface and the output equipment of the CoaXPress interface, and achieves interconnection and intercommunication between the two interfaces.
Description
Technical Field
The invention belongs to the technical field of high-speed data transmission, and particularly relates to a method for mutually converting CoaXPress interface data and Cameralink interface data.
Background
With the demand of high-speed signal processing in the field of machine vision, especially the development of high-resolution, large-area array CCD and CMOS devices, the bandwidth requirement for data transmission is increasing. In recent 20 years, most high-resolution cameras and photoelectric acquisition equipment adopt the Cameralink transmission standard, the maximum transmission bandwidth of the Full mode is 6.8Gbps, and the maximum transmission distance of wires is 10 meters. For optoelectronic devices with higher speed and bandwidth requirements, the conventional Cameralink interface has not been able to meet the requirements. Therefore, 6 companies in the field of machine vision, such as Adimec and eqcoLogic, jointly introduced a new high-speed data transmission interface in 2008, which can realize long-distance transmission of large-capacity data, i.e., the CoaXPress data transmission standard. At present, the maximum transmission rate of CoaXPress2.0 can reach 12.5Gbps, the theoretical maximum transmission distance of a wire can reach 100 meters, the standard connector is a Micro BNC, and an uplink with the transmission speed of 20Mbps is supported for controlling and configuring a data channel.
With the abundance of interface standards and the requirements for different interfaces in different application scenarios, including wire considerations, transmission distance considerations, interconnection between boards with different interfaces, compatibility with legacy equipment, etc., interconversion between CoaXPress and Cameralink is required. For example, some high-speed devices adopting CoaXPress interface need to be connected to the device of Cameralink interface; some Cameralink interface data need to be transmitted to a device at a longer distance on the premise of guaranteeing bandwidth and speed, and it can be considered to be converted into a CoaXPress interface for transmission. In view of this requirement, a method capable of converting two interface devices is required to be designed to meet the requirements of interconnection and timing sequence between the two interface devices.
Chinese patent CN207052613U discloses a method for collecting data by using interfaces such as CoaXPress, Cameralink, USB3.0, etc., and reading data by using RS 422. The method can only adopt RS422 to read slowly, has low reading rate and is not suitable for occasions with high real-time requirement.
Disclosure of Invention
Technical problem to be solved
The technical problem to be solved by the invention is as follows: how to solve the problem of mutual conversion between a Cameralink interface and a CoaXpress interface between different photoelectric devices, how to realize the self-adaptive matching of clocks between an input interface and an output interface, ensure the real-time performance of data transmission, and provide a high-speed, high-efficiency, scientific and reasonable method for realizing the interface compatibility between multi-type photoelectric products.
(II) technical scheme
In order to solve the above technical problem, the present invention provides a method for mutually converting CoaXPress interface data and Cameralink interface data, wherein the method is implemented based on a data interface conversion system, and the data interface conversion system comprises: the device comprises a Cameralink interface, a Cameralink decoding driving chip, a Cameralink coding driving chip, a main control element FPGA, a CoaXPress interface, a CoaXPress coding driving chip and a CoaXPress decoding driving chip;
the method comprises the following steps:
step 1: the upper computer software configures the converted working mode through RS 232;
step 2: converting the Cameralink interface data into CoaXPress interface data;
and step 3: the CoaXPress interface data is converted into Cameralink interface data.
In the step 1, the whole system adopts direct current 5V for power supply; after the system is powered on, the upper computer software is communicated with the FPGA through an RS232 serial port, and the DB9 connector is adopted as the RS232 serial port;
configuring the input and output flow direction of data on an upper computer interface; when the Cameralink is selected as an input interface and CoaXPress is selected as an output interface, setting a working mode that the Cameralink interface data is converted into CoaXPress interface data; when CoaXPress is selected as an input interface and Cameralink is selected as an output interface, the working mode is set to convert CoaXPress interface data into Cameralink interface data.
Wherein, in the step 2, the following substeps are included:
step 21: under the condition that the working mode is that the Cameralink interface data is converted into CoaXPress interface data, a Cameralink interface and a Cameralink decoding receiving driving chip are used for converting LVDS serial data into parallel data and transmitting the parallel data to a main control element FPGA, and the main control element FPGA extracts image data from a line field time sequence of the input parallel data according to a Cameralink protocol; then, the data is cached in an internal FIFO or an external DDR3SDRAM, and the writing clock of the data is the pixel clock of Cameralink;
step 22: for image data with an input clock faster than an output clock, the external DDR3SDRAM can read out the image data after finishing caching the image data;
for image data with an input clock slower than an output clock, the image data can be read out after one line of data is cached by an internal FIFO, and the data delay is the time of one line of data;
the main control element FPGA packs the read cache data into a data packet form according to a CoaXPress protocol, adds a head part and a tail part, transmits the data packet to a CoaXPress coding driving chip, and finally transmits the data packet outwards through a CoaXPress interface in a serial LVDS form.
In step 21, for image data with an input clock faster than an output clock, the image data is stored in an external DDR3SDRAM memory unit for caching; and for image data with an input clock slower than an output clock, selecting to store the image data into an internal FIFO of the main control element FPGA.
In step 2, when data in two interface formats are converted, buffering needs to be performed through FIFO or DDR3SDRAM due to inconsistency of front and rear clocks;
when the FIFO constructed by BRAM resources in the FPGA is used for caching, the input and output time sequence of the FPGA is operated completely according to the FIFO clock domain crossing mode;
when caching is carried out according to DDR3SDRAM, two pieces of DDR3SDRAM are needed to carry out ping-pong operation, and data conversion of different protocol formats is completed; namely, when one frame of image is written into the DDR3SDRAM 1, the last frame of data is read out from the DDR3SDRAM 2 at the same time; when the next frame image is written into the DDR3SDRAM 2, the last frame data is read out from the DDR3SDRAM 1 at the same time, and in this way, the data delay time is one frame data time.
In the operation mode in step 2, the maximum bandwidth of the input end is 6.8Gbps, and the maximum bandwidth of the output end is 6.25Gbps, so that the bandwidth of the whole channel is 6.25 Gbps.
Wherein, in the step 3, the following substeps are included:
step 31: under the condition that the working mode is that CoaXPress interface data is converted into Cameralink interface data, a CoaXPress interface and a CoaXPress decoding driving chip thereof are used for converting LVDS serial data into parallel data and transmitting the parallel data to a main control element FPGA, the main control element FPGA analyzes input image data according to a CoaXPress protocol to remove the head and the tail of the input image data, and the image data are extracted; then, the data is cached in an internal FIFO (first in first out) or an external DDR3SDRAM (synchronous dynamic random access memory) of a main control element FPGA (field programmable gate array), and the writing clock of the data is a pixel clock of CoaXPres;
step 32: for image data with an input clock faster than an output clock, the external DDR3SDRAM can read out after finishing caching an image;
for data with an input clock slower than an output clock, the data can be read out after the internal FIFO buffers one line, and the data is delayed to be the time of one line of data;
and the read cache data is transmitted to a Cameralink coding driving chip according to the requirements of the line field time sequence of the Cameralink interface, and finally is transmitted to the outside through the Cameralink interface in a serial LVDS mode.
In step 32, for data with an input clock faster than an output clock, the image data is stored in an external DDR3SDRAM memory unit for caching; for data with an input clock slower than an output clock, the image data is selectively stored in the internal FIFO.
In step 2, when data in two interface formats are converted, buffering needs to be performed through FIFO or DDR3SDRAM due to inconsistency of front and rear clocks;
when the FIFO constructed by BRAM resources in the FPGA is used for caching, the input and output time sequence of the FPGA is operated completely according to the FIFO clock domain crossing mode;
when caching is carried out according to DDR3SDRAM, two pieces of DDR3SDRAM are needed to carry out ping-pong operation, and data conversion of different protocol formats is completed; namely, when one frame of image is written into DDR3SDRAM 1, the last frame of data is read out from DDR3SDRAM 2 at the same time; when the next frame image is written into the DDR3SDRAM 2, the last frame data is read out from the DDR3SDRAM 1 at the same time, and in this way, the data delay time is one frame data time.
In the working mode of step 3, the maximum bandwidth of the input end is 6.25Gbps, and the maximum bandwidth of the output end is 6.8Gbps, so that the bandwidth of the whole channel is 6.25 Gbps.
(III) advantageous effects
Compared with the prior art, the method for mutually converting CoaXPress interface data and Cameralink interface data provided by the technical scheme of the invention can meet the interconnection and intercommunication between two interface devices, and has the following beneficial effects:
(1) the CoaXPress interface is converted into the Cameralink interface, so that the CoaXPress interface equipment can be connected to the photoelectric equipment of the Cameralink interface, the defect that the transmission distance of the Cameralink cable is short is overcome, and the CoaXPress cable can be used for collecting image data at a longer distance.
(2) For a CoaXPress camera with high frame frequency and high resolution, the CoaXPress interface is converted into the function of a Cameralink interface, the CoaXPress camera can be conveniently accessed into the existing Cameralink acquisition equipment, and the interconnection and intercommunication among the equipment can be quickly realized.
(3) Through the scheme that the CoaXPress and Cameralink interface driving chip are controlled by the FPGA, the rate self-adaptive matching between the two interfaces is realized by using a smaller FPGA resource utilization rate.
Drawings
Fig. 1 and 4 are overall block diagrams of a system in which the Cameralink data interface and the CoaXPress data interface are mutually converted.
Fig. 2 is a data flow diagram of a DDR3SDRAM for ping-pong operations.
Fig. 3 is a flow chart of configuring the operation mode through the RS232 serial port.
Detailed Description
In order to make the objects, contents, and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.
In order to solve the above technical problem, the present invention provides a method for mutually converting CoaXPress interface data and Cameralink interface data, wherein the method is implemented based on a data interface conversion system, and the data interface conversion system comprises: the device comprises a Cameralink interface, a Cameralink decoding driving chip, a Cameralink coding driving chip, a main control element FPGA, a CoaXPress interface, a CoaXPress coding driving chip and a CoaXPress decoding driving chip;
the method comprises the following steps:
step 1: the upper computer software configures the converted working mode through RS 232;
step 2: converting the Cameralink interface data into CoaXPress interface data;
and step 3: the CoaXPress interface data is converted into Cameralink interface data.
In the step 1, the whole system adopts direct current 5V for power supply; after the system is powered on, the upper computer software is communicated with the FPGA through an RS232 serial port, and the DB9 connector is adopted as the RS232 serial port;
configuring the input and output flow direction of data on an upper computer interface; when the Cameralink is selected as an input interface and CoaXPress is selected as an output interface, setting a working mode that the Cameralink interface data is converted into CoaXPress interface data; when CoaXPress is selected as an input interface and Cameralink is selected as an output interface, the working mode is set to convert CoaXPress interface data into Cameralink interface data.
Wherein, in the step 2, the following substeps are included:
step 21: under the condition that the working mode is that the Cameralink interface data is converted into CoaXPress interface data, a Cameralink interface and a Cameralink decoding receiving driving chip are used for converting LVDS serial data into parallel data and transmitting the parallel data to a main control element FPGA, and the main control element FPGA extracts image data from a line field time sequence of the input parallel data according to a Cameralink protocol; then, the data is cached in an internal FIFO or an external DDR3SDRAM, and the writing clock of the data is the pixel clock of Cameralink;
step 22: for image data with an input clock faster than an output clock, the external DDR3SDRAM can read out the image data after finishing caching the image data;
for image data with an input clock slower than an output clock, the image data can be read out after one line of data is cached by an internal FIFO, and the data delay is the time of one line of data;
the main control element FPGA packs the read cache data into a data packet form according to a CoaXPress protocol, adds a head part and a tail part, transmits the data packet to a CoaXPress coding driving chip, and finally transmits the data packet outwards through a CoaXPress interface in a serial LVDS form.
In step 21, for image data with an input clock faster than an output clock, the image data is stored in an external DDR3SDRAM memory unit for caching; and for image data with an input clock slower than an output clock, selecting to store the image data into an internal FIFO of the main control element FPGA.
In step 2, when data in two interface formats are converted, buffering needs to be performed through FIFO or DDR3SDRAM due to inconsistency of front and rear clocks;
when the FIFO constructed by BRAM resources in the FPGA is used for caching, the input and output time sequence of the FPGA is operated completely according to the FIFO clock domain crossing mode;
when caching is carried out according to DDR3SDRAM, two pieces of DDR3SDRAM are needed to carry out ping-pong operation, and data conversion of different protocol formats is completed; namely, when one frame of image is written into DDR3SDRAM 1, the last frame of data is read out from DDR3SDRAM 2 at the same time; when the next frame image is written into the DDR3SDRAM 2, the last frame data is read out from the DDR3SDRAM 1 at the same time, and in this way, the data delay time is one frame data time.
In the operation mode in step 2, the maximum bandwidth of the input end is 6.8Gbps, and the maximum bandwidth of the output end is 6.25Gbps, so that the bandwidth of the whole channel is 6.25 Gbps.
Wherein, in the step 3, the following substeps are included:
step 31: under the condition that the working mode is that CoaXPress interface data is converted into Cameralink interface data, a CoaXPress interface and a CoaXPress decoding driving chip thereof are used for converting LVDS serial data into parallel data and transmitting the parallel data to a main control element FPGA, the main control element FPGA analyzes input image data according to a CoaXPress protocol to remove the head and the tail of the input image data, and the image data are extracted; then, the data is cached in an internal FIFO (first in first out) or an external DDR3SDRAM (synchronous dynamic random access memory) of a main control element FPGA (field programmable gate array), and the writing clock of the data is a pixel clock of CoaXPres;
step 32: for image data with an input clock faster than an output clock, the external DDR3SDRAM can read out after finishing caching an image;
for data with an input clock slower than an output clock, the data can be read out after the internal FIFO buffers one line, and the data is delayed to be the time of one line of data;
and the read cache data is transmitted to a Cameralink coding driving chip according to the requirements of the line field time sequence of the Cameralink interface, and finally is transmitted to the outside through the Cameralink interface in a serial LVDS mode.
In step 32, for data with an input clock faster than an output clock, the image data is stored in an external DDR3SDRAM memory unit for caching; for data with an input clock slower than an output clock, the image data is selectively stored in the internal FIFO.
In step 2, when data in two interface formats are converted, buffering needs to be performed through FIFO or DDR3SDRAM due to inconsistency of front and rear clocks;
when the FIFO constructed by BRAM resources in the FPGA is used for caching, the input and output time sequence of the FPGA is operated completely according to the FIFO clock domain crossing mode;
when caching is carried out according to DDR3SDRAM, two pieces of DDR3SDRAM are needed to carry out ping-pong operation, and data conversion of different protocol formats is completed; namely, when one frame of image is written into DDR3SDRAM 1, the last frame of data is read out from DDR3SDRAM 2 at the same time; when the next frame image is written into the DDR3SDRAM 2, the last frame data is read out from the DDR3SDRAM 1 at the same time, and in this way, the data delay time is one frame data time.
In the working mode of step 3, the maximum bandwidth of the input end is 6.25Gbps, and the maximum bandwidth of the output end is 6.8Gbps, so that the bandwidth of the whole channel is 6.25 Gbps.
Example 1
The embodiment aims to solve the problem of mutual conversion between two interfaces, namely CoaXPress and Cameralink, and realize interconnection and intercommunication and real-time transmission between different interface devices. The Xilinx Kintex-7 series FPGA is used as a main control logic element to carry out logic control on receiving and sending between the two interfaces. The CoaXPress decoding chip is responsible for converting and receiving LVDS data into parallel data, and the CoaXPress coding chip is responsible for converting and sending the parallel data into LVDS serial data; the Cameralink decoding chip is responsible for converting and receiving LVDS data into parallel data, and the Cameralink coding chip is responsible for converting and sending the parallel data into LVDS serial data. The invention can realize the conversion from CoaXPress interface input data to Cameralink interface output data, or the conversion from Cameralink interface input data to CoaXPress interface output data, or the bidirectional independent transmission of the two interfaces. Infrared images with 640 × 512 resolutions at 1000 frames per second can be transmitted in real time, calculated at a maximum data throughput of 6.25 Gbps.
With reference to fig. 1 and 4, when the function of the Cameralink input interface is changed to the CoaXPress output interface, the Cameralink interfaces 1 and 2 are connected to form a Cameralink Full input mode. LVDS differential data is input through a Cameralink interface, two Cameralink decoding receiving driving chips complete conversion from serial data to parallel data, meanwhile, FPGA main control logic caches the data into FIFO 1 or DDR3SDRAM, and the writing clock is a pixel clock of the Cameralink. And then the FPGA main control logic reads the data from the cache, packs the data according to the format of a CoaXPress protocol, adds head and tail information, sends the data to a CoaXPress coding chip to carry out 8b/10b coding and balancing, and sends the data to a CoaXPress connector Micro BNC 1 in the form of LVDS. When the function is used, the maximum bandwidth of the input end is 6.8Gbps, and the maximum bandwidth of the output end is 6.25Gbps, so that the bandwidth of the whole channel is 6.25 Gbps.
With reference to fig. 1, when the CoaXPress input interface is converted into the Cameralink output interface, the Cameralink interfaces 3 and 4 are plugged to form a Cameralink Full output mode. LVDS differential data is input through a CoaXPress interface Micro BNC 2, the CoaXPress decoding receiving driving chip completes the conversion from serial data to parallel data, the head and the tail are removed according to a CoaXPress protocol, image data are extracted, the data are cached in FIFO 2 or DDR3SDRAM, and the writing clock of the data is the pixel clock of CoaXPress. And then the FPGA main control logic reads the data from the cache, packs the data according to the line field format of the Cameralink protocol, sends the data to two Cameralink sending chips for coding, and sends the data to the Cameralink connector Cameralink interfaces 3 and 4 in the form of LVDS. When the function is used, the maximum bandwidth of the input end is 6.25Gbps, and the maximum bandwidth of the output end is 6.8Gbps, so that the bandwidth of the whole channel is 6.25 Gbps.
Referring to fig. 2, when data in two interface formats are converted, the data need to be buffered by FIFO or DDR3SDRAM due to the inconsistency of front and back clocks. The FIFO constructed by BRAM resources in the FPGA is used for buffering, and the input and output time sequence of the FPGA is operated completely according to the FIFO clock domain crossing mode. When caching is carried out according to DDR3SDRAM, two pieces of ping-pong operation are needed to complete data conversion of different protocol formats. When one frame of image is written into DDR3SDRAM 1, reading the last frame of data from DDR3SDRAM 2 at the same time; when the next frame image is written in the DDR3SDRAM 2, the last frame data is read out from the DDR3SDRAM 1 at the same time. In this way, the data delay time is one frame data time.
With reference to fig. 3, after the system is started, the input/output interface mode of the system can be selected by using the RS232 serial port, the system is provided with typical 4 video formats, and after the typical format is selected, the system performs conversion according to the format. For the unusual video formats, the input and output clocks, the resolution, the working time sequences of two interfaces and the like of the unusual video formats can be configured through the serial ports, sent to the FPGA, and then the corresponding working modes are started. The communication mode of the RS232 serial port is 115200 baud rate, 8bit of data bit and even check.
Example 2
The embodiment provides a method for interconversion between a Cameralink data interface and a CoaXpress data interface, which comprises the following steps:
step 1: the upper computer software configures the conversion mode through RS 232;
step 2: converting the Cameralink interface data into CoaXPress interface data;
and step 3: the CoaXPress interface data is converted into Cameralink interface data.
Wherein the step 1 comprises the sub-steps of:
the whole system adopts direct current 5V power supply. After the system supplies power, the upper computer software communicates with the FPGA through an RS232 serial port, and the RS232 adopts a DB9 connector. Configuring the input and output flow direction of data on an upper computer interface, selecting CoaXPress as an input interface and Cameralink as an output interface, and setting a working mode to convert CoaXPress into Cameralink; and selecting Cameralink as an input interface and CoaXPress as an output interface, and setting the working mode to convert the Cameralink into the CoaXPress. The input interface is configured with a clock and the output interface is configured with an output clock, so that data with different rates can be converted between two kinds of decoupling. The data interface conversion system is internally provided with a typical video format working mode, can be matched with an input/output interface mode in a self-adaptive manner, and realizes seamless butt joint and input/output; for the unusual working mode, the specific working mode of the system can be configured through the upper computer.
Wherein the step 2 comprises the sub-steps of:
2.1 using a Cameralink interface and a corresponding receiving driving chip thereof to convert LVDS serial data into parallel data and transmit the parallel data to a main control element FPGA, and extracting image data from a line-field time sequence by the FPGA according to a Cameralink protocol for the input data. For data with an input clock faster than an output clock, image data is stored in an external DDR3SDRAM storage unit for caching; for data with input clock slower than output clock, selecting to store image data into internal FIFO;
2.2, inputting data with a clock faster than an output clock, and reading the data after an external DDR3SDRAM finishes caching an image; the data with the input clock slower than the output clock can be read out after the internal FIFO buffers one line, and the data is delayed to be the time of one line of data. The read cache data packs the image data into a data packet form according to a CoaXPress protocol, adds a head part and a tail part, transmits the data packet to a CoaXPress coding transmission driver chip, and finally transmits the data packet outwards in a serial LVDS form;
2.3 for Camerlink input to CoaXPress output, the core of the invention is that the invention can carry out self-adaptive matching according to different clock rates, and complete automatic conversion of different rates. According to the difference between a Camerlink input clock and a CoaXPress output clock, an internal clock matching scheme is automatically completed, the FIFO cache in the FPGA is adopted to realize the delay of a pixel clock stage between two interfaces, and the conversion from a slow clock to a fast clock is completed; the external DDR3SDRAM is adopted to realize the caching of an image and complete the conversion from a fast clock to a slow clock; the maximum bandwidth of input data is 6.8 Gbps.
Wherein the step 3 comprises the following substeps:
3.1 use CoaXPress interface and its corresponding receive the driver chip, change LVDS serial data into parallel data and transmit to main control element FPGA, analyze its head and afterbody according to CoaXPress agreement to the data of input by FPGA, extract image data. For data with an input clock faster than an output clock, image data is stored in an external DDR3SDRAM storage unit for caching; for data with input clock slower than output clock, selecting to store image data into internal FIFO;
3.2, inputting data with a clock faster than an output clock, and reading the data after an image is cached by an external DDR3 SDRAM; the data with the input clock slower than the output clock can be read out after the internal FIFO buffers one line, and the data is delayed to be the time of one line of data. The read cache data are transmitted to a Cameralink coding transmission driver chip according to the requirements of the Cameralink interface line field time sequence, and are finally transmitted outwards in a serial LVDS mode;
3.3 converting CoaXPress input to Camerlink output, the core of the invention is that the invention can carry out self-adaptive matching according to different clock rates, and complete automatic conversion of different rates. According to the difference between the CoaXPress input clock and the Camerlink output clock, an internal clock matching scheme is automatically completed, the FIFO cache in the FPGA is adopted to realize the delay of a pixel clock stage between two interfaces, and the conversion from a slow clock to a fast clock is completed; the external DDR3SDRAM is adopted to realize the caching of an image and complete the conversion from a fast clock to a slow clock; the maximum bandwidth of the input data is 6.25 Gbps.
In the data interface conversion system, a main element FPGA of conversion logic adopted by a conversion system for converting CoaXPress into Cameralink data interface adopts Xilinx XC7K325T to realize logic time sequence control of the two interfaces; the CoaXPress receiving and decoding chip adopts a CoaXPress2.0 chip EQCO125X40 of Microchip company to realize serial-parallel conversion of high-speed LVDS data, and the interface connector adopts Micro BNC; the Cameralink coding transmission chip adopts two DS90CR287 chips of National Semiconductor company to form a Cameralink Full mode, so that conversion from parallel data to serial LVDS data is realized, and the interface connector adopts two SDRs 26.
In the data interface conversion system, a main element FPGA of a data interface conversion logic of Cameralink conversion CoaXPress adopts the same FPGA with the functions to realize logic time sequence control of two interfaces; the Cameralink codec receiving chip adopts two DS90CR288 chips of National Semiconductor company to form a Cameralink Full mode, so that the conversion from serial LVDS data to parallel data is realized, and the interface connector adopts two paths of SDRs 26; CoaXPress coding transmission chip adopts CoaXPress2.0 chip EQCO125X40 of Microchip company, realizes parallel data to LVDS data's conversion, the interface connector adopts Micro BNC.
Example 3
The embodiment provides a method for interconversion between high-speed CoaXPress interface data and high-speed Cameralink interface data, which comprises the following steps:
step 1: the upper computer software configures the conversion mode through RS 232;
step 2: converting the Cameralink interface data into CoaXPress interface data;
and step 3: the CoaXPress interface data is converted into Cameralink interface data.
Wherein the step 1 comprises the following substeps:
1.1 after the system is powered on, starting the upper computer software, and communicating with the FPGA through RS 232;
1.2 configuring the input and output flow direction of data, and selecting a corresponding interface;
1.3 for typical video formats, directly starting the working mode;
1.4 setting the pixel clock, the resolution and the working time sequence of the unusual video format, and then starting the working mode;
wherein the step 2 comprises the following substeps:
2.1, converting LVDS image data into parallel data and transmitting the parallel data to a main control element FPGA by using a Cameralink interface and a corresponding receiving driving chip thereof, and selectively storing the real-time image data into an internal FIFO or an external DDR3SDRAM for caching by the FPGA according to different input and output clocks;
2.2 after reading a line of data from FIFO or reading an image of data from DDR3SDRAM, packing the data according to the CoaXPress interface timing sequence, transmitting the packed data to a CoaXPress coding transmission driver chip, and finally transmitting the packed data outwards in the form of LVDS;
2.3 in order to realize the time sequence self-adaptive matching between different input and output clocks, when the input clock is faster than the output clock, a DDR3SDRAM is adopted to realize the caching of an image, and then the output is carried out; when the input clock is slower than the output clock, a line of data is cached by adopting FIFO in the FPGA, and then the output can be carried out.
Wherein the step 3 comprises the following substeps:
3.1 using CoaXPress interface and corresponding receiving drive chip to convert LVDS data into parallel data and transmit the parallel data to the main control element FPGA, analyzing the data according to CoaXPress protocol, and storing real-time image data into internal FIFO or external DDR3SDRAM for caching by FPGA selection according to the difference of input and output clocks;
3.2 after reading out a line of data from FIFO or reading out an image of data from DDR3SDRAM, the FPGA transmits the parallel data to a Cameralink coding transmission driver chip according to the time sequence requirement of a Cameralink interface, and finally transmits the parallel data outwards in the form of LVDS;
3.3 in order to realize the self-adaptive matching of the time sequences of different input and output clocks, when the input clock is faster than the output clock, a DDR3SDRAM is adopted to realize the caching of an image, and then the output is carried out; when the input clock is slower than the output clock, a line of data is cached by adopting FIFO in the FPGA, and then the output can be carried out;
the main element FPGA for data interface conversion adopts Xilinx XC7K325T to realize logic control of different interface time sequences; the CoaXPress receiving and decoding chip adopts a CoaXPress2.0 chip EQCO125X40 of the first product of Microchip company to realize serial-parallel conversion of high-speed LVDS data, and the interface adopts Micro BNC; the Cameralink coding transmission chip adopts two DS90CR287 chips of National Semiconductor company to form a Cameralink Full mode, so that conversion from parallel data to serial LVDS data is realized, and the interface adopts two SDR26 paths.
The main element FPGA for data interface conversion adopts the same FPGA as the main element FPGA in claim 3 to realize logic control of different interface time sequences; the Cameralink codec receiving chip adopts two DS90CR288 chips of National Semiconductor company to form a Cameralink Full mode, so that the conversion from serial LVDS data to parallel data is realized, and the interface adopts two SDR26 paths; CoaXPress coding transmission chip adopts CoaXPress2.0 chip EQCO125X40 of Microchip company, realizes the conversion of parallel data to LVDS data, the interface adopts Micro BNC.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A method for interconversion between CoaXPress interface data and Cameralink interface data, the method being implemented based on a data interface conversion system, the data interface conversion system comprising: the device comprises a Cameralink interface, a Cameralink decoding driving chip, a Cameralink coding driving chip, a main control element FPGA, a CoaXPress interface, a CoaXPress coding driving chip and a CoaXPress decoding driving chip;
the method comprises the following steps:
step 1: the upper computer software configures the converted working mode through RS 232;
step 2: converting the Cameralink interface data into CoaXPress interface data;
and step 3: the CoaXPress interface data is converted into Cameralink interface data.
2. The method for interconversion between CoaXPress interface data and Cameralink interface data as claimed in claim 1, wherein in step 1, the whole system is powered by DC 5V; after the system is powered on, the upper computer software is communicated with the FPGA through an RS232 serial port, and the DB9 connector is adopted as the RS232 serial port;
configuring the input and output flow direction of data on an upper computer interface; when the Cameralink is selected as an input interface and CoaXPress is selected as an output interface, setting a working mode that the Cameralink interface data is converted into CoaXPress interface data; when CoaXPress is selected as an input interface and Cameralink is selected as an output interface, the working mode is set to convert CoaXPress interface data into Cameralink interface data.
3. The method for interconversion of CoaXPress interface data and Cameralink interface data as claimed in claim 1, wherein said step 2 comprises the sub-steps of:
step 21: under the condition that the working mode is that the Cameralink interface data is converted into CoaXPress interface data, a Cameralink interface and a Cameralink decoding receiving driving chip are used for converting LVDS serial data into parallel data and transmitting the parallel data to a main control element FPGA, and the main control element FPGA extracts image data from a line field time sequence of the input parallel data according to a Cameralink protocol; then, the data is buffered in an internal FIFO or an external DDR3SDRAM, and the writing clock of the data is the pixel clock of Cameralink;
step 22: for image data with an input clock faster than an output clock, the external DDR3SDRAM can read out the image data after finishing caching the image data;
for image data with an input clock slower than an output clock, the image data can be read out after one line of data is cached by an internal FIFO, and the data delay is the time of one line of data;
the main control element FPGA packs the read cache data into a data packet form according to a CoaXPress protocol, adds a head part and a tail part, transmits the data packet to a CoaXPress coding driving chip, and finally transmits the data packet outwards through a CoaXPress interface in a serial LVDS form.
4. The method for interconversion of CoaXPress interface data and Cameralink interface data as claimed in claim 3, wherein in said step 21, for image data with faster input clock than output clock, selecting to store the image data in external DDR3SDRAM memory unit for buffering; and for image data with an input clock slower than an output clock, selecting to store the image data into an internal FIFO of the main control element FPGA.
5. The method for converting CoaXPress interface data and Cameralink interface data into each other as claimed in claim 4, wherein in step 2, when data in two interface formats are converted, it needs to be buffered by FIFO or DDR3SDRAM due to the inconsistency of front and back clocks;
when the FIFO constructed by BRAM resources in the FPGA is used for caching, the input and output time sequence of the FPGA is operated completely according to the FIFO clock domain crossing mode;
when caching is carried out according to DDR3SDRAM, two pieces of DDR3SDRAM are needed to carry out ping-pong operation, and data conversion of different protocol formats is completed; namely, when one frame of image is written into the DDR3SDRAM 1, the last frame of data is read out from the DDR3SDRAM 2 at the same time; when the next frame image is written into the DDR3SDRAM 2, the last frame data is read out from the DDR3SDRAM 1 at the same time, and in this way, the data delay time is one frame data time.
6. The method for interconversion of CoaXPress interface data and Cameralink interface data as claimed in claim 4, wherein in said step 2 operating mode, the maximum bandwidth of the input terminal is 6.8Gbps, and the maximum bandwidth of the output terminal is 6.25Gbps, so that the bandwidth of the whole channel is 6.25 Gbps.
7. The method for interconversion of CoaXPress interface data and Cameralink interface data as claimed in claim 1, wherein said step 3 comprises the sub-steps of:
step 31: under the condition that the working mode is that CoaXPress interface data is converted into Cameralink interface data, a CoaXPress interface and a CoaXPress decoding driving chip thereof are used for converting LVDS serial data into parallel data and transmitting the parallel data to a main control element FPGA, the main control element FPGA analyzes input image data according to a CoaXPress protocol to remove the head and the tail of the input image data, and the image data are extracted; then, the data is cached in an internal FIFO (first in first out) or an external DDR3SDRAM (synchronous dynamic random access memory) of a main control element FPGA (field programmable gate array), and the writing clock of the data is a pixel clock of CoaXPres;
step 32: for image data with an input clock faster than an output clock, the external DDR3SDRAM can read out after finishing caching an image;
for data with an input clock slower than an output clock, the data can be read out after the internal FIFO buffers one line, and the data is delayed to be the time of one line of data;
and the read cache data is transmitted to a Cameralink coding driving chip according to the requirements of the line field time sequence of the Cameralink interface, and finally is transmitted to the outside through the Cameralink interface in a serial LVDS mode.
8. The method for interconversion of CoaXPress interface data and Cameralink interface data as claimed in claim 7, wherein in said step 32, for data with faster input clock than output clock, selecting to store image data into external DDR3SDRAM memory location for buffering; for data with an input clock slower than an output clock, the image data is selectively stored in the internal FIFO.
9. The method as claimed in claim 7, wherein in step 2, when the data in the two interface formats are converted, the data need to be buffered by FIFO or DDR3SDRAM due to the inconsistency of the front and rear clocks;
when the FIFO constructed by BRAM resources in the FPGA is used for caching, the input and output time sequence of the FPGA is operated completely according to the FIFO clock domain crossing mode;
when caching is carried out according to DDR3SDRAM, two pieces of DDR3SDRAM are needed to carry out ping-pong operation, and data conversion of different protocol formats is completed; namely, when one frame of image is written into the DDR3SDRAM 1, the last frame of data is read out from the DDR3SDRAM 2 at the same time; when the next frame image is written into the DDR3SDRAM 2, the last frame data is read out from the DDR3SDRAM 1 at the same time, and in this way, the data delay time is one frame data time.
10. The method for interconversion between CoaXPress interface data and Cameralink interface data of claim 7, wherein in the step 3 mode of operation, the maximum bandwidth of the input port is 6.25Gbps, and the maximum bandwidth of the output port is 6.8Gbps, so that the bandwidth of the whole channel is 6.25 Gbps.
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