CN115061967A - Method for reducing interface clock by using homemade FPGA (field programmable Gate array) based camera link image compression - Google Patents
Method for reducing interface clock by using homemade FPGA (field programmable Gate array) based camera link image compression Download PDFInfo
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Abstract
The scheme belongs to the technical field of electronics, and particularly relates to a method for reducing an interface clock by using homemade FPGA (field programmable gate array) based camera link image compression. The method comprises the following steps: the method comprises the following steps: the camera alink interface collects 14bit and 8bit infrared images and converts the images into camera alink signals; step two: the Cameralink interface module receives the Cameralink signal and sends the Cameralink signal to the Cameralink decoding module; step three: the Cameralink decoding module decodes the Cameralink signal and sends the decoded parallel digital image signal to the serial-parallel signal conversion module; and the serial-to-parallel signal conversion module converts the serial signals input by the camera link interface into parallel data according to time sequence and logic. According to the scheme, the 14-bit and 8-bit pixels are mixed in one pixel period, so that the pixel clock of the interface is reduced, the requirement of an image processing algorithm can be met by earlier camera link interface equipment with higher precision of more than 14 bits, and the cost of replacing the camera link interface is avoided.
Description
Technical Field
The scheme belongs to the technical field of electronics, and particularly relates to a method for reducing an interface clock by using a homemade FPGA (field programmable gate array) based camera alink image compression.
Background
The CameraLink interface is widely used in a high-performance machine vision system and mainly comprises the fields of industrial production, security monitoring, military video acquisition and display and the like. The definition of the video interface capable of being freely configured greatly enhances the flexibility of the CameraLink interface, and customized video products based on the CameraLink interface continuously appear.
The high-definition video has huge information content, which brings huge pressure to video transmission, and the CameraLink and other high-speed interfaces are only used for short-distance transmission between the video acquisition equipment and the video processing equipment. In long-distance transmission, the high video bandwidth brings a huge increase in cost, so that the video is generally compressed first in long-distance transmission.
The patent with the application number of CN107509036A discloses a massive image compression method for a camera based on an FPGA, wherein the FPGA is directly connected with an image sensor of the camera, and the image sensor outputs a field synchronization signal V, a line synchronization signal H, a pixel clock CLK and pixel data D; the FPGA is connected with a memory, an image compression marking matrix F is stored in the memory, the dimension of the F is w x h, w is the width of an acquired image, h is the height of the acquired image, the value ranges of w and h are 1-100000, and the value of an element in the F is 0 or 1; the FPGA takes a pixel clock CLK as an image compression driving clock, counts the number of input pixels according to a field synchronizing signal V and a line synchronizing signal H, and calculates the image coordinates (i, j) of the current pixel P according to the number of the input pixels, wherein the value range of i is 0-w-1, and the value range of j is 0-H-1; the FPGA reads the (i, j) th element in the image compression mark matrix F in the memory: f (i, j), when F (i, j) is 0, the current pixel P is not sampled, when F (i, j) is 1, the current pixel P is sampled, wherein the starting coordinate of the element in F is (0, 0); after completing the compression of a line of image, storing the current line of compressed image into a memory; and sequentially completing the pixel compression of the h lines of images to obtain a compressed image.
The method can be used for rapidly compressing mass images of industrial cameras and high-speed cameras. But the current high-precision thermal infrared imager can generally reach 14 bits or higher precision so as to meet the requirements of image processing algorithms. However, the pixel bit width of the single-path image of the early camera alink interface is 28 bits, and for the commonly used infrared detector, the pixel bit width is commonly 14 bits and 8 bits, so that the camera alink interface device cannot realize higher precision of more than 14 bits to meet the requirement of an image processing algorithm, and if the camera alink interface is replaced to realize a higher-precision image, the manufacturing cost will be increased.
Disclosure of Invention
The scheme provides a method for reducing an interface clock by using the homemade FPGA-based camera link image compression, which realizes a high-precision image by using an early camera link interface.
In order to achieve the above purpose, the present scheme provides a method for reducing an interface clock by compressing a camera link image based on a domestic FPGA, comprising the following steps:
the method comprises the following steps: a camera link interface of the infrared camera collects 14bit and 8bit infrared images and converts the images into camera link signals;
step two: the Cameralink interface module receives the Cameralink signal and sends the Cameralink signal to the Cameralink decoding module;
step three: the Cameralink decoding module decodes the Cameralink signal and sends the decoded parallel digital image signal to the serial-parallel signal conversion module; the serial-to-parallel signal conversion module converts serial signals input by the camera link interface into parallel data according to time sequence and logic,
step four: analyzing the time sequence of the Cameralink pixel data by adopting a time sequence analysis module;
step five: an AXI interface module is adopted to store data time sequence into a cache asynchronous FIFO;
step six: the asynchronous FIFO data buffer module buffers the image data according to the system clock and synchronously outputs the image data across clock domains,
step seven: the asynchronous FIFO data caching module receives the 14bit and 8bit camera link pixel data time sequences, mixes the 14bit and 8bit camera link pixel data time sequences to be used as a writing input clock of the FIFO, and respectively writes the image data into the two FIFOs according to odd lines and even lines; wherein the odd rows comprise 14bit +8bit, and the even rows comprise 14bit and 8 bit; and reading image data, and generating new line, field and image signals according to the line and field control signals of the input image to finish the caching and clock domain crossing of the image data.
The principle of the scheme is as follows: the asynchronous FIFO data buffer module receives a timing sequence of the camera link pixel data after the 14bit and 8bit are mixed as a write input clock of the FIFO, the image data is respectively written into the two FIFOs according to odd lines and even lines, the data is read at the rising edge or the falling edge of each clock signal, and then 14bit and 8bit are read at each signal clock.
The beneficial effect of this scheme:
(1) according to the scheme, the 14-bit and 8-bit pixels are mixed in one pixel period, so that the pixel clock of the interface is reduced, the requirement of an image processing algorithm can be met by earlier camera link interface equipment with higher precision of more than 14 bits, and the cost of replacing the camera link interface is avoided.
(2) After pixel mixing, the clock of the pixels of the camera alink interface is reduced from 80Mhz to 40MHZ, and the efficiency is improved.
Further, in the fourth step, the FPGA chip is connected to the serial-to-parallel signal conversion module through a selecto interface; the selecto interface is used for inputting the timing sequence of the cameralink pixel data and outputting the timing sequence of the cameralink pixel data through channellink. The coding speed is adjusted, and the coding efficiency is improved, so that the purpose of coding is achieved.
Further, in the fifth step, the AXI interface module uses an asynchronous handshake mechanism to transfer the rising edge rxfvalbegegegeggin and the falling edge rxfvalend of the field effective signal across the clock domain; respectively making a selecto signal as a sending or receiving Start on the rising edge of each clock signal of a system clock, sequentially sending a selecto _ tx output time sequence at the rxfvelbegin clock signal rising edge of each FPGA based on a packet structure, sending a selecto _ tx output time sequence at a Cameralink output end according to a beat, searching a starting Start, recovering a Payload and checking and finishing the LAST at a Cameralink receiving end according to the beat of the selecto _ rx input time sequence. Start by setting lookup, resume Payload, and check, end of LAST. When data is transmitted from a transmitting end to a receiving end, the data is transmitted to a register at the same time, when all the data is transmitted to the receiving end, a data sampling processing module, a time sequence analysis module and an AXI interface module in the register module analyze all the received data to judge whether a data packet is lost, the possibility of losing the data packet possibly occurs under the condition of external signal interference of large current or strong current, and when the data packet is lost, the transmitting end retransmits image data and a camera serial communication signal in a Cameralink interface to the receiving end, so that the accuracy of image transmission is higher.
Further, in the seventh step, when reading the image, the data is read only when the falling edge (or the rising edge) of the pixel clock comes. To ensure the correctness of the read data.
Further, in the seventh step, a register configuration module is adopted to enable the data sampling processing module, the time sequence analysis module and the AXI interface module to work according to corresponding parameters.
Further, in the seventh step, the time sequence is received and sent and the time sequence is sent through a serial port.
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FIG. 1 is a schematic diagram of the embodiment of the invention before mixing of 14-bit and 8-bit pixels.
FIG. 2 is a diagram illustrating a mixture of 14-bit and 8-bit pixels according to an embodiment of the present invention.
Detailed Description
The following is further detailed by way of specific embodiments:
the embodiment is basically as shown in the attached figures 1-2:
a method for reducing an interface clock by using homemade FPGA (field programmable gate array) based camera link image compression comprises the following steps:
the method comprises the following steps: a camera link interface of the infrared camera collects 14bit and 8bit infrared images and converts the images into camera link signals;
step two: the Cameralink interface module receives the Cameralink signals of 14 bits and 8 bits and sends the Cameralink signals to the Cameralink decoding module;
step three: the Cameralink decoding module decodes the 14bit and 8bit Cameralink signals and sends the decoded parallel digital image signals to the serial-parallel signal conversion module; the serial-to-parallel signal conversion module converts serial signals input by the camera link interface into parallel data according to time sequence and logic,
step four: analyzing the time sequence of the Cameralink pixel data by adopting a time sequence analysis module; the FPGA chip is connected with the serial-parallel signal conversion module through a selecto interface; the selecto interface is used for inputting the timing sequence of the cameralink pixel data and outputting the timing sequence of the cameralink pixel data through channellink. The coding speed is adjusted, and the coding efficiency is improved, so that the purpose of coding is achieved.
Step five: an AXI interface module is adopted to store data time sequence into a cache asynchronous FIFO; the AXI interface module adopts an asynchronous handshake mechanism and transfers a rising edge rxfvalbegegin and a falling edge rxfvalend of a field effective signal across a clock domain; respectively making a selecto signal as a sending or receiving Start on the rising edge of each clock signal of a system clock, sequentially sending a selecto _ tx output time sequence at the rxfvelbegin clock signal rising edge of each FPGA based on a packet structure, sending a selecto _ tx output time sequence at a Cameralink output end according to a beat, searching a starting Start, recovering a Payload and checking and finishing the LAST at a Cameralink receiving end according to the beat of the selecto _ rx input time sequence. Start by setting lookup, resume Payload, and check, end of LAST. When data is transmitted from a transmitting end to a receiving end, the data is transmitted to a register at the same time, when all the data is transmitted to the receiving end, a data sampling processing module, a time sequence analysis module and an AXI interface module in the register module analyze all the received data to judge whether a data packet is lost, the possibility of data packet loss possibly occurs under the condition of external signal interference of large current or strong current, and when the data packet is lost, the transmitting end retransmits image data and a camera serial communication signal in a Cameralink interface to the receiving end, so that the accuracy of image transmission is higher.
Step six: the asynchronous FIFO data buffer module buffers the image data according to the system clock and synchronously outputs the image data across clock domains,
step seven: the asynchronous FIFO data caching module receives 14bit and 8bit camera link pixel data time sequences, mixes the 14bit and 8bit camera link pixel data time sequences to be used as a writing input clock of the FIFO, and respectively writes the image data into two FIFOs according to odd lines and even lines; wherein the odd rows comprise 14bit +8bit, and the even rows comprise 14bit and 8 bit; and reading image data, and generating new line, field and image signals according to the line and field control signals of the input image to finish the caching and clock domain crossing of the image data. And the register configuration module is adopted to enable the data sampling processing module, the time sequence analysis module and the AXI interface module to work according to corresponding parameters.
The foregoing is merely an example of the present invention and common general knowledge of known specific structures and features of the embodiments is not described herein in any greater detail. It should be noted that, for those skilled in the art, without departing from the structure of the present invention, several changes and modifications can be made, which should also be regarded as the protection scope of the present invention, and these will not affect the effect of the implementation of the present invention and the practicability of the patent. The scope of the claims of the present application shall be determined by the contents of the claims, and the description of the embodiments and the like in the specification shall be used to explain the contents of the claims.
Claims (6)
1. The method for reducing the interface clock by the image compression of the camera alink based on the domestic FPGA is characterized by comprising the following steps: the method comprises the following steps:
the method comprises the following steps: a camera link interface of the infrared camera collects 14bit and 8bit infrared images and converts the images into camera link signals;
step two: the Cameralink interface module receives the Cameralink signal and sends the Cameralink signal to the Cameralink decoding module;
step three: the Cameralink decoding module decodes the Cameralink signal and sends the decoded parallel digital image signal to the serial-parallel signal conversion module; the serial-to-parallel signal conversion module converts serial signals input by the camera link interface into parallel data according to time sequence and logic,
step four: analyzing the time sequence of the Cameralink pixel data by adopting a time sequence analysis module;
step five: an AXI interface module is adopted to store data time sequence into a cache asynchronous FIFO;
step six: the asynchronous FIFO data buffer module buffers the image data according to the system clock and synchronously outputs the image data across clock domains,
step seven: the asynchronous FIFO data caching module receives the 14bit and 8bit camera link pixel data time sequences, mixes the 14bit and 8bit camera link pixel data time sequences to be used as a writing input clock of the FIFO, and respectively writes the image data into the two FIFOs according to odd lines and even lines; wherein the odd rows comprise 14bit +8bit, and the even rows comprise 14bit and 8 bit; and reading image data, and generating new line, field and image signals according to the line and field control signals of the input image to finish the caching and clock domain crossing of the image data.
2. The method for reducing interface clock based on homemade FPGA camera alink image compression as claimed in claim 1, wherein: in the fourth step, the FPGA chip is connected with the serial-parallel signal conversion module through a selecto interface; the selecto interface is used for inputting the timing sequence of the cameralink pixel data and outputting the timing sequence of the cameralink pixel data through channellink.
3. The method for reducing interface clock based on homemade FPGA camera alink image compression as claimed in claim 1, wherein: in the fifth step, the AXI interface module adopts an asynchronous handshake mechanism to transfer a rising edge rxfvalbegegegin and a falling edge rxfvalend of the field effective signal across the clock domain; respectively making a selecto signal as a sending or receiving Start on the rising edge of each clock signal of a system clock, sequentially sending a selecto _ tx output time sequence at the rxfvelbegin clock signal rising edge of each FPGA based on a packet structure, sending a selecto _ tx output time sequence at a Cameralink output end according to a beat, searching a starting Start, recovering a Payload and checking and finishing the LAST at a Cameralink receiving end according to the beat of the selecto _ rx input time sequence.
4. The method for reducing interface clock based on homemade FPGA camera alink image compression as claimed in claim 1, wherein: in the seventh step, when reading the image, the data is read only when the falling edge or the rising edge of the pixel clock comes.
5. The method for reducing interface clock based on homemade FPGA camera alink image compression as claimed in claim 1, wherein: and seventhly, enabling the data sampling processing module, the time sequence analysis module and the AXI interface module to work according to corresponding parameters by adopting a register configuration module.
6. The method for reducing interface clock based on homemade FPGA camera alink image compression as claimed in claim 1, wherein: and step seven, receiving and sending the time sequence and the sending time sequence through the serial port.
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