CN111314645A - Camera Link interface signal decoding method based on FPGA - Google Patents

Abstract

The invention discloses a Camera Link interface signal decoding method based on FPGA, which comprises the following steps: firstly, converting a clock differential signal transmitted by a Camera Link interface under any configuration into a single-ended pixel clock signal, then converting a data differential signal transmitted by the Camera Link interface under any configuration into a single-ended data signal, decoding the single-ended data signal into a 28-bit parallel data signal according to a data bit width conversion ratio of 1:7, arranging and recombining the 28-bit parallel data signal, then outputting the data signal to the outside as a video control signal and a pixel signal of a TTL level, and finally outputting the video to the outside in an HDMI/VGA format under corresponding resolution. The method simplifies hardware design and has the advantages of small system volume, low cost, strong adjustability and good transportability.

Description

Camera Link interface signal decoding method based on FPGA

Technical Field

The invention relates to the technical field of machine vision, Camera Link interface transmission protocols and FPGA logic development, in particular to a method for decoding signals of a Camera Link interface based on an FPGA.

Background

The Camera Link interface is a relatively common data transmission interface applied to an industrial Camera in the machine vision industry, is developed by a Channel Link technical standard proposed by national Semiconductor laboratories (national Semiconductor), has an open interface protocol, and is characterized in that low-voltage differential signal LVDS transmission is used in signal transmission. LVDS is a data transmission and interface technology appearing in the 90 s of the 20 th century, which adopts a low voltage differential signal transmission mode, and the core technology is to adopt a very low voltage swing to complete high speed differential signal transmission, to realize point-to-point or point-to-multipoint signal transmission, and has the advantages of low power consumption, low error rate, low crosstalk and low radiation, and can maintain a high transmission rate.

The field Programmable logic device fpga (field Programmable Gate array) is a new type of digital logic device developed in the last decade, and is a basic device for designing modern complex digital electronic systems. Due to the advantages of easy use and low cost of FPGAs, FPGAs are currently widely used in the field of image transmission and data communication. Currently, a Camera Link signal receiving method based on an FPGA adopts a professional Channel Link decoding chip at the front end of the FPGA, such as classical Channel Link to TTL/CMOS chips DS90CR28, DS90CR288, and the like, to convert LVDS differential signals into corresponding TTL data signals. However, the Camera Link interface has three modes, namely Base, Medium and Full, and the number of Channel Link decoding chips required in different configuration modes is also different, for example, the Full mode has 8 pixel channels, 3 professional Channel Link decoding chips are required, and at most 8 pixels can be output in each clock cycle. A single Channel Link chip, such as DS90CR288, has 56 pins in total, and is responsible for converting 4 pairs of data differential signals into 24-bit data signals and 4-bit video control signals, so that the Camera Link interface signals in Full mode have 64-bit data signals and 4-bit video control signals in total after conversion using three dedicated Channel Link decoding chips, while 3 Channel Link decoding chips have 168 pins in total. Similarly, the Medium mode of Camera Link has 6 pixel channels, and requires 2 professional Channel Link decoding chips, and there are 112 pins in total, even if there are only 3 pixel channels in the simplest Base mode, and 1 professional Channel Link decoding chip is required, there are 56 pins. It can be seen from the above that the method of processing the Camera Link interface signal by adopting the professional Channel Link decoding chip will cause difficulties in designing the receiving end and realizing size miniaturization on the front end layout of the FPGA.

Currently, most FPGAs under the Xilinx flag have built-in one or more MGT (Multi-Gigabit transceiver), also known as SERDES (Multi-Gigabit Serializer/Deserializer). The SERDES internally comprises a high-speed serial-parallel conversion circuit, a clock data recovery circuit, a data coding and decoding circuit, a clock correction circuit and a channel binding circuit, and provides a physical layer basis for various high-speed serial data transmission protocols. SERDES is an abbreviation for serializer and deserializer. The functions supported by the SERDES mainly include:

(1) special serial-to-parallel converter: the SERDES can be used as a deserializer to realize serial-parallel conversion of data and support high-speed serial data transmission. The deserializer supports two modes, Single Data Rate (SDR) and Double Data Rate (DDR).

(2) The Bitslip submodule: the Bitslip submodule allows parallel data entering the interior of the FPGA to be reordered for word alignment.

(3) DDR3 and QDR storage interfaces are supported.

The method for converting the Camera Link video at any resolution into the SDI video is realized in the patent CN 109194928A, wherein a DS90CR286 decoding chip is adopted in the video decoding unit chip to process the Camera Link interface signal. An FPGA-based Camera Link interface experimental development system is designed in patent CN 103763549a, wherein a DS90CR287 decoding chip is adopted in an image signal transmission unit to decode a Camera Link interface signal. The video decoding methods have the defects of complex hardware structure design, complex spatial layout, heavy front-end wiring pressure, poor decoding real-time performance, poor program portability, low use flexibility and poor universality.

Disclosure of Invention

The invention aims to provide a Camera Link interface signal decoding method based on an FPGA, which saves hardware space, reduces resource cost and reduces power consumption.

The technical solution for realizing the purpose of the invention is as follows: a Camera Link interface signal decoding method based on FPGA comprises the following steps:

step 1, converting 1 pair of differential clock signals in a Camera Link interface signal into a single-ended clock signal;

step 2, converting 4 pairs of differential data signals in the Camera Link interface signals into single-ended data signals, and decoding the single-ended data signals into 28-bit parallel data signals;

and 3, arranging and recombining the 28-bit parallel data signals, outputting the 28-bit parallel data signals to the outside as video control signals and pixel signals of TTL level, and outputting the video signals to the outside in an HDMI/VGA format under corresponding resolution.

Further, the step 1 of converting 1 pair of differential clock signals in the Camera Link interface signal into a single-ended clock signal specifically includes:

step 1.1, converting the differential clock signal into a single-ended clock signal by adopting a primitive IBUFDS;

step 1.2, receiving the converted single-ended clock signal by using IDELAY, dynamically adjusting the input delay of the clock signal by using the dynamic loading delay of the IDELAY and a corresponding control signal, so that the sampling clock is just positioned in the middle of the sampled data, and simultaneously accessing the single-ended clock signal into a PLL (phase locked loop) module to generate clocks required by other modules;

step 1.3, processing the adjusted clock signal by using a special serial-parallel converter SERDES;

and step 1.4, shifting the converted clock signal by adopting a Bitslip state machine, comparing the shifted clock signal with the set alignment parameter, and finishing clock signal alignment when the received clock data is consistent with the alignment parameter.

Further, in step 2, the 4 pairs of differential data signals in the Camera Link interface signals are converted into single-ended data signals, and are decoded into 28-bit parallel data signals, specifically as follows:

step 2.1, converting the differential data signal into a single-ended data signal by adopting a primitive IBUFDS;

step 2.2, entering IDELAY to adapt to dynamically adjusting the delay of the single-ended data signal;

step 2.3, processing the adjusted data signal by using a special serial-parallel converter SERDES;

and 2.4, aligning the differential data signal data by adopting a Bitslip state machine, finding the initial end of the data, recovering a final data array with a unique sequence, and analyzing 4 data signal lines into a 28-bit data array.

Further, after arranging and recombining the 28-bit parallel data signals in step 3, the video control signals and the pixel signals which are output externally as TTL levels are output externally, and the video output is performed externally in the HDMI/VGA format under the corresponding resolution, which is specifically as follows:

3.1, removing 4-bit video control signals Fval-frame effective, Dval-data effective, Lval-row effective and Spare-empty from the 28-bit data array analyzed in the step 2;

3.2, arranging and recombining the remaining 24-bit pixel data;

3.3, under the Base mode, dividing a pixel data port into three ports, namely an A port, a B port and a C port, wherein the three ports are 8-bit ports;

and 3.4, outputting the video control signal and pixel signals of the three ports of the port A, the port B and the port C.

Compared with the prior art, the invention has the remarkable advantages that: (1) the hardware structure is simple in design, space is saved in layout, and wiring pressure at the front end is light; (2) the FPGA has high resource utilization rate, good decoding real-time performance and strong program portability, and the developed decoding IP core has high use flexibility and strong universality.

Drawings

FIG. 1 is a schematic diagram of a method for decoding signals of a Camera Link interface based on an FPGA according to the present invention.

FIG. 2 is a schematic flow chart of the FPGA-based Camera Link interface signal decoding method of the present invention.

FIG. 3 is a timing diagram of Camera Link signals in an embodiment of the present invention.

Fig. 4 is a schematic structural diagram of an IP core interface in the present invention.

FIG. 5 is a schematic diagram of the processing flow of the differential clock signal in the present invention.

Fig. 6 is a schematic diagram of a processing flow of differential data signals in the present invention.

Detailed Description

The invention relates to a Camera Link interface signal decoding method based on FPGA, which comprises the steps of firstly converting a clock differential signal transmitted by a Camera Link interface under any configuration into a single-ended pixel clock signal, then converting a data differential signal transmitted by the Camera Link interface under any configuration into a single-ended data signal, decoding the single-ended data signal into a 28-bit parallel data signal according to a data bit width conversion ratio of 1:7, arranging and recombining the 28-bit parallel data signal, then outputting the parallel data signal to the outside as a video control signal and a pixel signal of TTL level, and finally outputting the video to the outside in a HDMI/VGA format under corresponding resolution.

The invention is described in further detail below with reference to the figures and specific examples.

With reference to fig. 1-2, the invention provides a Camera Link interface signal decoding method based on an FPGA, comprising the following steps:

step 1, converting 1 pair of differential clock signals in the Camera Link interface signals into single-ended clock signals, which is specifically as follows with reference to fig. 5:

step 1.1, converting the differential clock signal into a single-ended clock signal by adopting a primitive IBUFDS;

and step 1.2, receiving the converted single-ended clock signal by using IDELAY. IDELAY takes Tap as a basic delay unit, can change the delay length of Tap and provides 4 delay modes: zero hold time delay, fixed delay, variable delay, and dynamic loading delay. The dynamic loading delay of IDELAY is adopted, and the input delay of the clock signal is dynamically adjusted through a corresponding control signal, so that the sampling clock is just positioned in the middle of the sampled data, and the stability of clock analysis is ensured. Meanwhile, a single-end clock signal is connected into a PLL (clock phase locked loop) module and is used for generating clocks required by other modules.

Step 1.3, the adjusted clock signal is processed using a dedicated serial-to-parallel converter SERDES.

And step 1.4, after the data serial-parallel conversion, for the digital signals which are continuously converted, a Bitslip state machine is needed to solve the problem of data alignment after the serial-parallel conversion. By designing a Bitslip state machine to perform shift operation, comparing with a set alignment parameter (e.g. 1100011), when clock data received at a certain time is consistent with the alignment parameter, the clock data is 1100011, the clock data can be considered to be aligned, and meanwhile, the data received at the time is considered to be a start bit and a subsequent operation flow is performed.

Step 2, converting 4 pairs of differential data signals in the Camera Link interface signals into single-ended data signals, and decoding the single-ended data signals into 28-bit parallel data signals, which is specifically as follows in combination with fig. 6:

2.1, 4, the differential data signal line is processed similarly to the clock signal line, and the conversion from differential to single end is carried out by the primitive IBUFDS;

step 2.2, entering IDELAY to adapt to the delay of the dynamic adjustment signal so as to avoid the deflection of the signal;

step 2.3, processing the adjusted data signal by adopting a deserializer SERDES;

and 2.4, aligning the data by adopting a Bitslip state machine, finding out the initial end of the data, recovering a final data array with a unique sequence, and analyzing 4 data signal lines into a 28-bit data array.

Step 3, after arranging and recombining the 28-bit parallel data signals, outputting the video control signals and the pixel signals which are TTL levels to the outside, and outputting the video in an HDMI/VGA format to the outside under the corresponding resolution, which is specifically as follows:

step 3.1, for the 28-bit data array analyzed in step 2, except for the 4-bit video control signals Fval (frame valid), Dval (data valid), Lval (line valid), Spare (empty);

3.2, arranging and recombining the remaining 24-bit pixel data;

3.3, under the Base mode, dividing a pixel data port into three ports, namely an A port (8 bits), a B port (8 bits) and a C port (8 bits);

and 3.4, finally outputting the video control signal and the pixel array.

Example 1

In this embodiment, a Camera Link signal in the Base mode is taken as an example for explanation, and there are 5 pairs of LVDS differential signals in the Base mode, where 4 pairs are data signals and 1 pair is a clock signal, and FPGA primitive IBUFDS resources are called to convert the 5 pairs of differential signals into single-ended signals respectively, so as to prepare for subsequent processing.

And a deserializer SERDES is used for realizing a deserializing function under high-speed source synchronization on the converted single-ended signal wire. In addition, since 7 bits share one clock in the transmission process, a high-rate clock is required to sample the signal data line. Taking the pixel clock as 25MHz for example, a clock of 175MHz, which is 7 times the 25MHz clock, is needed to collect the rising edge of the single-ended data signal line, so that 4 data signal lines are resolved into 28-bit data arrays for subsequent operations, as shown in fig. 3. However, the data array sequence for acquiring the single-ended data signal line at different times is different. In order to ensure the uniqueness of the sequence of the analyzed data arrays, the present embodiment adopts a method of sampling clock signal lines simultaneously, where a certain result (e.g., 1100011) is agreed as an initial analysis state in the clock sampling result, and the sequence of the data arrays analyzed by sampling the other 4 data signal lines is the unique sequence.

Referring to fig. 4, for the 28-bit data signal analyzed in step 2, except for the 4-bit video control signals Fval (frame valid), Dval (data valid), Lval (line valid), Spare (empty), the remaining 24-bit pixel data needs to be arranged and reorganized. Taking the Camera Link signal of Base mode as an example, the pixel data ports are divided into: port A (8 bit), port B (8 bit) and port C (8 bit). The specific rearrangement order is as shown in the following attached table 1, and the video control signal and A, B, C pixel signals of three ports are finally output.

TABLE 1 data array and corresponding arrangement table of pixel data

Data-Na me	Signal-Name
		TX24	LVAL
TX25	FVAL
		TX26	DVAL
TX23	Spare
		TX0	PortA0
TX1	PortA1
		TX2	PortA2
TX3	PortA3
		TX4	PortA4
TX6	PortA5
		TX27	PortA6
TX5	PortA7
		TX7	PortB0
TX8	PortB1
		TX9	PortB2
TX12	PortB3
		TX13	PortB4
TX14	PortB5
		TX10	PortB6
TX11	PortB7
		TX15	PortC0
TX18	PortC1
		TX19	PortC2
TX20	PortC3
		TX21	PortC4
TX22	PortC5
		TX16	PortC6
TX17	PortC7

Claims (4)

1. A Camera Link interface signal decoding method based on FPGA is characterized by comprising the following steps:

step 1, converting 1 pair of differential clock signals in a Camera Link interface signal into a single-ended clock signal;

step 2, converting 4 pairs of differential data signals in the Camera Link interface signals into single-ended data signals, and decoding the single-ended data signals into 28-bit parallel data signals;

and 3, arranging and recombining the 28-bit parallel data signals, outputting the 28-bit parallel data signals to the outside as video control signals and pixel signals of TTL level, and outputting the video signals to the outside in an HDMI/VGA format under corresponding resolution.

2. The method for decoding Camera Link interface signals based on FPGA of claim 1, wherein 1 pair of differential clock signals in the Camera Link interface signals in step 1 are converted into single-ended clock signals, specifically as follows:

step 1.1, converting the differential clock signal into a single-ended clock signal by adopting a primitive IBUFDS;

step 1.2, receiving the converted single-ended clock signal by using IDELAY, dynamically adjusting the input delay of the clock signal by using the dynamic loading delay of the IDELAY and a corresponding control signal, so that the sampling clock is just positioned in the middle of the sampled data, and simultaneously accessing the single-ended clock signal into a PLL (phase locked loop) module to generate clocks required by other modules;

step 1.3, processing the adjusted clock signal by using a special serial-parallel converter SERDES;

and step 1.4, shifting the converted clock signal by adopting a Bitslip state machine, comparing the shifted clock signal with the set alignment parameter, and finishing clock signal alignment when the received clock data is consistent with the alignment parameter.

3. The method for decoding Camera Link interface signals based on FPGA of claim 1, wherein said step 2 converts 4 pairs of differential data signals in the Camera Link interface signals into single-ended data signals, and decodes the single-ended data signals into 28-bit parallel data signals, specifically as follows:

step 2.1, converting the differential data signal into a single-ended data signal by adopting a primitive IBUFDS;

step 2.2, entering IDELAY to adapt to dynamically adjusting the delay of the single-ended data signal;

step 2.3, processing the adjusted data signal by using a special serial-parallel converter SERDES;

and 2.4, aligning the differential data signal data by adopting a Bitslip state machine, finding the initial end of the data, recovering a final data array with a unique sequence, and analyzing 4 data signal lines into a 28-bit data array.

4. The method for decoding Camera Link interface signals based on FPGA of claim 1, wherein 28-bit parallel data signals are arranged and recombined in step 3, and then video control signals and pixel signals with TTL levels are externally output, and video output is performed externally in HDMI/VGA format at corresponding resolution, specifically as follows:

3.1, removing 4-bit video control signals Fval-frame effective, Dval-data effective, Lval-row effective and Spare-empty from the 28-bit data array analyzed in the step 2;

3.2, arranging and recombining the remaining 24-bit pixel data;

3.3, under the Base mode, dividing a pixel data port into three ports, namely an A port, a B port and a C port, wherein the three ports are 8-bit ports;

and 3.4, outputting the video control signal and pixel signals of the three ports of the port A, the port B and the port C.

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