CN205378080U - LVDS digital video transmission interface device based on FPGA - Google Patents
LVDS digital video transmission interface device based on FPGA Download PDFInfo
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- CN205378080U CN205378080U CN201521074946.9U CN201521074946U CN205378080U CN 205378080 U CN205378080 U CN 205378080U CN 201521074946 U CN201521074946 U CN 201521074946U CN 205378080 U CN205378080 U CN 205378080U
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Abstract
The utility model provides a LVDS digital video transmission interface device based on FPGA, including sending interface arrangement and/or receiving interface arrangement, should send interface arrangement and include: a digital video preprocessor module, a LVDS video sending module and LVDS standard IO module. The utility model discloses an in the engineering more succinct mode solved the digital video signal's of camera link standard the receipt problem of sending. The utility model discloses the digital video transmission that makes the FPGA system satisfies that image data is real -time, stable, the requirement of high -speed transmission, provides fine solution for video transmission way.
Description
Technical field
This utility model relates to digital video transmission technical field, particularly relate to a kind of based on FPGA (Field-ProgrammableGateArray, field programmable gate array) LVDS (Low-VoltageDifferentialSignaling, low-voltage differential signal) digital video transmission interface arrangement.
Background technology
Digital visual interface is widely used in the fpga chip of image processing function, can being exported the video after catching, processing, picture signal to computer by digital visual interface, preserving original image for computer, carrying out algorithm simulating and carrying out the follow-up works such as test data sheet provides facility.Meanwhile, digital video turns common interfaces (such as USB, network interface etc.) device and has further speeded up the universal of digital visual interface.
Significant limitation is there is in traditional digital video transmission method in speed, noise, power consumption, cost etc., and LVDS signal has at a high speed, the characteristic of low cost, this LVDS signal is applied in Digital Video Transmission System, just can be made by rational conceptual design system meet view data in real time, the requirement of stable, high-speed transfer.LVDS technological core is to adopt extremely low voltage swing high speed differential transmission data, it is possible to achieve the connection of point-to-point or point to multi--point, carries out distant signal transmission.This technology is that the general purpose I/O standard of kind of the low amplitude of oscillation, its low amplitude of oscillation and low current drive output to have the features such as low-power consumption, low noise, low error rate, low crosstalk and Low emissivity, it is possible to meet the requirement of high speed data transfer.
At present, digital video sends and receive capabilities is mainly by various ChannelLink transceiving chips and what CameraLink digital visual interface completed.Wherein ChannelLink transceiving chip converts CMOS/TTL level signal to LVDS signal, then carries out data transmission.Conventional ChannelLink transceiving chip model includes: DS90CR281/DS90CR282, DS90CR283/DS90CR284, DS90CR285/DS90CR286 (A), DS90CR287/DS90CR288 (A) etc..
CameraLink signal includes video, camera control, three parts of serial communication, and wherein video section is the core of CameraLink signal, mainly includes following 5 pairs of LVDS signals: 4 pairs of data and 1 pair of phase-locked loop clock.The video section transmitting terminal of CameraLink, by the data signal of 28, converts 4 pairs of differential signals in the ratio of 7:1, and 1 clock signal converts 1 pair of differential signal to, and 5 pairs of differential signals are then converted to 28 bit data signals and 1 clock signal by receiving terminal.
ChannelLink transceiving chip is used to need to consider the sequential line sequence matching problem of CMOS/TTL level signal and LVDS data, just when fpga chip sends or receives CMOS/TTL data signal according to the timing requirements of ChannelLink transceiving chip the parallel digital signal to transmit should be encoded and decode, and corresponding signal is carried out delay process；Meanwhile, ChannelLink transceiving chip needs to take area on certain FPGA plate, adds use cost, reduces motility and the versatility of board.
Utility model content
The technical problems to be solved in the utility model is to provide a kind of LVDS digital video transmission interface arrangement based on FPGA, utilizes resource in FPGA sheet to realize transmission and the reception of CameraLink digital video.
The technical solution adopted in the utility model is, the described LVDS digital video transmission interface device based on FPGA, including: the first digital video pretreatment module, a LVDS video sending module and a LVDS standard I/O module, wherein,
Parallel video data signal is postponed by described first digital video pretreatment module and line sequence matching treatment is to obtain meeting the parallel data signal that CameraLink standard time sequence requires, and described parallel data signal and corresponding clock signal are sent to a described LVDS video sending module；
Described parallel data signal is carried out parallel-serial conversion and obtains serial data signal by a described LVDS video sending module, and described clock signal and described serial data signal are sent to a described LVDS standard I/O module；
A described LVDS standard I/O module connects LVDS difference cable, for described clock signal and described serial data signal being transferred out.
Further, a described LVDS video sending module callsIn II softwareThe serializer IP kernel altlvds_tx that Plug-InManager manager provides completes the parallel-serial conversion of data.
Further, described parallel data signal is 28 bit parallel data signals, and described clock signal is 1 bit clock signal；Described serial data signal is 4 road LVDS data signals；
A described LVDS standard I/O module connects 5 road LVDS difference cables, and wherein, 4 road LVDS differential lines are used for transmitting 4 road LVDS data signals, and remaining 1 road LVDS differential lines is used for transmitting 1 bit clock signal.
This utility model also provides for a kind of LVDS digital video receiving interface device based on FPGA, including: the 2nd LVDS standard I/O module, the 2nd LVDS video reception module and the second digital video pretreatment module, wherein,
Described 2nd LVDS standard I/O module connects LVDS difference cable, meets, for receiving, serial LVDS data signal and the corresponding clock signal that CameraLink standard time sequence requires；
Described LVDS data signal is carried out serioparallel exchange and obtains parallel data signal by described 2nd LVDS video reception module, and described clock signal and described parallel data signal are sent to described second digital video pretreatment module；
Parallel data signal is postponed by described second digital video pretreatment module and line sequence matching treatment is to obtain meeting the parallel data signal of the timing requirements of other Digital Video Processing modules on fpga chip.
Further, described 2nd LVDS video reception module is calledIn II softwareThe deserializer IP kernel altlvds_rx that Plug-InManager manager provides completes the serioparallel exchange of data.
Further, described LVDS data signal is 4 road LVDS data signals；Described clock signal is 1 bit clock signal；
Described 2nd LVDS standard I/O module connects 5 road LVDS difference cables, and wherein, 4 road LVDS differential lines are used for receiving 4 road LVDS data signals, and remaining 1 road LVDS differential lines is used for receiving 1 bit clock signal；
Described parallel data signal is 28 bit parallel data signals.
This utility model also provides for a kind of LVDS digital video transmission interface arrangement based on FPGA, including: above-mentioned LVDS digital video transmission interface device, and/or, above-mentioned LVDS digital video receiving interface device.
Adopting technique scheme, this utility model at least has the advantage that
LVDS digital video transmission interface arrangement based on FPGA described in the utility model, in fpga chip, configure digital video transmission/receiving interface, therefore have employed the transmission Receiver Problem that mode more succinct in a kind of engineering solves the digital video signal of CameraLink standard.This utility model make the digital video transmission of FPGA system meet view data in real time, the requirement of stable, high-speed transfer, the delivering path for video provides good solution.
Accompanying drawing explanation
The LVDS digital video transmission interface device based on FPGA that Fig. 1 is this utility model first embodiment forms structural representation；
The LVDS digital video receiving interface device based on FPGA that Fig. 2 is this utility model the second embodiment forms structural representation.
Detailed description of the invention
For further setting forth that this utility model is reach technological means and effect that predetermined purpose is taked, below in conjunction with accompanying drawing and preferred embodiment, this utility model is described in detail as rear.
Development along with fpga chip technology, the I/O pin of fpga chip can be configured to LVDS standard I/O, namely realized the data transmission of LVDS standard by FPGA and receive, matching standard LVDS sends and receives IP kernel module so that this utility model embodiment utilizes resource in FPGA sheet to realize the transmission of ordinary numbers video and CameraLink digital video and reception is possibly realized.
The principle that realizes of the digital video transmission apparatus of this utility model embodiment is: the data being realized LVDS standard by FPGA send and receive, matching standard LVDS sends/receives IP kernel module, the I/O pin configuration of fpga chip is become LVDS standard, carries out transmission and the reception of digital video signal.This video transceiver is made up of LVDS digital video dispensing device and LVDS digital video receiving apparatus, is respectively completed LVDS digital video and sends and LVDS digital video receive capabilities.
This utility model first embodiment, a kind of LVDS digital video transmission interface device based on FPGA, as it is shown in figure 1, include: be positioned at the first digital video pretreatment module the 10, the oneth LVDS video sending module 20 and LVDS standard I/O module 30 on fpga chip, wherein
Parallel video data signal is postponed by the first digital video pretreatment module 10 and line sequence matching treatment is to obtain meeting the parallel data signal that CameraLink standard time sequence requires, and described parallel data signal and corresponding clock signal are sent to a LVDS video sending module 20；
Described parallel data signal is carried out parallel-serial conversion and obtains serial data signal by the oneth LVDS video sending module 20, and described clock signal and described serial data signal are sent to a LVDS standard I/O module 30；
Oneth LVDS standard I/O module 30 connects LVDS difference cable, for described clock signal and described serial data signal being transferred out.
Concrete, a LVDS video sending module 20 callsIn II softwareThe serializer IP kernel altlvds_tx that Plug-InManager manager provides completes the parallel-serial conversion of data.
Described parallel data signal is 28 bit parallel data signals, and described clock signal is 1 bit clock signal；Described serial data signal is 4 road LVDS data signals；
Oneth LVDS standard I/O module 30 connects 5 road LVDS difference cables, and wherein, 4 road LVDS differential lines are used for transmitting 4 road LVDS data signals, and remaining 1 road LVDS differential lines is used for transmitting 1 bit clock signal.
This utility model the second embodiment, a kind of LVDS digital video receiving interface device based on FPGA, as in figure 2 it is shown, include: be positioned at the 2nd LVDS standard I/O module the 60, the 2nd LVDS video reception module 70 and the second digital video pretreatment module 80 on fpga chip, wherein
2nd LVDS standard I/O module 60 connects LVDS difference cable, meets, for receiving, serial LVDS data signal and the corresponding clock signal that CameraLink standard time sequence requires；
Described LVDS data signal is carried out serioparallel exchange and obtains parallel data signal by the 2nd LVDS video reception module 70, and described clock signal and described parallel data signal are sent to the second digital video pretreatment module 80；
Parallel data signal is postponed by the second digital video pretreatment module 80 and line sequence matching treatment is to obtain meeting the parallel data signal of the timing requirements of other Digital Video Processing modules on fpga chip.
Concrete, the 2nd LVDS video reception module 70 is calledIn II softwareThe deserializer IP kernel altlvds_rx that Plug-InManager manager provides completes the serioparallel exchange of data.
Described LVDS data signal is 4 road LVDS data signals；Described clock signal is 1 bit clock signal；
2nd LVDS standard I/O module 60 connects 5 road LVDS difference cables, and wherein, 4 road LVDS differential lines are used for receiving 4 road LVDS data signals, and remaining 1 road LVDS differential lines is used for receiving 1 bit clock signal；
Described parallel data signal is 28 bit parallel data signals.
This utility model the 3rd embodiment, a kind of LVDS digital video transmission interface arrangement based on FPGA, including: the LVDS digital video transmission interface device described in first embodiment, and/or, the LVDS digital video receiving interface device described in the second embodiment.
The described LVDS digital video transmission interface arrangement based on FPGA of this utility model embodiment, it is applied in and sends in the system receiving processor using fpga chip as video signal, avoid adopting special CameraLink video to send and receive chip, thus reducing board area, reduce circuit board making cost.Simultaneously in data transmission procedure, data transfer clock speed is maximum up to 115MHz, higher 85MHz raising 35% than employing transceiving chip, adds the maximum bandwidth of data transmission, also breach CameraLink video simultaneously and send the use restriction receiving the minimum clock 20MHz of chip, reach 5MHz；Actual application more can adapt to standard CameraLink or non-standard ChannelLink interface by the mode of employing change program, without changing hardware circuit, it is possible to meet the design needs of generalization, modularized circuit.
By the explanation of detailed description of the invention, should be reach technological means that predetermined purpose takes and effect is able to more deeply and concrete understanding to this utility model, but appended diagram be only to provide with reference to and purposes of discussion, be not used for this utility model is any limitation as.
Claims (7)
1. the low-voltage differential signal LVDS digital video transmission interface device based on on-site programmable gate array FPGA, it is characterised in that including: the first digital video pretreatment module, a LVDS video sending module and a LVDS standard I/O module, wherein,
Parallel video data signal is postponed by described first digital video pretreatment module and line sequence matching treatment is to obtain meeting the parallel data signal that CameraLink standard time sequence requires, and described parallel data signal and corresponding clock signal are sent to a described LVDS video sending module；
Described parallel data signal is carried out parallel-serial conversion and obtains serial data signal by a described LVDS video sending module, and described clock signal and described serial data signal are sent to a described LVDS standard I/O module；
A described LVDS standard I/O module connects LVDS difference cable, for described clock signal and described serial data signal being transferred out.
2. the LVDS digital video transmission interface device based on FPGA according to claim 1, it is characterised in that a described LVDS video sending module callsIn softwareThe serializer IP kernel altlvds_tx that Plug-InManager manager provides completes the parallel-serial conversion of data.
3. the LVDS digital video transmission interface device based on FPGA according to claim 1 and 2, it is characterised in that described parallel data signal is 28 bit parallel data signals, and described clock signal is 1 bit clock signal；Described serial data signal is 4 road LVDS data signals；
A described LVDS standard I/O module connects 5 road LVDS difference cables, and wherein, 4 road LVDS differential lines are used for transmitting 4 road LVDS data signals, and remaining 1 road LVDS differential lines is used for transmitting 1 bit clock signal.
4. the LVDS digital video receiving interface device based on FPGA, it is characterised in that including: the 2nd LVDS standard I/O module, the 2nd LVDS video reception module and the second digital video pretreatment module, wherein,
Described 2nd LVDS standard I/O module connects LVDS difference cable, meets, for receiving, serial LVDS data signal and the corresponding clock signal that CameraLink standard time sequence requires；
Described LVDS data signal is carried out serioparallel exchange and obtains parallel data signal by described 2nd LVDS video reception module, and described clock signal and described parallel data signal are sent to described second digital video pretreatment module；
Parallel data signal is postponed by described second digital video pretreatment module and line sequence matching treatment is to obtain meeting the parallel data signal of the timing requirements of other Digital Video Processing modules on fpga chip.
5. the LVDS digital video receiving interface device based on FPGA according to claim 4, it is characterised in that described 2nd LVDS video reception module is calledIn softwareThe deserializer IP kernel altlvds_rx that Plug-InManager manager provides completes the serioparallel exchange of data.
6. the LVDS digital video receiving interface device based on FPGA according to claim 4 or 5, it is characterised in that described LVDS data signal is 4 road LVDS data signals；Described clock signal is 1 bit clock signal；
Described 2nd LVDS standard I/O module connects 5 road LVDS difference cables, and wherein, 4 road LVDS differential lines are used for receiving 4 road LVDS data signals, and remaining 1 road LVDS differential lines is used for receiving 1 bit clock signal；
Described parallel data signal is 28 bit parallel data signals.
7. the LVDS digital video transmission interface arrangement based on FPGA, it is characterized in that, including: the LVDS digital video transmission interface device as according to any one of claims 1 to 3, and/or, the LVDS digital video receiving interface device as according to any one of claim 4～6.
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| CN201521074946.9U CN205378080U (en) | 2015-12-22 | 2015-12-22 | LVDS digital video transmission interface device based on FPGA |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106341639A (en) * | 2016-08-30 | 2017-01-18 | 德为显示科技股份有限公司 | FPGA based multi-channel video signal LVDS serialization device and method |
| CN106454187A (en) * | 2016-11-17 | 2017-02-22 | 凌云光技术集团有限责任公司 | FPGA system having Camera Link interface |
| CN111314645A (en) * | 2020-02-24 | 2020-06-19 | 南京理工大学 | Camera Link interface signal decoding method based on FPGA |
-
2015
- 2015-12-22 CN CN201521074946.9U patent/CN205378080U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106341639A (en) * | 2016-08-30 | 2017-01-18 | 德为显示科技股份有限公司 | FPGA based multi-channel video signal LVDS serialization device and method |
| CN106454187A (en) * | 2016-11-17 | 2017-02-22 | 凌云光技术集团有限责任公司 | FPGA system having Camera Link interface |
| CN111314645A (en) * | 2020-02-24 | 2020-06-19 | 南京理工大学 | Camera Link interface signal decoding method based on FPGA |
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