CN111050024A - Image transmission circuit based on MIPI protocol and implementation method thereof - Google Patents
Image transmission circuit based on MIPI protocol and implementation method thereof Download PDFInfo
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Abstract
The invention discloses an image transmission circuit based on MIPI protocol and a realization method thereof, wherein the circuit comprises: the camera interface circuit is connected with the host interface circuit; the host interface circuit comprises a main processor and a host multi-core aviation socket; the main processor is connected with the host multi-core aviation socket; the camera interface circuit comprises an image sensor, an LVDS transmitter and a camera multi-core aviation socket; the image sensor is connected with the LVDS transmitter, the LVDS transmitter is connected with the camera multi-core aviation socket, and the image sensor is connected with the camera multi-core aviation socket. The invention can adapt to high-speed data transmission with longer transmission distance, can decode data bytes at high speed, simultaneously supports MIPI upper layer protocol to carry out optimization control of automatically adjusting communication rate, and realizes high-speed and high-reliability image transmission.
Description
Technical Field
The invention relates to the technical field of image transmission processing, in particular to an image transmission circuit based on an MIPI protocol and an implementation method thereof.
Background
Currently, the MIPI standard becomes the main standard for image output of image sensors; the MIPI is named as a Mobile industry Processor Interface, the Interface among a camera, a display, a radio frequency baseband and a Processor in a mobile phone is standardized primarily to meet the requirement of large-capacity image transmission, and the transmission distance of the physical layers C-PHY and D-PHY of the MIPI which is widely applied at present is short. Due to the wide application of the image sensor in the fields of medical electronics (such as endoscopes) and automotive electronics (such as reverse images), the MIPI interface also largely uses the fields and other fields needing longer distance, the communication distance of the occasions reaches 5 meters and is far longer than that of the inside of a mobile phone, so that the MIPI interface cannot be directly adopted, and the extension of the video communication distance based on the MIPI protocol becomes a bottleneck problem of the popularization of a camera with the MIPI protocol. For MIPI communication application of current high-speed images of 5 meters, other possible solutions are also solution one: image data is not coded and decoded, and is directly transmitted by adopting optical fiber communication through photoelectric conversion; and in the second scheme, the processor is adopted for carrying out protocol conversion and image compression, then the transmission is carried out by adopting the modes of Ethernet or ultra-high-speed USB and the like, and the receiving end is used for carrying out protocol conversion and image data decompression by adopting the processor. Both schemes need to be transformed in a larger scale at a receiving end and a transmitting end, high-speed photoelectric conversion equipment or a high-speed image coding and decoding processor is added, and equipment cost, power consumption and camera size are obviously increased.
Disclosure of Invention
Aiming at the defects and shortcomings of the prior art, the invention designs a simple sending and receiving circuit for an image sensor with an MIPI interface, simply improves the electrical transmission of a D-PHY of the MIPI, enables the electrical transmission to adapt to the high-speed data transmission with the transmission distance of 5 meters, improves a physical layer of a receiving end, enables the physical layer to receive serial bit stream data at a high speed and decode data bytes of an MIPI communication frame, simultaneously supports an MIPI upper layer protocol to automatically adjust the optimization control of the communication rate, realizes high-speed and high-reliability image transmission, does not remarkably increase the cost, power consumption and volume of equipment, and has good application prospect.
In order to achieve the purpose, the invention adopts the following technical scheme:
the invention provides an image transmission circuit based on MIPI protocol, comprising: the camera interface circuit is connected with the host interface circuit;
the host interface circuit comprises a main processor and a host multi-core aviation socket;
the main processor is provided with an LVDS interface and an SCCB interface, the host multi-core aviation socket is provided with a host LVDS differential signal interface and a host SCCB transmission interface, the LVDS interface of the main processor is connected with the host LVDS differential signal interface of the host multi-core aviation socket, and the SCCB interface of the main processor is connected with the host SCCB transmission interface of the host multi-core aviation socket;
the camera interface circuit comprises an image sensor, an LVDS transmitter and a camera multi-core aviation socket;
the image sensor is provided with an image sensor power supply input end, an SLVS differential signal output end and an SCCB transmission signal output end;
the LVDS transmitter is provided with a LVDS transmitter power input end, an SLVS differential signal receiving end and an LVDS signal output end;
the camera multi-core aviation socket is provided with a camera power interface, a camera LVDS differential signal interface and a camera SCCB transmission interface;
the SLVS differential signal output end of the image sensor is connected with the SLVS differential signal receiving end of the LVDS transmitter, the LVDS signal output end of the LVDS transmitter is connected with the camera LVDS differential signal interface of the camera multi-core aviation socket, and the SCCB transmission signal output end of the image sensor is connected with the camera SCCB transmission interface of the camera multi-core aviation socket.
As a preferred technical solution, the input end of the image sensor power supply is connected with a first voltage converter and a second voltage converter, and the first voltage converter converts the input power supply voltage into an image sensor I/O port and an analog circuit power supply;
the second voltage converter converts an input power voltage into a core power of the image sensor.
As a preferred technical solution, a third voltage converter is connected to the power input end of the LVDS transmitter, and the third voltage converter converts the input power voltage into the input power of the LVDS transmitter.
As a preferred technical solution, a termination resistor is provided in the LVDS transmitter.
As a preferred technical scheme, the host interface circuit is further provided with a synchronous buck converter and an LVDS receiver, the synchronous buck converter is used for converting a power supply to provide the power supply for the host multi-core aviation socket, the synchronous buck converter is connected with the host multi-core aviation socket, the host multi-core aviation socket is connected with the LVDS receiver, and the LVDS receiver is connected with the main processor.
As a preferred technical scheme, the host interface circuit is further provided with a main processor voltage-stabilized power supply, an input end of the main processor voltage-stabilized power supply is connected with an external power supply, and an output end of the main processor voltage-stabilized power supply is connected with the main processor.
As a preferred technical solution, a first logic level converter, a second logic level converter, a first counter, a second counter, a measurement state machine, a reception state machine, an RX deserializer and a decoder are arranged in the main processor;
the output end of the measurement controller is respectively connected with a first counter and a second counter, the output end of the first logic level converter is respectively connected with the second counter, a receiving state machine, an RX deserializer and a decoder, and the output end of the second logic level converter is connected with the RX deserializer and the decoder;
the first counter is used for counting by reference clock signals, and the second counter is used for counting by synchronous communication clock signals;
the first logic level converter is used for converting the LVDS differential clock signal into a synchronous communication clock signal; the second logic level converter is used for converting the LVDS differential signal into serial bit stream data RxDataBit;
the input end of the receiving state machine is used for receiving a synchronous communication clock signal, a stop time counting signal and a reference clock signal, and the output end of the receiving state machine is used for outputting a synchronous communication state signal, a silent idle state signal, a BybeReset reset signal and a stop time maximum counting signal;
the receiving state machine is provided with a stop time counter, and the reset end of the stop time counter is connected with the communication synchronous clock signal end;
the measurement controller is used for receiving a synchronous communication state signal and outputting a measurement synchronous signal, and the first counter and the second counter receive the measurement synchronous signal;
and the RX deserializer and the decoder are used for receiving the synchronous communication clock signal, the BybeReset reset signal and serial bit stream data RxDataBit and outputting a byte stream signal and a byte synchronous clock signal.
As a preferred technical scheme, the multi-core aviation socket of the camera is connected with a host by adopting a connecting cable, the connecting cable is provided with eight twisted pairs which are respectively set as a first twisted pair, a second twisted pair, a third twisted pair, a fourth twisted pair, a fifth twisted pair, a sixth twisted pair, a seventh twisted pair and an eighth twisted pair;
the first twisted pair is provided with a power line and a ground wire, the second twisted pair is provided with a clock wire and a ground wire of a serial camera control bus, the third twisted pair is provided with a data wire and a ground wire of the serial camera control bus, the fourth twisted pair is provided with a positive terminal differential clock wire and a negative terminal differential clock wire, the fifth twisted pair is provided with a first group of differential data wires, the sixth twisted pair is provided with a second group of differential data wires, the seventh twisted pair is provided with a third group of differential data wires, and the eighth twisted pair is provided with a fourth group of differential data wires.
As a preferred technical solution, the main processor employs an FPGA chip, the image sensor employs an OV10823 model image sensor, and the LVDS transmitter employs a DS25BR440 model LVDS transmitter.
The invention also provides a realization method of the image transmission circuit based on the MIPI protocol, which comprises the following steps:
LVDS differential clock signals are converted into synchronous communication clock signals through a first logic level converter;
the LVDS differential signal is converted into serial bit stream data RxDataBit through a second logic level converter;
the serial Bit stream data RxDataBit passes through an RX deserializer and a decoder, under the control of a synchronous communication clock signal, a byte stream signal and a byte synchronous clock signal are output, and meanwhile, the RX deserializer and the decoder carry out 10/8Bit decoding to form byte data;
the receiving state machine outputs a synchronous communication state signal and a silent idle state signal, when the receiving state machine outputs the silent idle state signal, the receiving state machine sends a BybeReset reset signal to an RX deserializer and a decoder, and receives a bit stream from the next synchronous communication clock CommLock;
when the synchronous communication state signal and the period measuring signal are at the high level at the same time, the measuring controller sets the measuring synchronous signal to be at the high level, the first counter counts the reference clock signal, the second counter counts the synchronous communication clock signal, when the count reaches a set value MeasureeCycle, the measuring synchronous signal is set to be at the low level, the period measuring completion signal is set to be at the high level, the current synchronous clock period measurement is finished, a count value Nsys of the first counter and a count value Ncom of the second counter are read, and the synchronous clock period is calculated;
resetting the measurement controller, starting to measure again after the synchronous communication state signal of the receiving state machine is changed into high level, and setting the value of the measurement synchronous signal;
when the communication synchronous clock signal has a rising edge, the synchronous communication state signal is at a high level, the silent idle state is at a low level, and meanwhile, when the communication synchronous clock signal has a rising edge, the stop time counter is reset and cleared;
the stop time counter counts the reference clock signal, and when the count value is greater than the set stop time count value, the receiving state machine outputs a silent idle state signal;
the stop time counter outputs a count value StopTimerNumMax to obtain the silent idle state time;
and synthesizing a data frame, wherein the data frame comprises a check code, a synchronous clock period, a state signal of a receiving state machine and silent idle state time, and the main processor adjusts the communication rate and the frame rate according to the content of the data frame.
Compared with the prior art, the invention has the following advantages and beneficial effects:
(1) the invention combines the MIPI protocol and LVDS video transmission, and the video signal of the image sensor is directly transmitted to the host through the communication cable after being converted into the LVDS differential signal through the level, thereby ensuring the communication distance of 5 meters.
(2) The receiving and transmitting circuit based on LVDS is simple, optical cables and video coding and decoding are not needed, and the cost, the power consumption and the size of equipment are obviously reduced.
(3) The physical layer designed by the invention supports the upper layer protocol to manually and automatically adjust the image resolution and the frame rate, and fully exerts the communication capability of the cable.
Drawings
Fig. 1 is a schematic diagram illustrating a connection between a camera and a host of an image transmission circuit based on an MIPI protocol according to the present embodiment;
fig. 2 is a schematic diagram of a camera interface circuit of the image transmission circuit based on the MIPI protocol according to the embodiment;
fig. 3 is a schematic diagram of a host interface circuit of the image transmission circuit based on the MIPI protocol according to the embodiment;
fig. 4 is a schematic structural diagram of the physical layer based on the MIPI protocol in this embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Examples
As shown in fig. 1, the present embodiment provides an image transmission circuit based on MIPI protocol, including: the camera interface circuit is connected with the host interface circuit, the camera is connected with the host by a 16-core aviation socket, the connecting cable is an 8-pair twisted pair, and the twisted pair consists of two category-six CAT6 twisted pairs. The 1 st twisted pair is a power line, +4V and a ground line GND; the 2 nd twisted pair is a clock line SCL and a ground line GND of the SCCB bus, the 3 rd twisted pair is a data line SDA and a ground line GND of the SCCB bus, the clock line and the data line of the SCCB bus are respectively transmitted with the ground line on the twisted pair, so that the electromagnetic interference is reduced, and the communication reliability is improved; the 4 th twisted pair is differential CLOCK line CLOCK LANE + and CLOCK LANE based on the MIPI physical layer of LVDS, the 5 th to 8 th twisted pairs are differential DATA lines DATA LANE1+ and DATA LANE1-, DATA LANE2+ and DATA LANE2-, DATA LANE3+ and DATA LANE3-, DATA LANE4+ and DATA LANE4 based on the MIPI physical layer of LVDS, in order to ensure the synchronization of the transmitted CLOCK signal and DATA signal, the same parameter twisted pair (or coaxial cable) is required to be used for CLOCKLANE and DATA LANE, and the error of the length of the cable is within 2 centimeters, the LVDS differential transmission prolongs the communication distance, and ensures the reliability of communication.
As shown in fig. 2, the camera interface circuit mainly includes a power supply circuit and an LVDS conversion circuit. The power supply circuit comprises a first voltage converter, a second voltage converter and a third voltage converter, and mainly comprises two LDO power supply chips of TP5912-3.0 and TPS73533, a DC/DC voltage reduction power supply chip TPS62262 and peripheral circuits thereof, wherein the first voltage converter adopts the LP5912-3.0 power supply chip, changes 4V power supply voltage obtained from a host through a socket into 3.0V, and is used as an I/O port of the image sensor OV10823 and a power supply of an analog part; the second voltage converter adopts a TPS62262 chip and provides a 1.2V power supply for the kernel of the image sensor; the third voltage converter adopts a TPS73533 chip, changes the 4V power supply voltage into 3.3V, and is used as an LVDS conversion and line driving chip DS25BR440 power supply. The LVDS transmitter adopts a DS25BR440 chip to convert an SLVS differential signal of an MIPI physical layer of the image sensor into an LVDS differential signal, the DS25BR440 chip is configured to receive Equalization (Equalization) disabling and transmit Pre-emphasis (Pre-empaisis) enabling, the communication distance is prolonged, the transmission rate of a single Data Lane line reaching 3Gbps can be achieved, the DS25BR440 chip contains a terminal resistor, and the area of a PCB is reduced. The SCCB signal of the image sensor is directly connected to the communication cable. Therefore, the camera has the advantages of simple circuit, small volume, convenient installation and cost reduction.
As shown in fig. 3, the host interface circuit uses a 5V power supply to supply power to the system, the synchronous buck converter uses a TPS82150 chip to provide a 4V power supply to the host multicore aviation socket, the main processor regulated power supply uses a TPS73533 chip to provide a 3.3V power supply to the main processor, and the 5V power supply also provides power to other circuits (such as 2.5V, 1.2V, etc. of FPGA) of the host through other chips. The host employs 2 DS25BR440 as a host LVDS receiver to receive image data from the camera, the chip being configured to receive Equalization (Equalization) enable, transmit Pre-emphasis (Pre-empaisis) disable, preferably in reverse of the DS25BR440 configuration of the camera. The host system adopts an FPGA as a main processor, the model is MPF200T-FCG484E, LVDS and SCCB interfaces (including pull-up resistors) can be directly connected, and the image processing function of the host is also completed through the FPGA chip.
In this embodiment, LVDS electrical signals are used for video image transmission, which prolongs the communication distance, but the low power consumption transmission mode indicated by single-ended logic level (non-differential signal transmission level) in the original MIPI CSI-2D-PHY physical layer protocol does not exist, and the state transfer of the receiving state machine by different signal combinations depending on the low power consumption mode in the original MIPI protocol cannot be realized, a new receiver and a new receiving state machine must be designed for the physical layer of the MIPI protocol based on LVDS, and meanwhile, the modification of the MIPI upper layer protocol is reduced as much as possible, and the upper layer protocol can be compatible with the physical layer through simple configuration, thereby fully playing the advantages of high speed and standardization of the MIPI protocol.
As shown in fig. 4, in this embodiment, all MIPI physical layers based on LVDS are implemented inside an FPGA chip, an SCCB signal from a socket is isolated and then connected to a general I/O of the FPGA chip, and an SCCB protocol is implemented through an IP core of the general FPGA chip; the LVDS signals from the socket are isolated and then connected to the high-speed differential I/O of the FPGA chip, which is implemented by the receiving circuit and the receiving state machine of this embodiment.
As shown in fig. 4, the synchronous communication CLOCK Commclock of this embodiment is obtained by passing LVDS differential signals of CLOCK LANE + and CLOCK LANE-through an I/O level conversion circuit of an FPGA chip; differential data lines DATAx LANE + and DATAxLANE- (x is 1,2,3,4 and four paths) LVDS differential signals are processed by an I/O level conversion circuit of an FPGA chip to obtain serial bit stream data RxDataBit, and the serial bit stream data RxDataBit is processed by an RX Deserializer and a decoder RX Deserializer and decoder under the control of a synchronous communication clock Commclock to obtain a byte stream RxDataByte signal and a byte synchronous clock RxDataByteLock. The upper layer protocol obtains the byte stream of the data frame in the MIPI protocol according to two signals of the byte stream RxDataByte and the byte synchronous clock RxDataByteLock, and the upper layer protocol assembles the data frame according to the semantics of the bytes and the working state of a receiving state Machine RXState Machine. Meanwhile, the RX Deserializer and decoder RX Deserializer also complete 10/8Bit decoding into byte data. When the receiving State Machine RX State Machine is in silent idle State SilenceIdleState, BybeReset reset signal is sent to RX Deserializer and Decoder to reset the BybeReset reset signal, and the next byte is received from the next synchronous communication clock CommLock to receive bit stream, thereby realizing the synchronization of data frames and ensuring the reliability of communication.
The video output resolution and frame rate of the image sensor of the camera are set by the host computer through the SCCB bus, the range of the clock frequency or period of the video transmission after the setting is known, but in order to adapt to different cameras and fault diagnosis, the clock frequency or period of the communication process must be measured, and the synchronous communication clock period is also used as a basic parameter for the receiving state machine to judge the state transition. In this embodiment, two counters are designed to measure the period of the MIPI clock signal, a first counter and a second counter of the two 32-bit counters respectively count a reference clock SysClock and a synchronous communication clock comclock, the start and stop of the two counters are simultaneously controlled by a measurement synchronization signal MeasureSync, after the measurement synchronization signal MeasureSync passes through a start and stop time period (e.g., 10 microseconds), a host respectively reads count values Nsys and Ncomm of the first counter and the second counter, the period of the reference clock SysClock is known as period PeriodRef (e.g., the period is 800pS if the reference clock is 1250 MHz), and then the synchronous communication clock period can be calculated according to the following formula.
The measurement synchronization signal MeasureSync is generated by a measurement controller MeasureController. When the synchronous communication state synccomstate and the period measurement period are simultaneously at high level, the measurement controller MeasureController sets the measurement synchronous signal MeasureSync at high level, the counter in the measurement controller MeasureController starts counting the reference clock SysClock from zero, when the counter reaches a set value measureccycle, the measurement synchronous signal MeasureSync is set at low level, the period measurement completion signal period measuremenfinished is set at high level, which indicates that the measurement of the current synchronous clock period is finished, the host reads out corresponding count values from the first counter and the second counter, and calculates the synchronous clock period according to the formula (1). When measuring next time, the host computer firstly sets the period measurement PeriodMeasureEn to low level, the measurement controller MeasureController resets, the period measurement completion signal PeriodMeaurerefined sets to low level, the internal counter is reset, then the host computer sets the period measurement PeriodMeasureEn to high level, and starts to measure again after the synchronous communication state SyncCommState of the receiving state machine is changed to high level. The value of the measurement synchronization signal MeasureSync is set to be half of the time required by the image sensor to output a line of pixels, for example, when the pixels are 1920 × 1080 pixels and the frame rate of 30FPS and the system clock period is 1250MHz, the MeasureCycle is set to be 12500.
The receiving State Machine RX State Machine determines the working State of the physical layer receiver of the MIPI, and has two working states, namely a synchronous communication State SyncCommState and a silent idle State SilenceIdleState. The receive state Machine RXState Machine has two clock inputs, communicating the synchronous clock comclock and the host's reference clock SysClock. The receiving State Machine RX State Machine includes a 32-bit counter StopTimer with a reference clock SysClock as a counting input, and the communication synchronization clock comclock is connected to a reset terminal of the StopTimer. When the communication synchronous clock comclock has a rising edge, the receiving State Machine RX State Machine is set to a synchronous communication State synccomstate, i.e. the synchronous communication State synccomstate is high level, and the silent idle State SilenceIdleState is low level, and at the same time the rising edge of the communication synchronous clock comclock clears the counter StopTimer, and its count value StopTimer num is 0. When the counter StopTimer has no clear pulse after no communication synchronous clock CommClock, the counter StopTimer counts the reference clock SysClock, when the count value is greater than the set stop time count StopTimerNumSet, the State transition of the receiving State Machine RX State Machine to silent idle State SilentidState, i.e. the synchronous communication State SyncCommState is low and the silent idle State SilentidState is high, if the StopTimer has no reset pulse, the counting is continued until the maximum value 0 xFFFFFFFFFF, but the counting is not cleared, the reset clear is not performed until the communication synchronous clock CommClock rises, and the count value StopTimerNumMax of the StopTimer is stored in a register inside the receiving State Machine RX State Machine before the clear, thereby calculating the silent idle time, which can be used for fault diagnosis and communication rate modification. StopTimerNumSet is determined according to the following formula:
after the physical layer assembles the received data bytes into a data frame, the MIPI upper layer protocol can calculate the error rate according to the check code in the data frame, and the resolution and the frame rate of the image sensor are adjusted by combining the silent idle time length, so that high-speed reliable communication is ensured.
In this embodiment, LVDS differential signals are used between the video transmitting circuit and the video receiving circuit to realize high-speed video transmission, and parameter configuration of the host FPGA chip to the camera is performed through a Serial Camera Control Bus (SCCB) (similar to I)2C) The manual control and the automatic control of the communication speed of the image sensor by the host are also realized by the serial camera control bus. The mark and interval between the data frames of the MIPI are determined by adopting a silent idle state without a high-speed communication clock signal; protocols above MIPI physical layerThe communication rate and frame rate may be dynamically adaptively adjusted based on the silent idle state duration and the video data frame error rate.
In this embodiment, a video output interface of an image sensor (an OV10823 is selected) in a camera is MIPI, a control bus is SCCB, a physical layer level conversion and transmission circuit of the MIPI adopts 2 pieces of DS25BR440, a composite cable which is implemented by two CAT6 cables and is composed of 8 pairs of differential lines with a length of 5 meters, 8 pairs of differential lines are 4 pairs of MIPI Data lines Data Lane1 to DataLane4, 1 pair of Clock lines Clock Lane, 2 pairs of SCCB and a power line, respectively, and a receiving circuit in a host adopts an SCCB electrical isolation circuit ADuM2250 and 3 pieces of ADN4654 to perform LVDS electrical isolation, and then is connected to an I/O pin of an FPGA chip.
In this embodiment, the FPGA chip determines whether the communication process is in a synchronous communication state or a silent idle state according to whether a Clock Lane Clock signal is received, where the length of the silent idle state is an interval between two data frames; the designed physical layer comprises a synchronous communication clock period measuring function, a receiving state machine function, a serial-parallel conversion function and a decoding function, an upper layer protocol of the physical layer is supported to manually and automatically adjust image resolution and frame rate, the FPGA chip counts error rate or error code rate in the communication process through check codes of data frames, when the error code rate is larger than a set value (such as 1%), the FPGA chip updates the frame rate or resolution of an image sensor through an SCCB bus to reduce the actual communication rate, and the maximum communication capacity is guaranteed to be obtained under the existing communication condition.
The above embodiments are preferred embodiments of the present invention, but the present invention is not limited to the above embodiments, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be construed as equivalents thereof, and all such changes, modifications, substitutions, combinations, and simplifications are intended to be included in the scope of the present invention.
Claims (10)
1. An image transmission circuit based on MIPI protocol, characterized by comprising: the camera interface circuit is connected with the host interface circuit;
the host interface circuit comprises a main processor and a host multi-core aviation socket;
the main processor is provided with an LVDS interface and an SCCB interface, the host multi-core aviation socket is provided with a host LVDS differential signal interface and a host SCCB transmission interface, the LVDS interface of the main processor is connected with the host LVDS differential signal interface of the host multi-core aviation socket, and the SCCB interface of the main processor is connected with the host SCCB transmission interface of the host multi-core aviation socket;
the camera interface circuit comprises an image sensor, an LVDS transmitter and a camera multi-core aviation socket;
the image sensor is provided with an image sensor power supply input end, an SLVS differential signal output end and an SCCB transmission signal output end;
the LVDS transmitter is provided with a LVDS transmitter power input end, an SLVS differential signal receiving end and an LVDS signal output end;
the camera multi-core aviation socket is provided with a camera power interface, a camera LVDS differential signal interface and a camera SCCB transmission interface;
the SLVS differential signal output end of the image sensor is connected with the SLVS differential signal receiving end of the LVDS transmitter, the LVDS signal output end of the LVDS transmitter is connected with the camera LVDS differential signal interface of the camera multi-core aviation socket, and the SCCB transmission signal output end of the image sensor is connected with the camera SCCB transmission interface of the camera multi-core aviation socket.
2. The MIPI protocol-based image transmission circuit of claim 1, wherein a first voltage converter and a second voltage converter are connected to the image sensor power input terminal, the first voltage converter converting an input power voltage into an image sensor I/O port and an analog circuit power;
the second voltage converter converts an input power voltage into a core power of the image sensor.
3. The MIPI protocol-based image transmission circuit according to claim 1, wherein a third voltage converter is connected to the LVDS transmitter power input terminal, the third voltage converter converting an input power voltage into an LVDS transmitter input power.
4. The MIPI protocol-based image transmission circuit of claim 1 or 3, wherein a termination resistor is arranged in the LVDS transmitter.
5. The MIPI-protocol-based image transmission circuit of claim 1, wherein the host interface circuit is further provided with a synchronous buck converter and an LVDS receiver, the synchronous buck converter is configured to convert power to supply power to the host multicore aviation socket, the synchronous buck converter is connected to the host multicore aviation socket, the host multicore aviation socket is connected to the LVDS receiver, and the LVDS receiver is connected to the main processor.
6. The MIPI protocol based image transmission circuit of claim 1 wherein the host interface circuit further comprises a regulated main processor power supply, wherein an input terminal of the regulated main processor power supply is connected with an external power supply, and an output terminal of the regulated main processor power supply is connected with the main processor.
7. The MIPI protocol-based image transmission circuit according to claim 1, wherein a first logic level converter, a second logic level converter, a first counter, a second counter, a measurement state machine, a reception state machine, and an RX deserializer and decoder are provided in the main processor;
the output end of the measurement controller is respectively connected with a first counter and a second counter, the output end of the first logic level converter is respectively connected with the second counter, a receiving state machine, an RX deserializer and a decoder, and the output end of the second logic level converter is connected with the RX deserializer and the decoder;
the first counter is used for counting by reference clock signals, and the second counter is used for counting by synchronous communication clock signals;
the first logic level converter is used for converting the LVDS differential clock signal into a synchronous communication clock signal; the second logic level converter is used for converting the LVDS differential signal into serial bit stream data RxDataBit;
the input end of the receiving state machine is used for receiving a synchronous communication clock signal, a stop time counting signal and a reference clock signal, and the output end of the receiving state machine is used for outputting a synchronous communication state signal, a silent idle state signal, a BybeReset reset signal and a stop time maximum counting signal;
the receiving state machine is provided with a stop time counter, and the reset end of the stop time counter is connected with the communication synchronous clock signal end;
the measurement controller is used for receiving a synchronous communication state signal and outputting a measurement synchronous signal, and the first counter and the second counter receive the measurement synchronous signal;
and the RX deserializer and the decoder are used for receiving the synchronous communication clock signal, the BybeReset reset signal and serial bit stream data RxDataBit and outputting a byte stream signal and a byte synchronous clock signal.
8. The MIPI protocol-based image transmission circuit of claim 1, wherein the camera multi-core aviation socket is connected with the host computer by using a connection cable, and the connection cable is provided with eight twisted pairs, which are respectively set as a first twisted pair, a second twisted pair, a third twisted pair, a fourth twisted pair, a fifth twisted pair, a sixth twisted pair, a seventh twisted pair and an eighth twisted pair;
the first twisted pair is provided with a power line and a ground wire, the second twisted pair is provided with a clock wire and a ground wire of a serial camera control bus, the third twisted pair is provided with a data wire and a ground wire of the serial camera control bus, the fourth twisted pair is provided with a positive terminal differential clock wire and a negative terminal differential clock wire, the fifth twisted pair is provided with a first group of differential data wires, the sixth twisted pair is provided with a second group of differential data wires, the seventh twisted pair is provided with a third group of differential data wires, and the eighth twisted pair is provided with a fourth group of differential data wires.
9. The MIPI-protocol-based image transmission circuit according to claim 1, wherein the main processor employs an FPGA chip, the image sensor employs an OV10823 model image sensor, and the LVDS transmitter employs a DS25BR440 model LVDS transmitter.
10. An implementation method of an image transmission circuit based on MIPI protocol is characterized by comprising the following steps:
LVDS differential clock signals are converted into synchronous communication clock signals through a first logic level converter;
the LVDS differential signal is converted into serial bit stream data RxDataBit through a second logic level converter;
the serial Bit stream data RxDataBit passes through an RX deserializer and a decoder, under the control of a synchronous communication clock signal, a byte stream signal and a byte synchronous clock signal are output, and meanwhile, the RX deserializer and the decoder carry out 10/8Bit decoding to form byte data;
the receiving state machine outputs a synchronous communication state signal and a silent idle state signal, when the receiving state machine outputs the silent idle state signal, the receiving state machine sends a BybeReset reset signal to an RX deserializer and a decoder, and receives a bit stream from the next synchronous communication clock CommLock;
when the synchronous communication state signal and the period measuring signal are at the high level at the same time, the measuring controller sets the measuring synchronous signal to be at the high level, the first counter counts the reference clock signal, the second counter counts the synchronous communication clock signal, when the count reaches a set value MeasureeCycle, the measuring synchronous signal is set to be at the low level, the period measuring completion signal is set to be at the high level, the current synchronous clock period measurement is finished, a count value Nsys of the first counter and a count value Ncom of the second counter are read, and the synchronous clock period is calculated;
resetting the measurement controller, starting to measure again after the synchronous communication state signal of the receiving state machine is changed into high level, and setting the value of the measurement synchronous signal;
when the communication synchronous clock signal has a rising edge, the synchronous communication state signal is at a high level, the silent idle state is at a low level, and meanwhile, when the communication synchronous clock signal has a rising edge, the stop time counter is reset and cleared;
the stop time counter counts the reference clock signal, and when the count value is greater than the set stop time count value, the receiving state machine outputs a silent idle state signal;
the stop time counter outputs a count value StopTimerNumMax to obtain the silent idle state time;
and synthesizing a data frame, wherein the data frame comprises a check code, a synchronous clock period, a state signal of a receiving state machine and silent idle state time, and the main processor adjusts the communication rate and the frame rate according to the content of the data frame.
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