CN210807465U - Multifunctional video converter - Google Patents
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- CN210807465U CN210807465U CN202020057525.XU CN202020057525U CN210807465U CN 210807465 U CN210807465 U CN 210807465U CN 202020057525 U CN202020057525 U CN 202020057525U CN 210807465 U CN210807465 U CN 210807465U
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Abstract
The utility model provides a multi-functional video converter relates to video image processing conversion field, and this system contains the utility model discloses for core design hardware circuit based on FPGA, realize the data conversion between HDMI, 3GSDI, camera Link, BT656/BT1120, PAL/NTSC and the gigabit Ethernet. The utility model discloses a data input decoding processing portion, data transfer processing portion, data output coding processing portion. The input video generates parallel data after passing through the data input decoding processing part, the parallel data enters the data transfer processing part taking FPGA as a core, the preprocessed data is transmitted to the data output coding processing part according to channel selection, and the expected video format is output after being processed by a corresponding coding chip, so that the conversion among different video formats is realized.
Description
Technical Field
The utility model relates to a video converter, concretely relates to multi-functional video converter.
Background
At present, practical data interfaces of various cameras and equipment in the market are different, and great obstacles are created to product research and development and modular design. Different data interfaces in the market only have single conversion functions, the flexibility is deficient, and different data transmission requirements are difficult to meet.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a multi-functional video converter, it can realize mainstream video interface data transmission's on the market switching, has improved resource utilization, effectively solves the problem among the background art.
The utility model provides a multi-functional converter includes data input decoding processing portion, data transfer processing portion, data output coding processing portion. The input video generates parallel data after passing through the data input decoding processing part, the parallel data enters the data transfer processing part taking FPGA as a core, the data is preprocessed through an instruction sent by an upper computer and is cached, then the preprocessed data is transmitted to the data output coding processing part according to the instruction of the upper computer or a channel selection button, and an expected video format is output after being processed by a corresponding coding chip, so that conversion among different video formats is realized.
The utility model provides a multifunctional video converter, include:
HDMI decoder chip ADV7611, SDI decoder chip GS2970AIBE3, CameraLink decoder chip DS90CR288A, PAL/NTSC decoder chip MAX9526, and gigabit network PHY chip as data input decoding processing units;
an HDMI encoding chip ADV7511, an SDI encoding chip GS2972-IBE3, a CameraLink encoding chip DS90CR287A, a PAL/NTSC encoding chip ADV7179, and a gigabit network PHY chip as data output encoding processing units;
an FPGA chip XC7K325T as a data relay processing unit;
the HDMI decoding chip ADV7611, the SDI decoding chip GS2970AIBE3, the CameraLink decoding chip DS90CR288A, the PAL/NTSC decoding chip MAX9526 and the gigabit network PHY chip are respectively connected with the FPGA chip XC7K325T through parallel input data interfaces;
the HDMI coding chip ADV7511, the SDI coding chip GS2972-IBE3, the CameraLink coding chip DS90CR287A, the PAL/NTSC coding chip ADV7179 and the gigabit network PHY chip are respectively connected with the FPGA chip XC7K325T through parallel output data interfaces.
When HDMI video image data is input, a parallel input data interface of an FPGA chip XC7K325T corresponding to an HDMI decoding chip ADV7511 is set in an on state, and parallel output data interfaces of the FPGA chip XC7K325T corresponding to an HDMI coding chip ADV7511, an SDI coding chip GS2972-IBE3, a CameraLink coding chip DS90CR287A, a PAL/NTSC coding chip ADV7179 and a gigabit network PHY chip are set in an on state;
the HDMI video image data enters an HDMI decoding chip ADV7611 through an HDMI interface for decoding;
after decoding, the decoded image enters an FPGA chip XC7K325T through a parallel input data interface corresponding to an HDMI decoding chip ADV7511 to be subjected to image processing;
the data after image processing all enter an HDMI coding chip ADV7511, an SDI coding chip GS2972-IBE3, a CameraLink coding chip DS90CR287A, a PAL/NTSC coding chip ADV7179 and a gigabit network PHY chip through a parallel output data interface.
When SDI video image data is input, a parallel input data interface of an FPGA chip XC7K325T corresponding to an SDI decoding chip GS2970AIBE3 is set to be in an on state, and parallel output data interfaces of the FPGA chip XC7K325T corresponding to an HDMI coding chip ADV7511, an SDI coding chip GS2972-IBE3, a CameraLink coding chip DS90CR287A, a PAL/NTSC coding chip ADV7179 and a gigabit network PHY chip are set to be in an on state;
SDI video image data enters an SDI decoding chip GS2970AIBE3 through an SDI interface to be decoded;
after decoding, the image enters an FPGA chip XC7K325T through a parallel input data interface corresponding to an SDI decoding chip GS2970AIBE3 to be subjected to image processing;
the data after image processing all enter an HDMI coding chip ADV7511, an SDI coding chip GS2972-IBE3, a CameraLink coding chip DS90CR287A, a PAL/NTSC coding chip ADV7179 and a gigabit network PHY chip through a parallel output data interface.
When video image data of a CameraLink is input, a parallel input data interface of an FPGA chip XC7K325T corresponding to a CameraLink decoding chip DS90CR288A is set to be in an on state, and parallel output data interfaces of the FPGA chip XC7K325T corresponding to an HDMI coding chip ADV7511, an SDI coding chip GS2972-IBE3, a CameraLink coding chip DS90CR287A, a PAL/NTSC coding chip ADV7179 and a gigabit network PHY chip are set to be in an on state;
the CameraLink video image data enters a CameraLink decoding chip DS90CR288A through a CameraLink interface for decoding;
after decoding, the image is transmitted to an FPGA chip XC7K325T through a parallel input data interface corresponding to a CameraLink decoding chip DS90CR288A for image processing;
the data after image processing all enter an HDMI coding chip ADV7511, an SDI coding chip GS2972-IBE3, a CameraLink coding chip DS90CR287A, a PAL/NTSC coding chip ADV7179 and a gigabit network PHY chip through a parallel output data interface.
When PAL/NTSC video image data are input, the parallel input data interface of the FPGA chip XC7K325T corresponding to the PAL/NTSC decoding chip MAX9526 is set in an on state, and the parallel output data interface of the FPGA chip XC7K325T corresponding to the HDMI coding chip ADV7511, the SDI coding chip GS2972-IBE3, the CameraLink coding chip DS90CR287A, the PAL/NTSC coding chip ADV7179 and the gigabit network PHY chip is set in an on state;
PAL/NTSC video image data enter PAL/NTSC decoding chip MAX9526 to decode through PAL/NTSC interface;
after decoding, the decoded image enters an FPGA chip XC7K325T through a parallel input data interface corresponding to a PAL/NTSC decoding chip MAX9526 to be subjected to image processing;
the data after image processing all enter an HDMI coding chip ADV7511, an SDI coding chip GS2972-IBE3, a CameraLink coding chip DS90CR287A, a PAL/NTSC coding chip ADV7179 and a gigabit network PHY chip through a parallel output data interface.
When gigabit network PHY video image data is input, the parallel input data interface of the FPGA chip XC7K325T corresponding to the gigabit network PHY chip is set in an on state, and the parallel output data interface of the FPGA chip XC7K325T corresponding to the HDMI coding chip ADV7511, the SDI coding chip GS2972-IBE3, the CameraLink coding chip DS90CR287A, the PAL/NTSC coding chip ADV7179 and the gigabit network PHY chip is set in an on state;
kilomega network PHY video image data firstly enters an FPGA chip XC7K325T through a kilomega network PHY interface;
then enters an FPGA chip XC7K325T through a parallel input data interface corresponding to the gigabit network PHY chip to perform image processing;
the data after image processing all enter an HDMI coding chip ADV7511, an SDI coding chip GS2972-IBE3, a CameraLink coding chip DS90CR287A, a PAL/NTSC coding chip ADV7179 and a gigabit network PHY chip through a parallel output data interface.
The multifunctional video converter further comprises an RS232/RS422/CAN interface connected with the FPGA chip, and the RS232/RS422/CAN interface is connected with an upper computer.
The utility model discloses still include with the RS232 RS422 CAN interface that the FPGA chip links to each other, RS232 RS422 CAN interface links to each other with the host computer, CAN realize the host computer to input/output channel's gating operation, also CAN realize making an uproar, sharpening, upset, contrast regulation, brightness control etc. operations fall to the adjustment of output video frame frequency and chronogenesis perhaps to the image.
The beneficial effects of the utility model are that a multifunctional video converter is provided, it can realize mainstream video interface data transmission's switching on the market. The input video generates parallel data after passing through the input decoding module, the parallel data enters the channel selection module taking the FPGA as a core, the preprocessed data is transmitted to the output coding module according to the channel selection, and the expected video format is output after being processed by the corresponding coding chip, so that the conversion among different video formats is realized, and the resource utilization rate can be improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
fig. 1 is a schematic diagram of the structure of the multifunctional video converter module of the present invention.
Detailed Description
To make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the following examples and drawings, and the exemplary embodiments and descriptions thereof of the present invention are only used for explaining the present invention, and are not intended as limitations of the present invention.
Examples
As shown in fig. 1, the present invention adopts a modular design, in which the FPGA is a module core and is a link between each input module and each output module; the FPGA chip realizes image data double-buffer ping-pong switching through DDR 3: and when the image data is written into the DDR3 according to the time sequence control signal, reading the image data stored in the DDR3 at the last moment, and converting the image data into corresponding video image data through an output coding module after the FPGA chip integrates the time sequence.
Camera Link input clock and chronogenesis are nonstandard, the utility model discloses a but video reception is accomplished to equipment automated inspection chronogenesis and self-adaptation.
The utility model discloses a FPGA chip is XC7K325T of XILINX company, external RS232 RS422 serial interface, CAN interface, and the interface links to each other with the host computer, realizes with host computer communication, receives the instruction operation of host computer, realizes the processing of image and the selection of output video passageway.
The utility model provides a HDMI video image input adopts ADV7611 chip to decode, and the biggest TMDS clock frequency of this chip is 165M, possess 24 output pixel bus and high bandwidth digital content protection (HDCP).
The utility model provides a HDMI video image output adopts the ADV7511 chip, and the biggest TMDS clock frequency of this chip is 225M, the biggest 1080p video format that supports.
The utility model provides a GS2970AIBE3 chip is adopted in SDI video image input, and this chip parallel data output provides with 20 bits or 10 bit format, supports 3G, HD and SD video rate to provide multiple mapping option. Thus, such a parallel bus can interface directly with the video processor integrated circuit and the output data can be multiplexed onto 10 bits to achieve a low pin count interface.
The utility model provides a SDI video image output adopts GS2972-IBE3 chip, and this chip has integrateed the driver, can produce the serial digital output signal that accords with SMPTE 424M, SMPTE 292M, SMPTE 259M-C or DVB-ASI standard completely.
The utility model provides a camera Link video image input adopts the decoding chip to be DS90CR288A, and this chip converts 4 to LVDS data stream into 28 LVCMOS/LVTTL data. The maximum clock frequency supported by the chip is 85 MHz.
The utility model provides a camera Link video image output adopts the coding chip to be DS90CR287A, and this chip converts 28-bit LVCMOS/LVTTL data into 4 pairs LVDS data stream, with the fifth to LVDS lock phase clock link parallel transmission.
The utility model provides a PAL/NTSC decoding chip is MAX9526, and 8 bits or the parallel model of 10 bits of this chip output data are totally compatible BT.656 standard.
The utility model provides a PAL/NTSC coding chip is ADV7179, and this chip can carry out DA conversion to 10 high-quality video data, reaches 80dB SNR's PAL/NTSC signal up.
The utility model provides a BT656 BT1120 input and FPGA directly link, and BT656 BT1120 output and FPGA directly link, use FPGA logic circuit to accomplish the encoding and decoding operation.
The utility model provides an ethernet transceiver chip is 88E1111, and this chip has integrateed advanced mixed signal and has handled and promote balanced effect, eliminate echo and crosstalk, data recovery and error correction, can be used to gigabit ethernet and hundred mega ethernet.
The above-mentioned embodiments, further detailed description of the objects, technical solutions and advantages of the present invention, it should be understood that the above description is only the embodiments of the present invention, and is not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (7)
1. A multi-function video converter, comprising:
HDMI decoder chip ADV7611, SDI decoder chip GS2970AIBE3, CameraLink decoder chip DS90CR288A, PAL/NTSC decoder chip MAX9526, and gigabit network PHY chip as data input decoding processing units;
an HDMI encoding chip ADV7511, an SDI encoding chip GS2972-IBE3, a CameraLink encoding chip DS90CR287A, a PAL/NTSC encoding chip ADV7179, and a gigabit network PHY chip as data output encoding processing units;
an FPGA chip XC7K325T as a data relay processing unit;
the HDMI decoding chip ADV7611, the SDI decoding chip GS2970AIBE3, the CameraLink decoding chip DS90CR288A, the PAL/NTSC decoding chip MAX9526 and the gigabit network PHY chip are respectively connected with the FPGA chip XC7K325T through parallel input data interfaces;
the HDMI coding chip ADV7511, the SDI coding chip GS2972-IBE3, the CameraLink coding chip DS90CR287A, the PAL/NTSC coding chip ADV7179 and the gigabit network PHY chip are respectively connected with the FPGA chip XC7K325T through parallel output data interfaces.
2. The multi-function video converter according to claim 1,
when HDMI video image data is input, a parallel input data interface of an FPGA chip XC7K325T corresponding to an HDMI decoding chip ADV7611 is set in an on state, and parallel output data interfaces of the FPGA chip XC7K325T corresponding to an HDMI coding chip ADV7511, an SDI coding chip GS2972-IBE3, a CameraLink coding chip DS90CR287A, a PAL/NTSC coding chip ADV7179 and a gigabit network PHY chip are set in an on state;
the HDMI video image data enters an HDMI decoding chip ADV7611 through an HDMI interface for decoding;
after decoding, the decoded image enters an FPGA chip XC7K325T through a parallel input data interface corresponding to an HDMI decoding chip ADV7611 to be subjected to image processing;
the data after image processing all enter an HDMI coding chip ADV7511, an SDI coding chip GS2972-IBE3, a CameraLink coding chip DS90CR287A, a PAL/NTSC coding chip ADV7179 and a gigabit network PHY chip through a parallel output data interface.
3. The multi-function video converter according to claim 1,
when SDI video image data is input, a parallel input data interface of an FPGA chip XC7K325T corresponding to an SDI decoding chip GS2970AIBE3 is set to be in an on state, and parallel output data interfaces of the FPGA chip XC7K325T corresponding to an HDMI coding chip ADV7511, an SDI coding chip GS2972-IBE3, a CameraLink coding chip DS90CR287A, a PAL/NTSC coding chip ADV7179 and a gigabit network PHY chip are set to be in an on state;
SDI video image data enters an SDI decoding chip GS2970AIBE3 through an SDI interface to be decoded;
after decoding, the image enters an FPGA chip XC7K325T through a parallel input data interface corresponding to an SDI decoding chip GS2970AIBE3 to be subjected to image processing;
the data after image processing all enter an HDMI coding chip ADV7511, an SDI coding chip GS2972-IBE3, a CameraLink coding chip DS90CR287A, a PAL/NTSC coding chip ADV7179 and a gigabit network PHY chip through a parallel output data interface.
4. The multi-function video converter according to claim 1,
when video image data of a CameraLink is input, a parallel input data interface of an FPGA chip XC7K325T corresponding to a CameraLink decoding chip DS90CR288A is set to be in an on state, and parallel output data interfaces of the FPGA chip XC7K325T corresponding to an HDMI coding chip ADV7511, an SDI coding chip GS2972-IBE3, a CameraLink coding chip DS90CR287A, a PAL/NTSC coding chip ADV7179 and a gigabit network PHY chip are set to be in an on state;
the CameraLink video image data enters a CameraLink decoding chip DS90CR288A through a CameraLink interface for decoding;
after decoding, the image is transmitted to an FPGA chip XC7K325T through a parallel input data interface corresponding to a CameraLink decoding chip DS90CR288A for image processing;
the data after image processing all enter an HDMI coding chip ADV7511, an SDI coding chip GS2972-IBE3, a CameraLink coding chip DS90CR287A, a PAL/NTSC coding chip ADV7179 and a gigabit network PHY chip through a parallel output data interface.
5. The multi-function video converter according to claim 1,
when PAL/NTSC video image data are input, the parallel input data interface of the FPGA chip XC7K325T corresponding to the PAL/NTSC decoding chip MAX9526 is set in an on state, and the parallel output data interface of the FPGA chip XC7K325T corresponding to the HDMI coding chip ADV7511, the SDI coding chip GS2972-IBE3, the CameraLink coding chip DS90CR287A, the PAL/NTSC coding chip ADV7179 and the gigabit network PHY chip is set in an on state;
PAL/NTSC video image data enter PAL/NTSC decoding chip MAX9526 to decode through PAL/NTSC interface;
after decoding, the decoded image enters an FPGA chip XC7K325T through a parallel input data interface corresponding to a PAL/NTSC decoding chip MAX9526 to be subjected to image processing;
the data after image processing all enter an HDMI coding chip ADV7511, an SDI coding chip GS2972-IBE3, a CameraLink coding chip DS90CR287A, a PAL/NTSC coding chip ADV7179 and a gigabit network PHY chip through a parallel output data interface.
6. The multi-function video converter according to claim 1,
when gigabit network PHY video image data is input, the parallel input data interface of the FPGA chip XC7K325T corresponding to the gigabit network PHY chip is set in an on state, and the parallel output data interface of the FPGA chip XC7K325T corresponding to the HDMI coding chip ADV7511, the SDI coding chip GS2972-IBE3, the CameraLink coding chip DS90CR287A, the PAL/NTSC coding chip ADV7179 and the gigabit network PHY chip is set in an on state;
kilomega network PHY video image data firstly enters an FPGA chip XC7K325T through a kilomega network PHY interface;
then enters an FPGA chip XC7K325T through a parallel input data interface corresponding to the gigabit network PHY chip to perform image processing;
the data after image processing all enter an HDMI coding chip ADV7511, an SDI coding chip GS2972-IBE3, a CameraLink coding chip DS90CR287A, a PAL/NTSC coding chip ADV7179 and a gigabit network PHY chip through a parallel output data interface.
7. The multifunctional video converter according to any one of claims 1 to 6, further comprising an RS232/RS422/CAN interface connected to said FPGA chip, said RS232/RS422/CAN interface being connected to an upper computer.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112351223A (en) * | 2020-09-24 | 2021-02-09 | 天津市英贝特航天科技有限公司 | Multi-video extension system and method based on FPGA |
| CN112995557A (en) * | 2021-02-22 | 2021-06-18 | 航天科工火箭技术有限公司 | Parallel processing method and equipment for multi-channel images |
| CN113727111A (en) * | 2021-08-31 | 2021-11-30 | 威创集团股份有限公司 | 4K high definition IP video is compiled and is separated integrative box and video transmission system |
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2020
- 2020-01-10 CN CN202020057525.XU patent/CN210807465U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112351223A (en) * | 2020-09-24 | 2021-02-09 | 天津市英贝特航天科技有限公司 | Multi-video extension system and method based on FPGA |
| CN112995557A (en) * | 2021-02-22 | 2021-06-18 | 航天科工火箭技术有限公司 | Parallel processing method and equipment for multi-channel images |
| CN113727111A (en) * | 2021-08-31 | 2021-11-30 | 威创集团股份有限公司 | 4K high definition IP video is compiled and is separated integrative box and video transmission system |
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