CN102647613B - Internet protocol video coding box - Google Patents
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- CN102647613B CN102647613B CN201210107095.8A CN201210107095A CN102647613B CN 102647613 B CN102647613 B CN 102647613B CN 201210107095 A CN201210107095 A CN 201210107095A CN 102647613 B CN102647613 B CN 102647613B
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Abstract
The embodiment of the invention discloses an Internet protocol video coding box, which comprises a system level chip, a video coding chip and a physical layer chip, wherein the system level chip comprises an output interface and two kinds or more than two kinds of video input interfaces, in addition, each kind of video input interface receives video data with one kind of video sources, the video coding chip and the physical layer chip are respectively provided with an input interface and an output interface, the video input interface of the system level chip is an interface connected with the video data source, the output interface of the physical layer chip is an interface of an Internet protocol video coding box for sending video data to the outside of the Internet protocol video coding box, the output interface of the system level chip and the input interface of the video coding chip can be connected in a communicable way, and the output interface of the video coding chip and the input interface of the physical layer chip are connected in a communicable way. The Internet protocol video coding box can be compatible with various video data sources, the development efficiency is improved, and the maintenance difficulty is reduced.
Description
Technical field
The present invention relates to technical field of video coding, particularly a kind of Internet protocol video codec.
Background technology
Along with people are to the attention of self Environmental security, and the carrying out of safe city, we are a mass of camera everywhere at one's side, the rapid rising of IP (Internet Protocol, Internet protocol) network simultaneously, bring comprehensive fusion of tissue, trade information, as the important collection source of information, video monitoring system is integrated comprehensively and is incorporated network information system, has been trend of the times.Be distributed in video server everywhere, personal workstation also wishes by network insertion simultaneously, the propagation realizing multimedia messages with share.But the video data volume of un-encoded compression is huge, existing network environment is transmitted comparatively difficulty.
In order to realize the transmission of multimedia messages on network, IP video codec arises at the historic moment.IP video codec first carries out Video coding compression, then carries out IP transmission by network after adopting corresponding scheme to gather for different video source.
IP video codec as shown in Figure 1, comprise: CVBS (Composite Video BroadcastSignal, Composite Video Baseband Signal) decoder (decoder), deinterlace (de interlacing) & scale (convergent-divergent) chip and coding chip.Originate for camera as the video data of IP video codec, the process of video data and flow to specific as follows:
101:IP video codec receives the CVBS (Composite VideoBroadcast Signal, Composite Video Baseband Signal) exported from camera;
The CVBS of decoder (video) chip to input of 102:IP video codec carries out video decode, forms digital YUV (brightness and the aberration) signal of standard, exports to deinterlace & scale chip;
103:deinterlace (de interlacing) & scale (convergent-divergent) chip carries out de interlacing and convergent-divergent process to YUV signal, converts the video format of needs to, then exports to coding chip;
104: coding chip carries out compression coding to video and be packaged into network packet delivering on network and transmitting.
In the process of the process of above-mentioned video data, video decoder and deinterlace & scale realizes head end video collection, and coding chip realizes video compression and transmission.
Except shown in Fig. 1 being that video data source is thought with camera, video data source can also be: video server, personal workstation etc., and the interface of these video data sources varies.In order to adapt to the video data of these interfaces and correspondence, the front-end collection of IP video codec needs to adopt different chips, and an IPR video codec supports a kind of video data source of interface.
Inventor finds in the process realizing the embodiment of the present invention: in order to realize accessing different video data sources, and need to develop different IP video codecs to the video data supporting these different input, development efficiency is low, and maintenance difficulties is large.
Summary of the invention
Embodiments provide a kind of Internet protocol video codec, can compatible various video data source, improve development efficiency, reduce maintenance difficulties.
A kind of Internet protocol video codec, comprising:
System level chip, video coding chip and physical chip;
Described system level chip has output interface and two kinds or two or more video input interfaces, and often kind of video input interface receives a kind of video data of video source; Described video coding chip and physical chip all have input interface and output interface; The video input interface of described system level chip is the interface be connected with video data source, and the output interface of described physical chip is the interface that Internet protocol video codec sends video data outside Internet protocol video codec;
The output interface of described system level chip and the input interface of described video coding chip are being connected by communication mode, and the outgoing interface of described video coding chip and the input interface of described physical chip are being connected by communication mode;
Described system level chip carries out YC separation to the video data that its video input interface inputs and de interlacing process obtains progressive signal, and exports to the input interface of video coding chip by its output interface; Described video coding chip carries out compressed encoding to the progressive signal that its input interface inputs, and by after compressed encoding data line by line packing, by its output interface by packing after line by line data send to the input interface of described physical chip; Described physical chip by after packing line by line data sent to network interface by its output interface.
As can be seen from the above technical solutions, the embodiment of the present invention has the following advantages: system level chip can support the input of polytype video data, adopt an IP video codec just can compatible various video data source, do not need to develop different IP video codecs for different video data sources, can development efficiency be improved, reduce maintenance difficulties.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly introduced, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the structural representation of prior art IP video codec;
Fig. 2 is the structural representation of embodiment of the present invention IP video codec;
Fig. 3 is embodiment of the present invention IP video codec data flow schematic diagram.
Embodiment
In order to make the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, the present invention is described in further detail, and obviously, described embodiment is only a part of embodiment of the present invention, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making other embodiments all obtained under creative work prerequisite, belong to the scope of protection of the invention.
Embodiments provide a kind of Internet protocol video codec, as shown in Figure 2, comprising: system level chip 201, video coding chip 202 and physical chip 203;
Said system level chip 201 has output interface and two kinds or two or more video input interfaces, and often kind of video input interface receives a kind of video data of video source; Above-mentioned video coding chip 202 and physical chip 203 all have input interface and output interface; The video input interface of said system level chip 201 is the interfaces be connected with video data source, and the output interface of above-mentioned physical chip 203 is the interface that Internet protocol video codec sends video data outside Internet protocol video codec;
The output interface of said system level chip 201 and the input interface of above-mentioned video coding chip 202 are being connected by communication mode, and the outgoing interface of above-mentioned video coding chip 202 and the input interface of above-mentioned physical chip 203 are being connected by communication mode;
Said system level chip 201 carries out YC separation to the video data that its video input interface inputs and de interlacing process obtains progressive signal, and exports to the input interface of video coding chip 202 by its output interface; Above-mentioned video coding chip 202 carries out compressed encoding to the progressive signal that its input interface inputs, and by after compressed encoding data line by line packing, by its output interface by packing after line by line data send to the input interface of above-mentioned physical chip 203; Above-mentioned physical chip 203 by after packing line by line data sent to network interface by its output interface.
Adopt the scheme of above embodiment, system level chip 201 can support the input of polytype video data, adopt an IP video codec just can compatible various video data source, do not need to develop different IP video codecs for different video data sources, can development efficiency be improved, reduce maintenance difficulties.
Alternatively, said system level chip 201 is: any one in MST6M16 chip, MST6M20 chip and MST209 chip.It should be noted that, as long as the function that system level chip 201 can realize in above-described embodiment is just passable, concrete chip also may have a lot, and the embodiment of the present invention will not limit this, and the above citing about system level chip 201 also should not be construed as the restriction to the embodiment of the present invention.
Alternatively, the kind of above-mentioned video input interface comprises: at least one in HDMI (High DefinitionMultimedia Interface, HDMI (High Definition Multimedia Interface)), DVI (Digital Vi sual Interface, digital visual interface), VGA (Video Graphics Array, Video Graphics Array) interface, color difference components interface YpbPr, S-VIDEO (SEPARATE-VDIEO, YC separation vision signal), Composite Video Baseband Signal CVBS interface.It should be noted that, because video genre has a lot of corresponding interface also can have a lot, application documents cannot be exhaustive to this, and the above citing about video input interface kind should not be construed as the restriction to the embodiment of the present invention.
Further, at least one that the video data of said system level chip 201 also for inputting its video input interface carries out noise reduction process, image quality strengthens in process, picture-in-picture process, the process of screen menu type regulative mode obtains progressive signal.It should be noted that system level chip 201 may also have other function a lot, the video data disposal ability that above image procossing is correlated with should not be construed as the restriction to system level chip 201 disposal ability.
Further, said system level chip 201 is also for being unstringed when the video data determining that its video input interface inputs is serial video data and being encoded to parallel normal brightness and aberration YUV signal; Said system level chip 201 carries out YC separation and de interlacing process to the video data that its video input interface inputs and obtains progressive signal and comprise: said system level chip 201 performs de interlacing process to above-mentioned normal brightness and aberration YUV signal and obtains progressive signal.The present embodiment adopts the system level chip 201 with parallel YUV ability of unstringing and encode can realize the parallel processing capability of polytype video data, promotes the ability that IP video codec supports polytype video data source simultaneously further.
Further, said system level chip 201 also comprises: command reception interface;
Above-mentioned command reception interface is the command reception interface of the video pictures regulating parameter receiving user's input; Said system level chip 201 is also for regulating the video data that its input interface inputs according to above-mentioned video pictures regulating parameter.
Alternatively, above-mentioned command reception interface is resolution command reception interface;
Above-mentioned command reception interface is that the command reception interface of the video pictures regulating parameter receiving user's input is specially: above-mentioned resolution instruction interface is the resolution command reception interface of the resolution parameter instruction receiving user's input; Said system level chip 201 is also specially for carrying out adjustment according to above-mentioned video pictures regulating parameter to the video data that its input interface inputs: said system level chip 201 is also for being adjusted to the resolution that above-mentioned resolution is specified by the video data that its input interface inputs according to resolution parameter.
Alternatively, above-mentioned command reception interface is image quality command reception interface;
Above-mentioned command reception interface is that the command reception interface of the video pictures regulating parameter receiving user's input is specially: above-mentioned image quality instruction interface is the image quality command reception interface of the image quality parameter instruction receiving user's input; Said system level chip 201 is also specially for carrying out adjustment according to above-mentioned video pictures regulating parameter to the video data that its input interface inputs: said system level chip 201 is also for being adjusted to the image quality that above-mentioned image quality parameter is specified by the video data that its input interface inputs according to image quality parameter.
It should be noted that, the citing of two input interfaces comprised further about system level chip 201 above can realize the adjustment of user to video data, it should be noted that the information interaction of this system level chip 201 IP video codec and user in other words can meet the requirement of user for output video further, improve customer experience.It should be noted that, it will be understood by those skilled in the art that and be obviously not limited only to above two kinds with the information interaction of user to have a lot in addition, therefore above two kinds of interfaces are illustrated the restriction that should not be construed as the embodiment of the present invention.
Alternatively, above-mentioned video coding chip 202 carries out compressed encoding to the progressive signal that its input interface inputs and comprises: above-mentioned video coding chip 202 carries out H.264 compressed encoding to the progressive signal that its input interface inputs.It should be noted that the mode to progressive signal carries out compressed encoding has a lot, above-mentioned implementation H.264 should not be construed as unique implementation of compression coding mode as a kind of preferred implementation, should not be construed as the restriction to the embodiment of the present invention.
Alternatively, above-mentioned video coding chip 202 comprises: MAC (Medium Access Control, media access control layer) module; Data line by line after compressed encoding comprise by above-mentioned video coding chip 202: ethernet medium MAC layer MAC module is network packet to the packet line by line after above-mentioned compressed encoding.
The chip of said system level chip 201 is selected can with reference to as follows: very abundant for the one chip solution interface of LCD TV at present, 1 multimedia ASIC (Application Specific IntegratedCircuit, application-specific integrated circuit (ASIC)) chip can access CVBS simultaneously, S-VIDEO, YPbPr, VGA, DVI, HDMI etc., built-in deinterlace and Scale function simultaneously, also there is many image processing functions, as 3D noise reduction, image quality strengthens, picture-in-picture, OSD (on-screen display, screen menu type regulative mode) function etc., therefore the asic chip in LCD TV can be utilized to do the video acquisition of IP coding and decoding video box, realize multisignal source access.
The scheme that the chip of present system level chip 201 realizes head end video collection can make: utilize single-chip LCD TV solution MSTAR (stars at dawn semiconductor) 6M16 chip to realize head end video collection; Also can with the solution of other single-chips in LCD TV: SOC (System on Chip, system level chip), such as: as other model chip of MSTAR, as: MSTAR6M20, MST209, MTK (MediaTe, MediaTek Inc.'s multimedia chip), realtek (Realtek) have a lot of this kind of one chip solution.Wherein MSTAR 6M16 integrated chip video AD C (Analog-to-DigitalConverter, analog-to-digital conversion), Decoder (decoder), 3D (Three Dimensions, three-dimensional) comb filter, HDMI receiver, deinterlace, sacler, 3D noise reduction can be realized, picture quality enhancement, picture-in-picture, the functions such as OSD, and support 1080P resolution.
The present invention of back-end code chip adopts DM368 chip, other arbitrary H.264 codec chips can also be adopted, wherein DM368 chip can as a preferred implementation, DM368 chip supports multiple format HD video coded system, comprise MPEG2 (Moving Picture Experts Group, Motion Picture Experts Group, ISO/IEC13818 international standard), MPEG4 (Moving Pictures ExpertsGroup 4, dynamic image expert group 4, ISO/IEC14496), and H.264 (ISO/IEC14496 the 10th part) etc., support multi tate multithread and high definition multi-channel function, the 1080p standard of the highest support 30 frame codings per second, DM368 built-in chip type has ARM9 (Advanced RISC Machines, ARC computer processor) controller, can control whole system work, the module of all right integrated ethernet mac (Medium Access Control, media access control layer), can directly pack the data to network packet and send in addition.
Video data using CVBS as input, system level chip 201 is for 6M16, video coding chip 202 is for DM368 chip, signal processing flow shown in Fig. 3 of the present invention is as follows: after CVBS signal enters 6M16 chip, inner Decoder carries out YC separation to it and is decoded into YUV signal, deinterlacer does de interlacing process, changed into progressive signal, then as required (such as: user arranges image quality parameter with remote controller by adjustment OSD menu) processes image quality, last scaler exports to rear class DM368 chip after picture is zoomed to the resolution of requirement (resolution parameter that user is arranged requires) is encoded.DM368 chip can support VC1 (video decode form), MPEG2, MPEG4, MJPEG (Motion Joint Photographic Experts Group, motion pictures expert associating group) and H.264 coded system.Data after DM368 chip compression coding are by issuing PHY (physical layer after the MAC module packing of DM368 chip internal, physical layer) chip, data are sent on netting twine by RJ45 network interface by PHY chip (instantiation can with RTL8101 or BCM5221 etc.) to be transmitted.
In addition, if the video data position HDMI of input, after so HDMI enters 6M16 chip, HDMI serial data can also be carried out unstringing and be encoded into parallel YUV signal by the HDMI receiver (HDMI receiver) in 6M16 chip, then de interlacing process is carried out, image quality process, then sends to DM368 chip after convergent-divergent, DM368 chip is sent by PHY chip after H.264 encoding.The handling process of the video data of other type is similar with it to be illustrated no longer one by one.
Present invention employs based on efficient H.264 Image Compression, by efficient compression ratio, greatly can reduce video streaming image to the band-limited demand of transmission, unique algorithm H.264 ensures again image quality loss reduction simultaneously, realizes highly forcing down damage.
These are only the present invention's preferably embodiment; but protection scope of the present invention is not limited thereto; anyly be familiar with those skilled in the art in the technical scope that the embodiment of the present invention discloses, the change that can expect easily or replacement, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.
Claims (9)
1. an Internet protocol video codec, is characterized in that, comprising:
System level chip, video coding chip and physical chip; Described video coding chip comprises: ethernet medium MAC layer MAC module; Described system level chip has output interface and two kinds or two or more video input interfaces, and often kind of video input interface receives a kind of video data of video source; Described video coding chip and physical chip all have input interface and output interface; The video input interface of described system level chip is the interface be connected with video data source, and the output interface of described physical chip is the interface that Internet protocol video codec sends video data outside Internet protocol video codec;
The output interface of described system level chip and the input interface of described video coding chip are being connected by communication mode, and the outgoing interface of described video coding chip and the input interface of described physical chip are being connected by communication mode;
Described system level chip carries out YC separation to the video data that its video input interface inputs and de interlacing process obtains progressive signal, and exports to the input interface of video coding chip by its output interface; Described video coding chip carries out compressed encoding to the progressive signal that its input interface inputs, packet line by line after described compressed encoding is packaged as network packet by ethernet medium MAC layer MAC module, by its output interface by packing after line by line data send to the input interface of described physical chip; Described physical chip by after packing line by line data sent to network interface by its output interface.
2. Internet protocol video codec according to claim 1, is characterized in that,
Described system level chip is: any one in MST6M16 chip, MST6M20 chip and MST209 chip.
3. Internet protocol video codec according to claim 1, it is characterized in that, the kind of described video input interface comprises: at least one in HDMI (High Definition Multimedia Interface) HDMI, digital visual interface DVI, Video Graphics Array USB interface, color difference components interface YpbPr, YC separation vision signal S-VIDEO interface, Composite Video Baseband Signal CVBS interface.
4. Internet protocol video codec according to claim 1, is characterized in that,
At least one that the video data of described system level chip also for inputting its video input interface carries out noise reduction process, image quality strengthens in process, picture-in-picture process, the process of screen menu type regulative mode obtains progressive signal.
5. Internet protocol video codec according to claim 1, it is characterized in that, described system level chip is also for being unstringed when the video data determining that its video input interface inputs is serial video data and being encoded to parallel normal brightness and aberration YUV signal;
Described system level chip carries out YC separation and de interlacing process to the video data that its video input interface inputs and obtains progressive signal and comprise:
Described system level chip performs de interlacing process to described normal brightness and aberration YUV signal and obtains progressive signal.
6. Internet protocol video codec according to claim 1 to 5 any one, is characterized in that, described system level chip also comprises: command reception interface;
Described command reception interface is the command reception interface of the video pictures regulating parameter receiving user's input;
Described system level chip is also for regulating the video data that its input interface inputs according to described video pictures regulating parameter.
7. Internet protocol video codec according to claim 6, it is characterized in that, described command reception interface is resolution command reception interface;
Described command reception interface is that the command reception interface of the video pictures regulating parameter receiving user's input is specially: described resolution instruction interface is the resolution command reception interface of the resolution parameter instruction receiving user's input;
Described system level chip is also specially for carrying out adjustment according to described video pictures regulating parameter to the video data that its input interface inputs: described system level chip is also for being adjusted to the resolution that described resolution is specified by the video data that its input interface inputs according to resolution parameter.
8. Internet protocol video codec according to claim 6, it is characterized in that, described command reception interface is image quality command reception interface;
Described command reception interface is that the command reception interface of the video pictures regulating parameter receiving user's input is specially: described image quality instruction interface is the image quality command reception interface of the image quality parameter instruction receiving user's input;
Described system level chip is also specially for carrying out adjustment according to described video pictures regulating parameter to the video data that its input interface inputs: described system level chip is also for being adjusted to the image quality that described image quality parameter is specified by the video data that its input interface inputs according to image quality parameter.
9. Internet protocol video codec according to claim 1 to 5 any one, is characterized in that, described video coding chip carries out compressed encoding to the progressive signal that its input interface inputs and comprises:
Described video coding chip carries out H.264 compressed encoding to the progressive signal that its input interface inputs.
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| CN104506883A (en) * | 2014-12-11 | 2015-04-08 | 成都德芯数字科技有限公司 | Audio and video encoder based on wide area network live broadcast and working method thereof |
| CN111818084A (en) * | 2020-07-23 | 2020-10-23 | 斑马网络技术有限公司 | Vehicle machine remote display method and server |
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