CN104717440A - LED transmitting card cascade interface - Google Patents
LED transmitting card cascade interface Download PDFInfo
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- CN104717440A CN104717440A CN201510107125.9A CN201510107125A CN104717440A CN 104717440 A CN104717440 A CN 104717440A CN 201510107125 A CN201510107125 A CN 201510107125A CN 104717440 A CN104717440 A CN 104717440A
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Abstract
The invention relates to an LED transmitting card cascade interface which comprises a physical layer and a link layer, wherein the physical layer comprises a first connector, a balancing chip and a second connector, the link layer comprises an SERDES IP core, a data unbinding module, a data decoding module, a first clock domain conversion module, a second clock domain conversion module and a data coding module. The LED transmitting card cascade interface is designed based on a high speed SERDES interface and supports an SERDES serial link, and the data bandwidth is high; the interface comprises the physical layer and the link layer, a hardware circuit of the LED transmitting card cascade interface is simplified, the reliability is high, and the implementation is easy. When a transmitted image is larger, compared with the defect that an LED transmitting card cascade interface in the prior art is complex, the circuit of the LED transmitting card cascade interface is simple, and efficient transmission of large image data can be guaranteed.
Description
Technical field
The present invention relates to LED display system technical field, particularly relate to a kind of LED sending card subtending port.
Background technology
LED (light-emitting diode) sending card is the pith of LED display system.The function of LED sending card comprises: the image that Received signal strength source sends or vision signal, send to receiving card after buffer memory; Be responsible for the control to whole LED display system.In addition sending card also needs cascade function.When the maximum image resolution that sending card exports is less than input image resolution, needs with other sending card cascades thus complete the display of input picture.Such as, the resolution of input picture is 1920x960, and the maximum fan-out capability of sending card is 960x960, so just needs the cascade of 2 pieces of sending card phases could export the image of 1920x960.As shown in Figure 1, sending card A receives 1920x960 picture signal, the left-half of cutting picture signal is sent to the left-half of LED wall, sending card A sends to sending card B 1920x960 picture signal by subtending port, the right half part of sending card B cutting picture signal is sent to the right half part of LED wall, thus realizes the complete output of picture signal.
The cascade function of present LED sending card is generally DVI (the Digital VisualInterface of use standard, digital visual interface) or HDMI (High Definition Multimedia Interface, HDMI (High Definition Multimedia Interface)) realization.But when needs transmitting image is larger, the hardware circuit of existing LED sending card subtending port is more complicated, often more problems during debugging.
Summary of the invention
Based on this, be necessary for the problems referred to above, a kind of hardware circuit simple LED sending card subtending port is provided.
A kind of LED sending card subtending port, comprise the link layer on physical layer and FPGA, physical layer comprises the first connector, balancing chip, the second connector, and link layer comprises SERDES IP kernel, data solution binding module, data decode module, the first clock zone modular converter, second clock territory modular converter, data coding module;
First connector receives the view data of upper level sending card or signal source transmission, and view data is sent to balancing chip by each SERDES link; Balancing chip carries out equilibrium treatment to view data, and the view data after equilibrium treatment is sent to SERDES IP kernel by each SERDES link; SERDES IP kernel processes equilibrium treatment Hou Ge road view data, and process Hou Ge road view data is sent to data solution binding module; Alignment Hou Ge road view data according to the passage binding Ma Jiangge road view data alignment in the view data of process Hou Ge road, and is sent to data decode module by data solution binding module; Control code element in the view data of alignment Hou Ge road is rejected by data decode module, obtains RGB data, and sends to the first clock zone modular converter; RGB data is transformed into the clock zone of FPGA application side by the first clock zone modular converter;
Second clock territory modular converter receives the image RGB data that FPGA application side sends to link layer, image RGB data is transformed into the clock zone of SERDES IP kernel, and sends to data coding module; Data coding module is carried out coded treatment to the image RGB data after clock zone conversion and sends to SERDES IP kernel; The image RGB data of coded treatment is sent to the second connector by each SERDES link by SERDES IP kernel; The image RGB data of reception is sent to next stage sending card by the second connector.
LED sending card subtending port of the present invention, designs based on high speed SERDES interface, and support SERDES serial link, data bandwidth is high, can support that resolution is 3840x2160 and following picture signal cascaded transmission thereof; Comprise physical layer and link layer, simplify the hardware circuit of LED sending card subtending port, reliability is high, is easy to realize.When transmitting image is larger, the defect that LED sending card subtending port circuit is more complicated in prior art, the circuit of the LED sending card subtending port that the present invention realizes is simple, and can ensure the high efficiency of transmission of large view data.
Accompanying drawing explanation
Fig. 1 is the schematic diagram being realized the complete output of picture signal in prior art by the cascade of LED sending card;
Fig. 2 is the structural representation of LED sending card subtending port embodiment of the present invention;
Fig. 3 is the reception schematic diagram of data coding module embodiment of the present invention.
Embodiment
The technical problem solved for a better understanding of the present invention, the technological means taked and the technique effect reached, be described in detail below in conjunction with the embodiment of accompanying drawing to LED sending card subtending port of the present invention.It should be noted that, first, second wording mentioned in literary composition, just to distinguishing same type device, is not limited the order of device and quantity.
As shown in Figure 1, a kind of LED sending card subtending port, comprise physical layer 100 and FPGA (Field-Programmable Gate Array, field programmable gate array) on link layer 200, physical layer 100 comprises the first connector 110, balancing chip 120, second connector 130, link layer 200 comprises SERDES (SERializer/DESerializer, serializer/de-serializers) IP kernel (Intellectual Property core) 210, data solution binding module 220, data decode module 230, first clock zone modular converter 240, second clock territory modular converter 250, data coding module 260,
First connector 110 receives the view data of upper level sending card or signal source transmission, and view data is sent to balancing chip 120 by each SERDES link; Balancing chip 120 pairs of view data carry out equilibrium treatment, and the view data after equilibrium treatment is sent to SERDES IP kernel 210 by each SERDES link; SERDES IP kernel 210 pairs of equilibrium treatment Hou Ge road view data process, and process Hou Ge road view data is sent to data solution binding module 220; Alignment Hou Ge road view data according to the passage binding Ma Jiangge road view data alignment in the view data of process Hou Ge road, and is sent to data decode module 230 by data solution binding module 220; Control code element in the view data of alignment Hou Ge road is rejected by data decode module 230, obtains RGB (RGB) data, and sends to the first clock zone modular converter 240; RGB data is transformed into the clock zone of FPGA application side by the first clock zone modular converter 240;
Second clock territory modular converter 250 receives the image RGB data that FPGA application side sends to link layer, image RGB data is transformed into the clock zone of SERDES IP kernel, and sends to data coding module 260; Image RGB data after data coding module 260 pairs of clock zone conversions is carried out coded treatment and sends to SERDES IP kernel 210; The image RGB data of coded treatment is sent to the second connector 130 by each SERDES link by SERDES IP kernel 210; The image RGB data of reception is sent to next stage sending card by the second connector 130.
LED sending card subtending port provided by the invention designs based on SERDES interface, comprises physical layer and logical layer.SERDES is a kind of point-to-point high-speed serial communication technology of main flow, and the level standard of use is CML.For convenience of description, the LED sending card that Received signal strength source exports data is defined as first order LED sending card, the LED sending card receiving first order LED sending card output data is defined as second level LED sending card, by that analogy.When the LED sending card subtending port shown in Fig. 2 is the subtending port of first order LED sending card, what the first connector 110 received is the view data that signal source sends, when the LED sending card subtending port shown in Fig. 2 is the subtending port of other grade of LED sending card, what the first connector 110 received is the view data that upper level sending card sends.In addition, when the LED sending card subtending port shown in Fig. 2 is the subtending port of afterbody LED sending card, this LED sending card subtending port is only responsible for receiving data, and no longer send data, namely the second connector 130 no longer outwards sends data.
As shown in Figure 2, physical layer 100 comprises the first connector 110, balancing chip 120, second connector 130 etc.First connector 110 and the second connector 120 can adopt the HDMI connector of standard.It should be noted that, use standard HDMI connector just for the ease of making cable, and be not standard HDMI.Balancing chip 120 is used for carrying out equilibrium treatment to the view data received, and existing chip in prior art can be adopted to realize.Between first connector 110 and balancing chip 120, between balancing chip 120 and link layer 200, and between link layer 200 and the second connector 130, adopt SERDES link to carry out transfer of data, data bandwidth is high.If the speed of SERDES link uses 3Gbit/s (Gigabits per second), 4 SERDES links all used by first connector 110 and the second connector 130, then the data rate of cascade port is 12Gbit/s, can support that resolution is 3840x2160 and following image signal transmission thereof.It should be noted that, the present invention is not limited the number of SERDES link and transmission rate.
Link layer 200 realizes in FPGA, and FPGA also comprises other circuit part beyond link layer 200.The function of link layer 200 processes the view data of cascaded transmission, thus make view data be convenient to transmit in SERDES link.The input and output data format of link layer 200 is all the RGB data form of standard, comprises pixel clock, VS (field sync signal), HS (line synchronizing signal), DE (row data valid signal) and 48 pixel datas etc.As shown in Figure 2, link layer 200 comprises SERDES IP kernel 210, data solution binding module 220, data decode module 230, first clock zone modular converter 240, second clock territory modular converter 250, data coding module 260.SERDES IP kernel is the existing hardware unit that FPGA producer is integrated in FPGA inside, comprise High-speed I/O (input and output), high-speed phase-locked loop and each processing links unit, be used for realizing the function such as serioparallel exchange, alignment, clock correction, 8B10B encoding and decoding of serial data on SERDES link, its High-speed I/O for inputting the data of SERDES link transmission, or transfers data to SERDES link.Data solution binding module 220, data decode module 230, first clock zone modular converter 240, second clock territory modular converter 250, data coding module 260 can use verilog language (a kind of fpga logic programming language) to design.
Link layer 200 is responsible for the cascade view data that process balancing chip 120 is inputted by SERDES link, and the cascade view data that FPGA internal applications side direction link layer 200 sends.FPGA application side is the part except LED subtending port.The cascade view data that balancing chip 120 inputs is not necessarily identical with the cascade view data that FPGA application side inputs.
In order to better understand the workflow of link layer 200, physical layer 100 will be received from link layer 200 below and sending data and link layer 200 and send data two aspects to physical layer 100 and be described.
One, link layer 200 receive physical layer 100 send data time workflow:
(11) SERDES IP kernel 210 receives each road serial data that balancing chip 120 is sent by SERDES link, i.e. balancing chip 120 equilibrium treatment Hou Ge road view data, each road serial data is processed, comprise serioparallel exchange, alignment, clock correction and 8B10B decoding etc., then process Hou Ge road view data is sent to data solution binding module 220;
(12) data solution binding module 220 realizes the view data alignment of each road by the passage binding code detected in the view data of each road, and alignment Hou Ge road view data is sent to data decode module 230;
(13) the alignment code etc. that data decode module 230 is rejected in the view data of alignment Hou Ge road controls code element, parses the RGB data comprising VS, HS, DE and 48 pixel datas, and sends to the first clock zone modular converter 240;
The RGB data parsed is transformed into the clock zone of FPGA application side by (14) first clock zone modular converters 240.
Two, workflow when link layer 200 sends data to physical layer 100:
(21) second clock territory modular converter 250 receives the image RGB data that FPGA application side sends to link layer, image RGB data is transformed into the clock zone of SERDES IP kernel, and sends to data coding module 260;
(22) the image RGB data after data coding module 260 pairs of clock zone conversions is carried out coded treatment and sends to SERDES IP kernel 210;
The mode of data coding module 260 pairs of image RGB data coded treatment has multiple, and such as, as shown in Figure 3, described data coding module 260 comprises:
New image data creating unit 2601, for by VS, HS, the DE in clock zone converted images RGB data and 48 pixel data zero paddings, obtain the new view data of 64, low 51 of such as new view data is VS, HS, DE and 48 pixel datas, and high 13 bit data are zero;
Transmitting element 2602, in HS blanking interval time, send alignment code, clock correction code and passage binding code to SERDES IP kernel successively, the time outside HS blanking interval, send described new view data to SERDES IP kernel.Alignment code can be defined as the BC of 8 16 systems, and clock correction code can be defined as the 3C of 8 16 systems, and passage binding code can be defined as the F71C of 4 16 systems.
(23) the image RGB data of coded treatment is sent to the second connector 130 by each SERDES link by SERDES IP kernel 210.Then the image RGB data of reception is sent to next stage sending card by the second connector 130.
The present invention is based on high speed SERDES interface to design, support SERDES serial link, data bandwidth is high, can support that resolution is 3840x2160 and following picture signal cascaded transmission thereof; Comprise physical layer and link layer, simplify the hardware circuit of LED sending card subtending port, reliability is high, is easy to realize.When transmitting image is larger, the defect that LED sending card subtending port circuit is more complicated in prior art, the circuit of the LED sending card subtending port that the present invention realizes is simple, and can ensure the high efficiency of transmission of large view data.
Each technical characteristic of the above embodiment can combine arbitrarily, for making description succinct, the all possible combination of each technical characteristic in above-described embodiment is not all described, but, as long as the combination of these technical characteristics does not exist contradiction, be all considered to be the scope that this specification is recorded.
The above embodiment only have expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but can not therefore be construed as limiting the scope of the patent.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (6)
1. a LED sending card subtending port, it is characterized in that, comprise the link layer on physical layer and FPGA, physical layer comprises the first connector, balancing chip, the second connector, and link layer comprises SERDES IP kernel, data solution binding module, data decode module, the first clock zone modular converter, second clock territory modular converter, data coding module;
First connector receives the view data of upper level sending card or signal source transmission, and view data is sent to balancing chip by each SERDES link; Balancing chip carries out equilibrium treatment to view data, and the view data after equilibrium treatment is sent to SERDES IP kernel by each SERDES link; SERDES IP kernel processes equilibrium treatment Hou Ge road view data, and process Hou Ge road view data is sent to data solution binding module; Alignment Hou Ge road view data according to the passage binding Ma Jiangge road view data alignment in the view data of process Hou Ge road, and is sent to data decode module by data solution binding module; Control code element in the view data of alignment Hou Ge road is rejected by data decode module, obtains RGB data, and sends to the first clock zone modular converter; RGB data is transformed into the clock zone of FPGA application side by the first clock zone modular converter;
Second clock territory modular converter receives the image RGB data that FPGA application side sends to link layer, image RGB data is transformed into the clock zone of SERDES IP kernel, and sends to data coding module; Data coding module is carried out coded treatment to the image RGB data after clock zone conversion and sends to SERDES IP kernel; The image RGB data of coded treatment is sent to the second connector by each SERDES link by SERDES IP kernel; The image RGB data of reception is sent to next stage sending card by the second connector.
2. LED sending card subtending port according to claim 1, it is characterized in that, described data coding module comprises:
New image data creating unit, for by VS, HS, the DE in clock zone converted images RGB data and 48 pixel data zero paddings, obtains new view data;
Transmitting element, in HS blanking interval time, send alignment code, clock correction code and passage binding code to SERDES IP kernel successively, the time outside HS blanking interval, send described new view data to SERDES IP kernel.
3. LED sending card subtending port according to claim 2, is characterized in that, low 51 of described new view data is VS, HS, DE and 48 pixel datas, and high 13 bit data are zero.
4. LED sending card subtending port according to claim 2, it is characterized in that, described alignment code is defined as the BC of 8 16 systems, and described clock correction code is defined as the 3C of 8 16 systems, and described passage binding code is defined as the F71C of 4 16 systems.
5. LED sending card subtending port according to claim 1, is characterized in that, described SERDESIP checks equilibrium treatment Hou Ge road view data and carries out serioparallel exchange, alignment, clock correction and 8B10B decoding.
6. the LED sending card subtending port according to claim 1 to 5 any one, is characterized in that, described first connector and described second connector are HDMI connector.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510107125.9A CN104717440B (en) | 2015-03-11 | 2015-03-11 | LED sending card subtending ports |
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| CN201510107125.9A CN104717440B (en) | 2015-03-11 | 2015-03-11 | LED sending card subtending ports |
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| CN104717440A true CN104717440A (en) | 2015-06-17 |
| CN104717440B CN104717440B (en) | 2017-12-08 |
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| CN111600813A (en) * | 2020-05-13 | 2020-08-28 | 中国人民解放军国防科技大学 | Multi-mode interconnection interface controller for converged network |
| CN113096591A (en) * | 2021-06-08 | 2021-07-09 | 成都成电光信科技股份有限公司 | LED display video transmission method |
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Address after: Kezhu road high tech Industrial Development Zone, Guangzhou city of Guangdong Province, No. 233 510670 Patentee after: Wei Chong group Limited by Share Ltd Address before: 510670 Guangdong city of Guangzhou province Kezhu Guangzhou high tech Industrial Development Zone, Road No. 233 Patentee before: Guangdong Weichuangshixun Science and Technology Co., Ltd. |
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