CN104717440B - LED sending card subtending ports - Google Patents
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Abstract
The present invention relates to a kind of LED sending cards subtending port, including physical layer and link layer, physical layer includes the first connector, balancing chip, the second connector, and link layer includes SERDES IP kernels, data solution binding module, data decoder module, the first clock zone modular converter, second clock domain modular converter, data coding module.The present invention is designed based on high speed SERDES interfaces, supports SERDES serial links, data bandwidth height；Including physical layer and link layer, the hardware circuit of LED sending card subtending ports is simplified, reliability is high, it is easy to accomplish.When transmission image is larger, the circuit for the LED sending card subtending ports realized compared to the defects of LED sending cards subtending port circuit is more complicated in the prior art, the present invention is simple, and can guarantee that the high efficiency of transmission of big view data.
Description
Technical field
The present invention relates to LED display system technical field, more particularly to a kind of LED sending cards subtending port.
Background technology
LED (light emitting diode) sending card is the pith of LED display system.The function of LED sending cards includes：Receive
The image or vision signal that signal source is sent, reception card is sent to after caching；It is responsible for the control to whole LED display system
System.In addition sending card has also needed to cascade function.When the maximum image resolution ratio of sending card output is less than input image resolution
When, it is necessary to be cascaded with other sending cards so as to completing the display of input picture.For example, the resolution ratio of input picture is
1920x960, the maximum output ability of sending card is 960x960, thus needs 2 pieces of sending cards mutually to cascade and could export
1920x960 image.As shown in figure 1, sending card A receives 1920x960 picture signals, the left-half of picture signal is cut
The left-half of LED walls is sent to, 1920x960 picture signals are sent to sending card B by sending card A by subtending port, are sent
The right half part of card B cutting picture signals is sent to the right half part of LED walls, so as to realize the complete output of picture signal.
The cascade function of present LED sending cards be usually using standard DVI (Digital Visual Interface,
Digital visual interface) or HDMI (High Definition Multimedia Interface, HDMI)
Realize.But when need to transmit image it is larger when, the hardware circuit of existing LED sending cards subtending port is more complicated, during debugging
Often more problems.
The content of the invention
Based on this, it is necessary in view of the above-mentioned problems, providing a kind of hardware circuit simple LED sending cards subtending port.
A kind of LED sending cards subtending port, including the link layer in physical layer and FPGA, physical layer include the first connection
Device, balancing chip, the second connector, link layer include SERDES IP kernels, data solution binding module, data decoder module, first
Clock zone modular converter, second clock domain modular converter, data coding module；
First connector receives the view data that upper level sending card or signal source are sent, and view data is passed through each
SERDES links are sent to balancing chip；Balancing chip carries out equilibrium treatment to view data, by the picture number after equilibrium treatment
Sent according to by each SERDES links to SERDES IP kernels；SERDES IP kernels are carried out to equilibrium treatment Hou Ge roads view data
Processing, processing Hou Ge roads view data is sent to data solution binding module；Data unbind cover half root tuber according to processing Hou Ge roads
Passage binding Ma Jiangge roads view data alignment in view data, and alignment Hou Ge roads view data is sent to data solution
Code module；Data decoder module rejects the control symbol in Hou Ge roads view data of aliging, and obtains RGB data, and send
To the first clock zone modular converter；RGB data is transformed into the clock zone of FPGA application sides by the first clock zone modular converter；
Second clock domain modular converter receives the image RGB data that FPGA applies lateral link layer to send, by image RGB numbers
According to being transformed into the clock zone of SERDES IP kernels, and it is sent to data coding module；After data coding module is changed to clock zone
Image RGB data carries out coded treatment and is sent to SERDES IP kernels；SERDES IP kernels are by the image RGB data of coded treatment
Sent by each SERDES links to the second connector；The image RGB data of reception is sent to next stage hair by the second connector
Card feed.
LED sending cards subtending port of the present invention, it is designed based on high speed SERDES interfaces, supports SERDES serial chains
Road, data bandwidth is high, and it is 3840x2160 and its following picture signal cascaded transmission that can support resolution ratio；Including physical layer and
Link layer, simplifies the hardware circuit of LED sending card subtending ports, and reliability is high, it is easy to accomplish.When transmission image is larger,
Compared to the defects of LED sending cards subtending port circuit is more complicated in the prior art, the LED sending cards level connection that the present invention realizes
The circuit of mouth is simple, and can guarantee that the high efficiency of transmission of big view data.
Brief description of the drawings
Fig. 1 is to cascade the schematic diagram for realizing that picture signal completely exports by LED sending cards in the prior art；
Fig. 2 is the structural representation of LED sending cards subtending port embodiment of the present invention；
Fig. 3 is the reception schematic diagram of data coding module embodiment of the present invention.
Embodiment
In order to be better understood from present invention solves the technical problem that, the technological means taken and the technique effect reached, under
Face is described in detail with reference to accompanying drawing to the embodiment of LED sending cards subtending port of the present invention.It should be noted that in text
First, second wording referred to is not limited just to distinguish same type device to the order and quantity of device.
As shown in figure 1, a kind of LED sending cards subtending port, including physical layer 100 and FPGA (Field-
Programmable Gate Array, field programmable gate array) on link layer 200, physical layer 100 include first connection
Device 110, balancing chip 120, the second connector 130, link layer 200 include SERDES (SERializer/DESerializer,
Serializer/de-serializers) IP kernel (Intellectual Property core) 210, data solution binding module 220, data decoding
Module 230, the first clock zone modular converter 240, second clock domain modular converter 250, data coding module 260；
First connector 110 receives the view data that upper level sending card or signal source are sent, and view data is passed through each
SERDES links are sent to balancing chip 120；Balancing chip 120 carries out equilibrium treatment to view data, after equilibrium treatment
View data is sent to SERDES IP kernels 210 by each SERDES links；SERDES IP kernels 210 are to equilibrium treatment Hou Ge roads
View data is handled, and processing Hou Ge roads view data is sent to data solution binding module 220；Data solution binding module
220 passage in the view data of processing Hou Ge roads binds the view data alignment of Ma Jiangge roads, and will alignment Hou Ge roads figure
As data are sent to data decoder module 230；Data decoder module 230 is by the control symbol in Hou Ge roads view data of aliging
Reject, obtain RGB (RGB) data, and be sent to the first clock zone modular converter 240；First clock zone modular converter 240
RGB data is transformed into the clock zone of FPGA application sides；
Second clock domain modular converter 250 receives the image RGB data that FPGA applies lateral link layer to send, by image
RGB data is transformed into the clock zone of SERDES IP kernels, and is sent to data coding module 260；Data coding module 260 to when
Image RGB data after the conversion of clock domain carries out coded treatment and is sent to SERDES IP kernels 210；SERDES IP kernels 210 will be compiled
The image RGB data of code processing is sent to the second connector 130 by each SERDES links；Second connector 130 is by reception
Image RGB data is sent to next stage sending card.
LED sending cards subtending port provided by the invention is designed based on SERDES interfaces, including physical layer and logic
Layer.SERDES is a kind of point-to-point high-speed serial communication technology of main flow, and the level standard used is CML.Retouch for convenience
State, the LED sending cards of reception signal source output data are defined as first order LED sending cards, first order LED sending cards will be received
The LED sending cards of output data are defined as second level LED sending cards, by that analogy.When the LED sending cards level connection shown in Fig. 2
When mouth is the subtending port of first order LED sending cards, what the first connector 110 received is the view data that signal source is sent, when
When LED sending card subtending ports shown in Fig. 2 are the subtending ports of other grades of LED sending cards, what the first connector 110 received is
The view data that upper level sending card is sent.In addition, when the LED sending card subtending ports shown in Fig. 2 are that afterbody LED is sent
During the subtending port of card, this LED sending cards subtending port is only responsible for receiving data, does not retransmit data, i.e. the second connector 130
No longer it is sent out data.
As shown in Fig. 2 physical layer 100 includes the first connector 110, balancing chip 120, second connector 130 etc..First
The connector 120 of connector 110 and second can use the HDMI connector of standard.It should be noted that connected using standard HDMI
Device is connect only to facilitate making cable, and be not standard HDMI.Balancing chip 120 is used for the view data to reception
Equilibrium treatment is carried out, existing chip realization in the prior art can be used.Between first connector 110 and balancing chip 120,
Between balancing chip 120 and link layer 200, and between the connector 130 of link layer 200 and second, entered using SERDES links
Row data transfer, data bandwidth are high.If the speed of SERDES links uses 3Gbit/s (Gigabits per second), the first connector 110
With the second connector 130 with 4 SERDES links, then the data rate of cascade port is 12Gbit/s, can support that resolution ratio is
3840x2160 and its transmission of following picture signal.It should be noted that the present invention not the bar number to SERDES links and
Transmission rate is limited.
Link layer 200 realizes that FPGA also includes other circuit parts beyond link layer 200 in FPGA.Link layer 200
Function be that the view data of cascaded transmission is handled so that view data is easy to transmit in SERDES links.Chain
The input of road floor 200 and output data form are all the RGB data forms of standard, including pixel clock, VS (field sync signal),
HS (line synchronising signal), DE (row data valid signal) and 48 pixel datas etc..As shown in Fig. 2 link layer 200 includes
When SERDES IP kernels 210, data solution binding module 220, data decoder module 230, the first clock zone modular converter 240, second
Clock domain modular converter 250, data coding module 260.SERDES IP kernels are the existing hardwares that FPGA producers are integrated in inside FPGA
Unit, including High-speed I/O (input and output), high-speed phase-locked loop and each processing links unit, it is serial on SERDES links for realizing
The functions such as the serioparallel exchanges of data, alignment, clock correction, 8B10B encoding and decoding, its High-speed I/O are used to input SERDES links
The data of transmission, or transfer data to SERDES links.When data solution binding module 220, data decoder module 230, first
Clock domain modular converter 240, second clock domain modular converter 250, data coding module 260 can use verilog language (a kind of
Fpga logic programming language) it is designed.
Link layer 200 is responsible for the cascade view data that processing balancing chip 120 is inputted by SERDES links, and FPGA
The cascade view data that the lateral link layer 200 of internal applications is sent.FPGA application sides are the part in addition to LED subtending ports.
The cascade view data that balancing chip 120 inputs and the cascade view data that FPGA application sides input are not necessarily identical.
In order to be better understood from the workflow of link layer 200, it will receive physical layer 100 from link layer 200 below and send
Data and link layer 200 illustrate in terms of physical layer 100 sends data two.
The workflow during data that the first, the reception of link layer 200 physical layer 100 is sent：
(11) SERDES IP kernels 210 receive each road serial data that balancing chip 120 is sent by SERDES links, i.e.,
The equilibrium treatment Hou Ge roads view data of balancing chip 120, is handled each road serial data, including serioparallel exchange, character
Alignment, clock correction and 8B10B decodings etc., then processing Hou Ge roads view data is sent to data solution binding module 220；
(12) data solution binding module 220 realizes each road picture number by detecting the binding code of the passage in each road view data
Data decoder module 230 is sent to according to alignment, and by alignment Hou Ge roads view data；
(13) data decoder module 230 rejects the control symbols such as the alignment code in the view data of alignment Hou Ge roads,
The RGB data comprising VS, HS, DE and 48 pixel datas is parsed, and is sent to the first clock zone modular converter 240；
The RGB data parsed is transformed into the clock zone of FPGA application sides by (14) first clock zone modular converters 240.
2nd, link layer 200 to physical layer 100 send data when workflow：
(21) second clock domain modular converter 250 receives the image RGB data that FPGA applies lateral link layer to send, and will scheme
As RGB data is transformed into the clock zone of SERDES IP kernels, and it is sent to data coding module 260；
(22) the image RGB data after data coding module 260 is changed to clock zone carries out coded treatment and is sent to
SERDES IP kernels 210；
Data coding module 260 have to the mode of image RGB data coded treatment it is a variety of, for example, as shown in figure 3, described
Data coding module 260 includes：
New image data creating unit 2601, for by VS, HS, DE in clock zone converted images RGB data and
48 pixel data zero paddings, the new view data of 64 is obtained, such as low 51 of new view data is VS, HS, DE and 48
Position pixel data, high 13 data are zero；
Transmitting element 2602, during in HS blanking intervals, send alignment code, clock to SERDES IP kernels successively
Correcting code and passage binding code, the time outside HS blanking intervals, the new view data are sent to SERDES IP kernels.Word
Symbol alignment code can be defined as the BC of 8 16 systems, and clock correction code can be defined as the 3C of 8 16 systems, passage binding code
The F71C of 4 16 systems can be defined as.
(23) the image RGB data of coded treatment is sent to second and connected by SERDES IP kernels 210 by each SERDES links
Connect device 130.Then the image RGB data of reception is sent to next stage sending card by the second connector 130.
The present invention is designed based on high speed SERDES interfaces, supports SERDES serial links, data bandwidth is high, can support
Resolution ratio is 3840x2160 and its following picture signal cascaded transmission；Including physical layer and link layer, LED transmissions are simplified
The hardware circuit of card subtending port, reliability are high, it is easy to accomplish.When transmission image is larger, sent out compared to LED in the prior art
The defects of card feed subtending port circuit is more complicated, the circuit for the LED sending card subtending ports that the present invention realizes is simple, and can guarantee that
The high efficiency of transmission of big view data.
Each technical characteristic of embodiment described above can be combined arbitrarily, to make description succinct, not to above-mentioned reality
Apply all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, the scope that this specification is recorded all is considered to be.
Embodiment described above only expresses the several embodiments of the present invention, and its description is more specific and detailed, but simultaneously
Can not therefore it be construed as limiting the scope of the patent.It should be pointed out that come for one of ordinary skill in the art
Say, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the protection of the present invention
Scope.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (6)
1. a kind of LED sending cards subtending port, it is characterised in that including the link layer in physical layer and FPGA, physical layer includes
First connector, balancing chip, the second connector, link layer include SERDES IP kernels, data solution binding module, data decoding
Module, the first clock zone modular converter, second clock domain modular converter, data coding module；
First connector receives the view data that upper level sending card or signal source are sent, and view data is passed through into each SERDES chains
Road is sent to balancing chip；Balancing chip carries out equilibrium treatment to view data, the view data after equilibrium treatment is passed through each
SERDES links are sent to SERDES IP kernels；SERDES IP kernels are handled equilibrium treatment Hou Ge roads view data, will
Processing Hou Ge roads view data is sent to data solution binding module；Data unbind cover half root tuber according to processing Hou Ge roads view data
In the view data alignment of passage binding Ma Jiangge roads, and alignment Hou Ge roads view data is sent to data decoder module；
Data decoder module rejects the control symbol in Hou Ge roads view data of aliging, when obtaining RGB data, and being sent to first
Clock domain modular converter；RGB data is transformed into the clock zone of FPGA application sides by the first clock zone modular converter；
Second clock domain modular converter receives the image RGB data that FPGA applies lateral link layer to send, and image RGB data is turned
The clock zone of SERDES IP kernels is changed to, and is sent to data coding module；Data coding module is to the image after clock zone conversion
RGB data carries out coded treatment and is sent to SERDES IP kernels；SERDES IP kernels pass through the image RGB data of coded treatment
Each SERDES links are sent to the second connector；The image RGB data of reception is sent to next stage sending card by the second connector.
2. LED sending cards subtending port according to claim 1, it is characterised in that the data coding module includes：
New image data creating unit, for the field sync signal VS in clock zone converted images RGB data, row is synchronous
Signal HS, row data valid signal DE and 48 pixel data zero paddings, obtain new view data；
Transmitting element, during in HS blanking intervals, successively to SERDES IP kernels send alignment code, clock correction code and
Passage binds code, the time outside HS blanking intervals, the new view data is sent to SERDES IP kernels.
3. LED sending cards subtending port according to claim 2, it is characterised in that the new view data is low 51
For VS, HS, DE and 48 pixel datas, high 13 data are zero.
4. LED sending cards subtending port according to claim 2, it is characterised in that the alignment code is defined as 8
The BC of 16 systems, the clock correction code are defined as the 3C of 8 16 systems, and the passage binding code is defined as 4 16 systems
F71C。
5. LED sending cards subtending port according to claim 1, it is characterised in that the SERDES IP kernels to equilibrium at
Li Houge roads view data carries out serioparallel exchange, alignment, clock correction and 8B10B decodings.
6. the LED sending card subtending ports according to claim 1 to 5 any one, it is characterised in that first connection
Device and second connector are HDMI connector.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510107125.9A CN104717440B (en) | 2015-03-11 | 2015-03-11 | LED sending card subtending ports |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510107125.9A CN104717440B (en) | 2015-03-11 | 2015-03-11 | LED sending card subtending ports |
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| CN104717440A CN104717440A (en) | 2015-06-17 |
| CN104717440B true CN104717440B (en) | 2017-12-08 |
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| CN201510107125.9A Active CN104717440B (en) | 2015-03-11 | 2015-03-11 | LED sending card subtending ports |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111600813B (en) * | 2020-05-13 | 2021-10-29 | 中国人民解放军国防科技大学 | Multi-mode interconnection interface controller for converged network |
| CN113096591B (en) * | 2021-06-08 | 2021-08-27 | 成都成电光信科技股份有限公司 | LED display video transmission method |
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| CN101242284A (en) * | 2008-03-20 | 2008-08-13 | 杭州华三通信技术有限公司 | Communication method and network device based on SPI bus |
| CN103745682A (en) * | 2013-07-03 | 2014-04-23 | 上海视恒电子科技有限公司 | Method of asynchronous cascade |
| CN104267638A (en) * | 2014-09-19 | 2015-01-07 | 北京空间机电研究所 | Serializer/deserializer clock source based on clock managers and FPGA |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7839307B2 (en) * | 2008-04-04 | 2010-11-23 | Gennum Corporation | Video serializer and deserializer with mapping conversion |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101242284A (en) * | 2008-03-20 | 2008-08-13 | 杭州华三通信技术有限公司 | Communication method and network device based on SPI bus |
| CN103745682A (en) * | 2013-07-03 | 2014-04-23 | 上海视恒电子科技有限公司 | Method of asynchronous cascade |
| CN104267638A (en) * | 2014-09-19 | 2015-01-07 | 北京空间机电研究所 | Serializer/deserializer clock source based on clock managers and FPGA |
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Address after: Kezhu road high tech Industrial Development Zone, Guangzhou city of Guangdong Province, No. 233 510670 Patentee after: Wei Chong group Limited by Share Ltd Address before: 510670 Guangdong city of Guangzhou province Kezhu Guangzhou high tech Industrial Development Zone, Road No. 233 Patentee before: Guangdong Weichuangshixun Science and Technology Co., Ltd. |