CN208063339U - A kind of vision signal parser circuitry, vision signal resolver and sending card - Google Patents

Abstract

A kind of vision signal parser circuitry of the application offer, vision signal resolver and sending card, the vision signal parser circuitry include the first signal conversion module and second signal conversion module；Wherein：First signal conversion module for the HDMI2.0 signals of input to be converted to HDMI1.4 signals, and the HDMI1.4 signals is exported to the second signal conversion module；The second signal conversion module for the HDMI1.4 signals of input to be converted to parallel port data, and exports the parallel port data.Identification and processing of the fpga chip to HDMI2.0 signals may be implemented in the vision signal parser circuitry.

Description

A kind of vision signal parser circuitry, vision signal resolver and sending card

Technical field

This application involves LED (Light Emitting Diode, light emitting diode) display screen display technologies, more particularly to A kind of vision signal parser circuitry, vision signal resolver and sending card.

Background technology

4K@60HZ (pictures of 60 frame 3840*2160 resolution ratio of transmission per second) LED sending cards are a kind of support HDMI (High Definition Multimedia Interface, high-definition multimedia interface) 2.0 or DP (Display Port, display interface) a kind of (high-definition digital display interface standard) 1.2 signal 4K@60HZ accesses sending card.

Currently, sending card master control generally use the higher FPGA of performance (Field-Programmable Gate Array, Field programmable gate array) chip be kernel processor chip, therefore, how to enable FPGA identify and handle HDMI2.0 or The signal of DP1.2 agreements becomes the technical issues of 4K@60HZ LED sending cards realize a faced urgent need to resolve.

Invention content

In view of this, a kind of vision signal parser circuitry of the application offer, vision signal resolver and sending card.

Specifically, the application is achieved by the following technical solution：

According to the embodiment of the present application in a first aspect, providing a kind of vision signal parser circuitry, which is characterized in that including One signal conversion module and second signal conversion module；Wherein：

First signal conversion module, for being converted to the high-definition multimedia interface HDMI2.0 signals of input HDMI1.4 signals, and the HDMI1.4 signals are exported to the second signal conversion module；

The second signal conversion module, for the HDMI1.4 signals of input to be converted to parallel port data, and described in output Parallel port data.

Optionally, first signal conversion module, be specifically used for the HDMI2.0 signals that will input by odd even, it is upper and lower or Left and right is divided into two HDMI1.4 signals, and the HDMI1.4 signals are exported to the second signal conversion module.

Optionally, the vision signal parser circuitry further includes third signal conversion module；Wherein：

The third signal conversion module, for the display interface DP1.2 signals of input to be converted to HDMI2.0 signals, And the HDMI2.0 signals are exported to first signal conversion module.

According to the second aspect of the embodiment of the present application, a kind of vision signal resolver, including above-mentioned vision signal are provided Parser circuitry.

Optionally, the input terminal of the output end of the vision signal resolver and fpga chip connects.

According to the third aspect of the embodiment of the present application, provide a kind of sending card, including above-mentioned vision signal parser circuitry and Fpga chip；Wherein：

The fpga chip, the parallel port data for receiving the vision signal parser circuitry output, according to preset protocol The parallel port data of input are handled, and export treated data.

Optionally, the sending card further includes PHY chip；Wherein：

The fpga chip, specifically for data are exported to the PHY chip by treated；

The PHY chip, for treated by described in, data processing is data packet, and sends the data Packet.

Optionally, the fpga chip, specifically for passing through serializer/decoder SD, by treated, data are exported to institute State PHY chip.

The vision signal parser circuitry of the embodiment of the present application, by being arranged for HDMI2.0 signals to be converted to HDMI1.4 First signal conversion module of signal, and HDMI1.4 signals for exporting the first signal conversion module are converted to parallel port Data, and the second signal conversion module of parallel port data is exported, realize identification and place of the fpga chip to HDMI2.0 signals Reason.

Description of the drawings

Fig. 1 is a kind of schematic diagram of vision signal parser circuitry shown in one exemplary embodiment of the application；

Fig. 2 is a kind of schematic diagram of vision signal parser circuitry shown in the application another exemplary embodiment；

Fig. 3 is a kind of structural schematic diagram of sending card shown in one exemplary embodiment of the application；

Fig. 4 is a kind of structural schematic diagram of sending card shown in the application another exemplary embodiment；

Fig. 5 is a kind of structural schematic diagram of sending card shown in one exemplary embodiment of the application.

Specific implementation mode

Example embodiments are described in detail here, and the example is illustrated in the accompanying drawings.Following description is related to When attached drawing, unless otherwise indicated, the same numbers in different drawings indicate the same or similar elements.Following exemplary embodiment Described in embodiment do not represent all embodiments consistent with the application.On the contrary, they be only with it is such as appended The example of consistent device and method of some aspects be described in detail in claims, the application.

It is the purpose only merely for description specific embodiment in term used in this application, is not intended to be limiting the application. It is also intended to including majority in the application and "an" of singulative used in the attached claims, " described " and "the" Form, unless context clearly shows that other meanings.

In order to make those skilled in the art more fully understand technical solution provided by the embodiments of the present application, and keep the application real The above objects, features, and advantages for applying example can be more obvious and easy to understand, below in conjunction with the accompanying drawings to technical side in the embodiment of the present application Case is described in further detail.

Fig. 1 is referred to, is a kind of schematic diagram of vision signal parser circuitry provided by the embodiments of the present application, as shown in Figure 1, The vision signal parser circuitry may include the first signal conversion module 110 and second signal conversion module 120；Wherein：

First signal conversion module 110, for the HDMI2.0 signals of input to be converted to HDMI1.4 signals, and should HDMI1.4 signals are exported to second signal conversion module 120；

Second signal conversion module 120 for the HDMI1.4 signals of input to be converted to parallel port data, and exports this simultaneously Mouth data.

In the embodiment of the present application, it in order to enable the HDMI2.0 signals of input to be identified and be handled by fpga chip, is inciting somebody to action HDMI2.0 signals input before fpga chip, can HDMI2.0 signals be first converted to the parallel port number that fpga chip can identify According to for example, RGB (Red, Green, Blue, RGB) data (are referred to as VP (Video Pixel, video pixel) data (data), HV (Horizontal/Vertical, row field) control signal.

Specifically, in the embodiment of the present application, for the HDMI2.0 signals of input (maximum 6Gb/s per channel, 6Gb is per second per channel), the first signal conversion module 110 can be first passed through and be converted into HDMI1.4 signals (maximum 3Gb/s Per channel), and the HDMI1.4 signals are exported to second signal conversion module 120, in turn, second signal conversion module The HDMI1.4 signals of input can be converted to parallel port data by 120, and export the parallel port data, for example, the parallel port data are defeated Go out to fpga chip, the parallel port data are identified and are handled by fpga chip.

Wherein, the first signal conversion module 110 can include but is not limited to support the integrated electricity of the bimodulus of full bandwidth HDMI2.0 Road (Integrated Circuit, abbreviation IC), such as full bandwidth HDMI 2.0/MHL (Mobile High-Definition Link, mobile terminal high-definition audio and video standard interface) 3.0 bimodulus IC, the HDMI2.0 signals of input can be converted to HDMI1.4 Signal；Second signal conversion module 120 can include but is not limited to HDMI1.4 receiver IC, as HDMI1.4 4K-RGB are converted HDMI1.4 signals can be converted to parallel port data by chip.

In the embodiment of the present application, since HDMI2.0 signals are 4K@60HZ signals, and HDMI1.4 signal 4K@30HZ signals, Therefore, a HDMI2.0 signal can be converted into two HDMI1.4 signals.

Correspondingly, in the embodiment of the present application, the output end of each the first signal conversion module 110 can connect two One HDMI2.0 signal is converted to two HDMI1.4 signals by second signal conversion module 120, the first signal conversion module 110 Later, it can export respectively and give two second signal conversion modules 120, be distinguished by two second signal conversion modules 120 The HDMI1.4 signals of input are converted into parallel port data, and are exported to fpga chip.

The application in one embodiment, the first signal conversion module 110 can be specifically used for inputting HDMI2.0 signals are divided into two HDMI1.4 signals, and the HDMI1.4 signals are exported to second by odd even, upper and lower or left and right Signal conversion module.

Further, in the embodiment of the present application, in order to make the DP1.2 signals of input that can also be identified by fpga chip, Before DP1.2 signals are inputted fpga chip, DP1.2 signals can be also converted into the parallel port number that fpga chip can identify According to.

Correspondingly, refer to Fig. 2, the application in one embodiment, vision signal parser circuitry can also include Third signal conversion module 130；Wherein：

Third signal conversion module 130, for the DP1.2 signals of input to be converted to HDMI2.0 signals, and should HDMI2.0 vision signals are exported to the first signal conversion module 110.

In this embodiment, for the DP1.2 signals of input, can first pass through third signal conversion module 130 should DP1.2 signals are converted to HDMI2.0 signals, and the HDMI2.0 signals are exported to the first signal conversion module 110.

After first signal conversion module 110 receives the HDMI2.0 signals of input, HDMI1.4 can be converted into Signal, and export to second signal conversion module 120, parallel port data are converted by second signal conversion module 120, and defeated Go out the parallel port data, such as output is to fpga chip.

Wherein, third signal conversion module 130 can include but is not limited to PS and turn HDMI2.0 conversion chips, can will PS1.2 signals are converted to HDMI2.0 signals.

As it can be seen that in the embodiment of the present application, it, can be by input by vision signal parser circuitry shown in FIG. 1 HDMI2.0 signals are converted to parallel port data, and export to fpga chip, and the HDMI2.0 signals to realize input can be by Fpga chip identifies and processing.

In addition, by vision signal parser circuitry shown in Fig. 2, further the DP1.2 signals of input also can also be turned Parallel port data are changed to, and are exported to fpga chip, the DP1.2 signals to realize input can be identified and be located by fpga chip Reason.

Further, the embodiment of the present application also provides a kind of vision signal resolver, which can To include vision signal parser circuitry shown in fig. 1 or fig. 2.

In one embodiment, the input terminal of the output end of the vision signal resolver and fpga chip connects.

In this embodiment, above-mentioned vision signal resolver can be as between video signal source and fpga chip Transferring device.

Specifically, the input terminal of the output end of the vision signal resolver and fpga chip can be connected, video letter The vision signal of number source output, the input terminal as HDMI2.0 signals or DP1.2 signals pass through the vision signal resolver input The vision signal resolver, vision signal resolver are converted into the manner described above by vision signal parser circuitry Parallel port data, and exporting to fpga chip (such as fpga chip of 4K@60HZ sending cards), by by HDMI2.0 signals or DP1.2 Signal is converted to the signal that fpga chip can be identified and be handled, realize the fpga chip of sending card to HDMI2.0 signals or The identification and processing of DP1.2 signals.

Fig. 3 is referred to, is a kind of structural schematic diagram of sending card provided by the embodiments of the present application, as shown in figure 3, the transmission Card may include vision signal parser circuitry 310 and fpga chip 320；Wherein：

The structure of the vision signal parser circuitry can be as shown in Figure 1 or 2；

Fpga chip 320, the parallel port data for receiving the output of vision signal parser circuitry, according to preset protocol to input Parallel port data handled, and export treated data.

In the embodiment of the present application, for the HDMI2.0 signals of input, sending card can pass through video shown in fig. 1 or fig. 2 Signal resolution circuit 310 is converted into parallel port data, and obtained parallel port data are exported to fpga chip 320.

For the DP1.2 signals of input, sending card can by vision signal parser circuitry 310 as shown in Figure 2 by its Parallel port data are converted to, and obtained parallel port data are exported to fpga chip 320.

When fpga chip 320 receives parallel port data, it can be handled according to preset protocol (i.e. Protocol), and defeated The data that go out that treated.

Refer to Fig. 4, the application in one embodiment, above-mentioned sending card can also include PHY (physical layer) core Piece 330；Wherein：

Fpga chip 320, can be specifically for by treated, data are exported to PHY chip 330；

PHY chip 330, can be used for receive treated data processing is data packet, and sends the data packet.

In this embodiment, it after fpga chip 320 is handled parallel port data according to preset protocol, can output it PHY chip 330 (such as gigabit PHY chip) is given, is sent out by PHY chip 330.

When PHY chip 330 receives the data that transmit that treated of fpga chip 320, it can be packaged as counting It according to packet (such as gigabit data packet), and sends, is such as sent to reception card.

In one example, fpga chip 320 can pass through SD (Serializer/Deserializer, serializer/solution String device) (such as 5G SD) data are exported to PHY chip 330 by treated.

It should be noted that it includes storage unit (being not shown) to also need in practical applications, in sending card, such as DDR (Double Data Rate Double Data Rates synchronous DRAM) 3.

As it can be seen that in the embodiment of the present application, being located in advance to the HDMI2.0 signals of input by vision signal parser circuitry Reason allows fpga chip to be identified and handle the HDMI2.0 signals for inputting sending card.

When the structure of vision signal parser circuitry is as shown in Figure 2, fpga chip can also be to the DP1.2 of input sending card Signal is identified and handles.

In order to make those skilled in the art more fully understand technical solution provided by the embodiments of the present application, with reference to specific Example illustrates the operation principle for the sending card that application embodiment provides.

Fig. 5 is referred to, is a kind of structural schematic diagram of sending card provided by the embodiments of the present application, wherein hair shown in fig. 5 The signal processing flow of card feed can be as follows：

One, HDMI2.0 signals

In this embodiment, for the HDMI2.0 signals of input sending card, sending card can pass through vision signal and parse electricity The first signal conversion module in road is by odd even, and left and right is divided into two HDMI1.4 signals/up and down/, and by two HDMI1.4 Signal is exported respectively to two second signal conversion modules.

When second signal conversion module receives HDMI1.4 signals, which can be converted to parallel port number According to, and export to fpga chip.

When fpga chip receives the parallel ports RBG data, it can be handled according to Protocol, and by treated Data are exported by 5G SD and give gigabit PHY chip.

When gigabit PHY chip receives fpga chip transmission treated data, gigabit data can be packaged as Packet, and it is sent to reception card.

Two, DP1.2 signals

In this embodiment, for the DP1.2 signals of input sending card, sending card can pass through third signal conversion module HDMI2.0 signals are converted into, and are exported to the first signal conversion module.

First signal conversion module receive third signal conversion module output HDMI2.0 signals when, can by odd even/ Up and down/left and right is divided into two HDMI1.4 signals, and two HDMI1.4 signals are exported respectively and are turned to two second signals Change the mold block.

When second signal conversion module receives HDMI1.4 signals, which can be converted to parallel port number According to, and export to fpga chip.

When fpga chip receives the parallel ports RBG data, it can be handled according to Protocol, and by treated Data are exported by 5G SD and give gigabit PHY chip.

When gigabit PHY chip receives fpga chip transmission treated data, gigabit data can be packaged as Packet, and it is sent to reception card.

Include the first letter for HDMI2.0 signals to be converted to HDMI1.4 signals by setting in the embodiment of the present application Number conversion module, and HDMI1.4 signals for exporting the first signal conversion module are converted to parallel port data, and export simultaneously The video information parser circuitry of the second signal conversion module of mouth data, realizes identification of the fpga chip to HDMI2.0 signals And processing, and cost of implementation is relatively low.

It should be noted that herein, relational terms such as first and second and the like are used merely to a reality Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those Element, but also include other elements that are not explicitly listed, or further include for this process, method, article or equipment Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that There is also other identical elements in process, method, article or equipment including the element.

The foregoing is merely the preferred embodiments of the application, not limiting the application, all essences in the application With within principle, any modification, equivalent substitution, improvement and etc. done should be included within the scope of the application protection god.

Claims (8)

1. a kind of vision signal parser circuitry, which is characterized in that including the first signal conversion module and second signal conversion module； Wherein：

First signal conversion module, for being converted to the high-definition multimedia interface HDMI2.0 signals of input HDMI1.4 signals, and the HDMI1.4 signals are exported to the second signal conversion module；

The second signal conversion module for the HDMI1.4 signals of input to be converted to parallel port data, and exports the parallel port Data.

2. vision signal parser circuitry according to claim 1, which is characterized in that

First signal conversion module, specifically for the HDMI2.0 signals of input are divided into two by odd even, upper and lower or left and right A HDMI1.4 signals, and the HDMI1.4 signals are exported to the second signal conversion module.

3. vision signal parser circuitry according to claim 1, which is characterized in that further include third signal conversion module； Wherein：

The third signal conversion module, for the display interface DP1.2 signals of input to be converted to HDMI2.0 signals, and will The HDMI2.0 signals are exported to first signal conversion module.

4. a kind of vision signal resolver, which is characterized in that parsed including claim 1-3 any one of them vision signals Circuit.

5. vision signal resolver according to claim 4, which is characterized in that the vision signal resolver it is defeated Outlet is connect with the input terminal of programmable gate array FPGA chip.

6. a kind of sending card, which is characterized in that including vision signal parser circuitry as described in any one of claims 1-3 and can Program gate array FPGA chip；Wherein：

The fpga chip, the parallel port data for receiving the vision signal parser circuitry output, according to preset protocol to defeated The parallel port data entered are handled, and export treated data.

7. sending card according to claim 6, which is characterized in that further include PHY chip；Wherein：

The fpga chip, specifically for data are exported to the PHY chip by treated；

The PHY chip, for treated by described in, data processing is data packet, and sends the data packet.

8. sending card according to claim 7, which is characterized in that

The fpga chip, specifically for passing through serializer/decoder SD, by treated, data are exported to the physical layer PHY Chip.