CN103888693B - Image transmission - Google Patents
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- CN103888693B CN103888693B CN201410129037.4A CN201410129037A CN103888693B CN 103888693 B CN103888693 B CN 103888693B CN 201410129037 A CN201410129037 A CN 201410129037A CN 103888693 B CN103888693 B CN 103888693B
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Abstract
The invention discloses a kind of image transmission, using multipath high-speed serial transceiver simultaneous transmission picture signal all the way, because the bandwidth requirement to high speed serialization transceiver is not high, can be transmitted using the high speed serialization transceiver of low bandwidth, compared to by the way of the transmission of coding and decoding video chip, cost is reduced.When input image data bandwidth is higher, such as ultra high-definition resolution signal, 3D signals etc. can complete transmission by increasing the quantity of high speed serialization transceiver.The present apparatus also carries out Phase synchronization coding in transmitting terminal to picture signal, the Phase synchronization between receiving terminal ensures multichannel transceiver using corresponding measure, it is to avoid the Huaping phenomenon that view data dislocation is caused.
Description
Technical field
The present invention relates to technical field of image processing, more particularly to a kind of image transmission.
Background technology
In image processing field, it is often necessary to which picture signal is transferred into another processing unit from a processing unit.
The method for using at this stage will send regarding for another processing unit generally by video coding chip after image signal encoding
Frequency decoding chip, video decoding chip is used after signal is decoded for local signal treatment, and this method generally needs extra increasing
Plus coding and decoding video chip, the cost of product is increased, the size of simultaneous transmission image is limited by coding and decoding video chip bandwidth
System.
The content of the invention
Based on above-mentioned situation, the present invention proposes a kind of image transmission, to reduce the cost of image transmitting, while protecting
Card transmission quality.Therefore, the scheme for using is as follows.
A kind of image transmission, including transmitting terminal and receiving terminal,
The transmitting terminal includes signal selector, polarity unified modules, clock zone modular converter, Phase synchronization coding mould
Block, and multiple high speed serialization transmitters；
The receiving terminal includes multiple high-speed serial receivers, Phase synchronization module and local signal processing unit；
The resolution ratio of the number of the high-speed serial receiver and the high-speed serial receiver and picture signal to be transmitted
It is adapted with frame per second；
The signal selector sends to the polarity unified modules selected picture signal, and the polarity unifies mould
The polarity unification of the field sync signal of picture signal and line synchronising signal is positive polarity or negative polarity, the clock zone conversion by block
Picture signal of the module by polarity after reunification is transformed into high speed serialization transmitter parallel data input clock domain, the Phase synchronization
Synchronization Control code is inserted coding module the starting position alternate image data of the field synchronization head of each, multiple high speed strings
Row transmitter transmits to multiple high speed serializations the picture signal after Phase synchronization is encoded commonly through transmission link
Receiver；
The multiway images data is activation that multiple high-speed serial receivers will be received is to the Phase synchronization module, institute
State Phase synchronization module to judge whether to read the Synchronization Control code of multiway images data simultaneously, if then sending out multiway images data
Toward the local signal processing unit, if otherwise multiway images data are carried out with Phase synchronization treatment, then the local letter is sent to
Number processing unit.
Image transmission of the present invention, using multipath high-speed serial transceiver simultaneous transmission picture signal all the way, due to right
The bandwidth requirement of high speed serialization transceiver is not high, it is possible to use the high speed serialization transceiver of low bandwidth is transmitted, compared to use
The mode of coding and decoding video chip transmission, reduces cost.When input image data bandwidth is higher, such as ultra high-definition resolution ratio is believed
Number, 3D signals etc. can complete transmission by increasing the quantity of high speed serialization transceiver.The present apparatus is also believed image in transmitting terminal
Number Phase synchronization coding is carried out, the Phase synchronization between receiving terminal ensures multichannel transceiver using corresponding measure, it is to avoid image
The Huaping phenomenon that data dislocation is caused.
Brief description of the drawings
Fig. 1 is the structural representation of image transmission of the present invention；
Fig. 2 is the structural representation of clock zone modular converter in image transmission of the present invention；
Fig. 3 is two structural representations of FIFO memory of Phase synchronization module in image transmission of the present invention；
Fig. 4 carries out phase locked schematic flow sheet for Phase synchronization module.
Specific embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is described in further detail.It should be appreciated that specific embodiment described herein is only used to explain this hair
It is bright, do not limit protection scope of the present invention.
The structure of image transmission of the invention is as shown in figure 1, the multiway images signal of transmitting terminal passes through signal behavior
Device selection is transmitted all the way, and selected picture signal is input to polarity unified modules, due to different input signal sources, figure
The polarity of field sync signal and line synchronising signal as signal may be different, for convenience of back end signal treatment, need to be by field synchronization
Signal and line synchronising signal unification are converted to positive polarity or negative polarity.
Picture signal after dipole inversion is input to clock zone modular converter, because the picture signal being input into can be various
The signal of resolution ratio, the picture signal pixel clock of different resolution is different, and high speed serialization transceiver is in bandwidth one
In the case of fixed, what the input clock of parallel data was to determine, the picture signal of input must be transformed into height to complete to send
Fast serial transceiver parallel data input clock domain.
The structure of clock zone modular converter including one as shown in Fig. 2 write control module, two FIFO and reading controls
Module, writes control module and controls the odd-numbered line of view data to be written to FIFO_a according to the line synchronising signal of input image data,
Even number line is written to FIFO_b, read control module according to the line synchronising signal of input image data alternately from FIFO_a and
View data is read in FIFO_b, when writing control module and writing FIFO_a, read control module reads FIFO_b, when writing control
When module writes FIFO_b, read control module reads FIFO_a.To ensure picture signal（Including field sync signal, line synchronising signal,
Data valid signal and viewdata signal）Clock zone conversion is all carried out, two width of FIFO are all necessary for field synchronization letter
Number, line synchronising signal, the width sum of data valid signal and viewdata signal, depth have to be larger than in received image signal
The total pixel of row of ultimate resolution image, writing control module carries out write operation with the pixel clock of received image signal, reads control
Module carries out read operation with high speed serialization transceiver parallel data input clock, so as to complete the conversion of image clock signal domain.
The picture signal changed through oversampling clock need to carry out Phase synchronization coding, and the Synchronization Control code of addition is used for receiving terminal pair
The data phase that multipath high-speed serial receiver is received is synchronized.Control code is in the starting position of the field synchronization head of each
Alternate image data, identical control code is sent per road high speed serialization transmitter simultaneously.
Picture signal after Phase synchronization coding is transferred to another by multipath high-speed serial transmitter by transmission link
The high speed serialization transceiver receiving terminal of signal processing unit.How many road high speed serialization transceivers are needed to be determined by the bandwidth of picture signal
Fixed, the bandwidth sum of high speed serialization transceiver have to be larger than the bandwidth of picture signal.It is impossible due to being connected up on cable and pcb board
Ensure that the parameters such as impedance and the length of two-way link are consistent, two paths of data is likely to result in receiving terminal reception for high-speed data
When it is asynchronous, so as to cause image signal data to misplace.
The high-speed serial receiver of receiving terminal is input to Phase synchronization module, Phase synchronization module after receiving picture signal
By judging whether control code out completes synchronization from multipath reception device end solution simultaneously.
The structure of Phase synchronization module as shown in figure 3, here by taking two-way high speed serialization transceiver as an example, Phase synchronization module
Including two FIFO.FIFO_0 and FIFO_1 is respectively written into after two receiving terminals receive data, as we can see from the figure
The corresponding links of FIFO_0 link more corresponding than FIFO_1 has fallen behind a clock cycle, and FIFO_0 is a high position for view data,
FIFO_1 is the low level of view data, and being read from FIFO_0 and FIFO_1 after data merge can cause high-low-position to misplace, it is impossible to
Restore image.
Phase synchronization module completes the synchronization of multiple high speed serialization transceiver links according to the flow shown in Fig. 4：
1st, it is first determined whether reading Synchronization Control code simultaneously from FIFO_0 and FIFO_1, if reading explanation two simultaneously
Individual link is synchronous, and Phase synchronization treatment is not done, because Synchronization Control code is to replace each starting position of field synchronization
Inserted for the mode of view data, this when, if the polarity unified modules are by the field sync signal and row of picture signal
The polarity unification of synchronizing signal is negative polarity, then field sync signal, line synchronising signal, view data useful signal and picture signal
All it is 0, when Synchronization Control code is received, it is believed that the data for receiving are 0, from without influenceing image signal data extensive
It is multiple.If the polarity unification of the field sync signal of picture signal and line synchronising signal is positive polarity by the polarity unified modules,
Field sync signal and line synchronising signal are 1, and view data useful signal and picture signal are still 0, when receiving Synchronization Control code
When, it is believed that line synchronising signal and field sync signal data bit are 1 in the data for receiving, and other positions are 0, are not influenceed equally
Image signal data recovers.
2nd, if not Synchronization Control code is read simultaneously, illustrate that two links are asynchronous, enable write-in end and prepare to reset
FIFO。
3rd, when FIFO_0 write-in ends are when the Synchronization Control code that next field duration sends is received, reset FIFO_0；When
FIFO_0 writes end when the Synchronization Control code that next field duration sends is received, reset FIFO_1；
4th, the data of Synchronization Control code are closelyed follow in write-in at once after having resetted.
5th, when the data bulk in FIFO_0 and FIFO_1 is simultaneously greater than the threshold value of setting, at the same read FIFO_0 and
Data in FIFO_1, it is ensured that read data 1 simultaneously from two FIFO, complete data phase synchronization.
Two FIFO depths and read threshold are relevant with the difference of two links, if two link impedances and length etc. are joined
Number difference is bigger, and FIFO depth and read threshold need to set bigger.Because all can as the high speed serialization transceiver for using parallel
Isometric design is done in hardware design, so difference is typically not too large.
Compared with prior art, the advantage of this image transmission is as follows：
1st, because having the logical device price and the phase without high speed serialization transceiver of high speed serialization transceiver at this stage
Difference is little, and cost is lower than increasing coding and decoding video chip.
2nd, the image signal data of high bandwidth can be transmitted using the high-speed transceiver of low bandwidth, is reduce further into
This.
3rd, multipath high-speed serial transceiver data phase synchronization can be automatically performed, it is to avoid the figure that view data dislocation is caused
As Huaping phenomenon.
Embodiment described above only expresses several embodiments of the invention, and its description is more specific and detailed, but simultaneously
Therefore the limitation to the scope of the claims of the present invention can not be interpreted as.It should be pointed out that for one of ordinary skill in the art
For, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to guarantor of the invention
Shield scope.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (3)
1. a kind of image transmission, it is characterised in that including transmitting terminal and receiving terminal,
The transmitting terminal includes signal selector, polarity unified modules, clock zone modular converter, Phase synchronization coding module, and
Multiple high speed serialization transmitters；
The receiving terminal includes multiple high-speed serial receivers, Phase synchronization module and local signal processing unit；
The number of the high speed serialization transmitter and the high-speed serial receiver is determined by the bandwidth of picture signal；
The signal selector sends to the polarity unified modules selected picture signal, and the polarity unified modules will
The field sync signal of picture signal is positive polarity or negative polarity, the clock zone modular converter with the polarity unification of line synchronising signal
Polarity picture signal after reunification is transformed into high speed serialization transmitter parallel data input clock domain, the Phase synchronization coding
Synchronization Control code is inserted module the starting position alternate image data of the field synchronization head of each, multiple high speed serializations hairs
Send device to transmit to multiple high speed serializations the picture signal after Phase synchronization is encoded commonly through transmission link to receive
Device；
The multiway images data is activation that multiple high-speed serial receivers will be received is to the Phase synchronization module, the phase
Bit sync module judges whether to read the Synchronization Control code of multiway images data simultaneously, if multiway images data then are sent into institute
Local signal processing unit is stated, if otherwise multiway images data are carried out with Phase synchronization treatment, then is sent at the local signal
Reason unit；
The Phase synchronization module includes multiple FIFO memories and synchronous processing module, the corresponding institute all the way of each FIFO memory
High-speed serial receiver is stated, for storing view data all the way, the synchronous processing module reads same from each FIFO memory
Step control code, judges multiway images data syn-chronization if read simultaneously, and multiway images data are judged not if can not read simultaneously
Synchronous, when one of FIFO memory receives the Synchronization Control code that next field duration sends, all FIFO that reset are deposited
Reservoir, writes the data after Synchronization Control code after the completion of reset；
In the Phase synchronization module, when the data bulk in multiple FIFO memories is simultaneously greater than the threshold value of setting, institute
State data synchronous processing module reads multiple FIFO memories simultaneously in.
2. image transmission according to claim 1, it is characterised in that
The clock zone modular converter includes writing control module, read control module and two FIFO memories：FIFO_a、FIFO_
b；
The control module of writing controls the odd-numbered line of picture signal to be written to FIFO_a according to the line synchronising signal of picture signal, even
Several rows are written to FIFO_b, and the read control module is according to the line synchronising signal of picture signal alternately from FIFO_a and FIFO_b
Middle reading picture signal, when it is described write control module and write FIFO_a when, read control module reads FIFO_b, and control is write when described
When molding block writes FIFO_b, the read control module reads FIFO_a, and two width of FIFO memory are field sync signal, OK
The width sum of synchronizing signal, data valid signal and viewdata signal, maximum point more than in picture signal to be transmitted of depth
The total pixel of row of resolution image, the control module of writing carries out write operation with the pixel clock of picture signal, and the reading controls mould
Block carries out read operation with high speed serialization transmitter parallel data input clock, so as to complete the conversion of image clock signal domain.
3. image transmission according to claim 2, it is characterised in that
In the Phase synchronization module, the depth of multiple FIFO memories and the threshold value with impedance between transmission link and
The increase of the difference of length and increase.
Priority Applications (1)
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| CN201410129037.4A CN103888693B (en) | 2014-03-31 | 2014-03-31 | Image transmission |
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| CN201410129037.4A CN103888693B (en) | 2014-03-31 | 2014-03-31 | Image transmission |
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| CN103888693B true CN103888693B (en) | 2017-06-13 |
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Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104378648B (en) * | 2014-10-31 | 2017-10-10 | 广东威创视讯科技股份有限公司 | image coding, decoding, transmission method and system |
| CN104349016B (en) * | 2014-10-31 | 2018-08-07 | 广东威创视讯科技股份有限公司 | High-definition image data transmission method and system |
| CN105657318B (en) * | 2016-01-04 | 2018-08-07 | 广东威创视讯科技股份有限公司 | Video transmission method based on LVDS signals and device |
| TW201915818A (en) * | 2017-10-05 | 2019-04-16 | 香港商印芯科技股份有限公司 | Optical identification module |
| CN109862210B (en) * | 2019-03-26 | 2020-12-25 | 中国科学院长春光学精密机械与物理研究所 | Acquisition and receiving system for multi-path and multi-spectral-band serial image data |
| CN110636219B (en) * | 2019-09-03 | 2020-12-01 | 北京三快在线科技有限公司 | Video data stream transmission method and device |
| WO2021119967A1 (en) * | 2019-12-17 | 2021-06-24 | 威创集团股份有限公司 | Method, device, and system for mosaic wall video signal synchronization |
| CN113038069B (en) * | 2019-12-25 | 2022-06-10 | 魔门塔(苏州)科技有限公司 | Data transmission system |
| CN114758606B (en) * | 2020-12-29 | 2023-09-26 | 杭州海康威视数字技术股份有限公司 | Method for transmitting field synchronizing signal, controller and display control system |
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