CN201349262Y - Multi-eye camera - Google Patents
Multi-eye camera Download PDFInfo
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- CN201349262Y CN201349262Y CNU2009201059011U CN200920105901U CN201349262Y CN 201349262 Y CN201349262 Y CN 201349262Y CN U2009201059011 U CNU2009201059011 U CN U2009201059011U CN 200920105901 U CN200920105901 U CN 200920105901U CN 201349262 Y CN201349262 Y CN 201349262Y
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Abstract
The utility model discloses a multi-eye camera, which belongs to the field of robot peripheral equipments and comprises a primary imaging unit, at least one secondary imaging unit and a control unit. The control unit comprises a cache chip and is connected with both the primary imaging unit and the secondary imaging unit, the primary imaging unit images in synchronization with all the secondary imaging units via the control unit, and the control unit is used for receiving the image data of the primary imaging unit and all the secondary imaging units and combining the image data after being cached by the cache chip. The multi-eye camera can realize control and synchronization of all the imaging units, thereby improving measurement accuracy and reducing system cost.
Description
Technical field
The utility model relates to robot peripheral equipment field, particularly a kind of many orders camera.
Background technology
Many orders camera is meant the camera with a plurality of image-generating units.At present, a lot of many orders cameras all are to adopt independently mode of bull, promptly in order to reach real-time measurement, adopt a plurality of image-generating units to work alone, take simultaneously respectively, be sent to PC by data-interface respectively then, finish the splicing of each image, processing such as synthetic by PC.Fig. 1 is existing many orders camera system, and this many orders camera system has 4 independently image-generating unit, shootings simultaneously respectively mutually.To take the view data that obtains then and pass through 4 data interfaces respectively, be Cameralink (camera link) interface here, is sent to PC and goes to handle.In PC, correspondingly, 4 Cameralink capture cards are installed, receive the view data that many orders camera system sends.If select other interface shape for use, BNC (Bayonet Nut Connector, the bayonet nut connector) interface such as analog signal so also needs four analog signal receiving cards.If the non-standard image-generating unit of self defined interface then can be more complicated.
After prior art is analyzed, the inventor finds: the shortcoming of this way maximum is, because each image-generating unit synchronism is bad to cause that the measurement in space accuracy is not enough, simultaneously because each image-generating unit all needs the data-interface that uses one to match with it, in PC, also the capture card of same number of Cameralink capture card or other form to be installed correspondingly, increase a lot of costs for whole many orders camera system, also increased the weight of the work load of PC simultaneously greatly.In addition, corresponding to the view data of different acquisition form different capture cards need be installed, the compatible performance of many orders camera is good inadequately.
The utility model content
In order to improve certainty of measurement, reduce system cost, the utility model embodiment provides a kind of many orders camera.Described technical scheme is as follows:
A kind of many orders camera comprises: main image-generating unit, at least one is from image-generating unit and control unit, and described control unit comprises cache chip,
Wherein said control unit links to each other from image-generating unit with described with described main image-generating unit respectively, described main image-generating unit is described from the image-generating unit synchronous imaging by described control unit and all, described control unit receives described main image-generating unit and all described view data from image-generating unit, by after the described cache chip buffer memory described view data being merged.
Particularly, described control unit comprises:
Main image-generating unit connector, main image-generating unit data decode chip, digital coding chip,
Respectively from the image-generating unit connector, respectively from image-generating unit data decode chip, respectively from image-generating unit digital coding chip,
And metadata cache chip, programmable logic array; Wherein,
Described main image-generating unit connector links to each other with described main image-generating unit, and link to each other with described programmable logic array by described main image-generating unit data decode chip, the parameter of picture signal, synchronizing signal and the described main image-generating unit of described main image-generating unit is sent to described programmable logic array; Described programmable logic array links to each other with described main image-generating unit by described main image-generating unit digital coding chip, sends to described main image-generating unit after by described main image-generating unit digital coding chip the parameter signalization being encoded;
Describedly link to each other from the image-generating unit connector with described from the image-generating unit connector, and link to each other with described programmable logic array from image-generating unit data decode chip by described, described picture signal and described parameter from image-generating unit from image-generating unit sent to described programmable logic array; Described programmable logic array links to each other from image-generating unit with described from image-generating unit digital coding chip by described, sends to after with parameter signalization, described synchronizing signal coding described from image-generating unit by described from image-generating unit digital coding chip;
Described metadata cache chip and described programmable logic array direct interconnection are used for each frame image data of described principal and subordinate's image-generating unit of receiving by described programmable logic array is carried out buffer memory.
Wherein, described main image-generating unit and describedly be all the digital imagery unit from image-generating unit perhaps is all the analog imaging unit.When described main image-generating unit and described when image-generating unit is all the analog imaging unit, described many orders camera also comprises analog to digital converter, after being used for described main image-generating unit and described analog picture signal from image-generating unit be converted to digital signal, send to described control unit.
Further, described many orders camera also comprises the PC data-interface that links to each other with described programmable logic array.
Described PC data-interface is network signal transducer and the network interface that is attached thereto.
Described network interface is the gigabit network interface.
By in many orders of the utility model embodiment camera system, control unit being set, can realize control and parameter setting to each image-generating unit, improve the synchronism and the whole certainty of measurement of each image-generating unit, reduced system cost, expanded range of application.
Description of drawings
Fig. 1 is the schematic diagram of many orders camera system of prior art;
Fig. 2 is the schematic diagram of many orders of the utility model embodiment camera system;
Fig. 3 is the system schematic of the utility model embodiment principal phase machine;
Fig. 4 is the system schematic of the utility model embodiment from camera;
Fig. 5 is the block diagram of the utility model embodiment control unit;
Fig. 6 is the sequential chart of the synchronizing signal of the utility model embodiment principal phase machine imageing sensor output;
Fig. 7 is the utility model embodiment receives external synchronization signal from the camera image transducer a sequential chart;
Fig. 8 is the sequential that the FPGA of the utility model embodiment control unit adopts 4 times of speed transmission.
Embodiment
For making the purpose of this utility model, technical scheme and advantage clearer, embodiment of the present invention is described further in detail below in conjunction with accompanying drawing.
Fig. 2 shows the system configuration of many orders of the utility model embodiment camera, comprising: main image-generating unit 1, at least one is from image-generating unit 2, control unit 3, wherein control unit 3 respectively with main image-generating unit 1 with link to each other from image-generating unit 2.
In the present embodiment, there to be three to be that example is narrated from image-generating unit 2.The main image-generating unit 1 here and three are from image-generating unit 2, and their internal structure all is identical.Unique different be their " status " difference, they wherein have one to be " master ", remaining be " from ".So-called " MS master-slave " is exactly need to be consistent with the step of main image-generating unit from image-generating unit.Main image-generating unit with can be digital camera from image-generating unit, also can be analogue camera.When main image-generating unit with when image-generating unit is all analogue camera, many orders camera of present embodiment also comprises analog to digital converter, after being used for being converted to digital signal with main image-generating unit with from the analog picture signal of image-generating unit, sends to control unit.Principal and subordinate's image-generating unit has different numberings, because when needing different parameters to be set for each image-generating unit, need distinguish them according to numbering.Following image-generating unit is called for short camera.The principal phase machine need send synchronous signal and give other three from camera.If the principal phase machine with all be digital camera from camera, principal phase machine three synchronizing signals from camera issuing other comprise row synchronously, frame synchronization and synchronous three signals of exposure so.These three signals that the principal phase machine sends at first feed back to control unit, and control unit is through certain delay, and operations such as phase shift are issued from camera again.Through after this method of synchronization, can guarantee from the step of camera consistently with the principal phase machine, and then guaranteed the synchronous of 4 camera data sources.If the principal phase machine with all be analogue camera from camera, the principal phase machine only need send a synchronizing signal and gives from camera so.
For guaranteeing that further the multiway images that control unit sends PC to keeps having increased storage chip in the control unit synchronously, passes to PC again after the buffer memory.Storage chip guarantees that synchronous function is achieved in that in the middle of the process of control unit that is transferred to from image-generating unit of view data, may be because of the not first-class problem of electromagnetic interference, track lengths, cause asynchronous between the multiway images.After having increased storage chip, each road image carries out buffer memory at storage chip earlier, waits after multiway images all arrives fully, and main control unit is passed to PC more together, has so just guaranteed the transmitting synchronous of multiway images.Present embodiment all is that digital camera is that example is narrated with the principal phase machine and from camera.
Each camera is from different angles same object to be taken, under synchronous situation, can guarantee image that PC obtains be at synchronization to same object in different angle shots.A very important aspect of many orders camera is to realize three-dimensional imaging.So-called three-dimensional imaging is taken same object simultaneously from different angles exactly, and this object may be static, also may move; If static object, the synchronous requirement of each shooting point is just lower so, on the contrary, if the object of motion is just very high to synchronous requirement.
Principal and subordinate's camera is the same on hardware constitutes, and as shown in Figure 3 and Figure 4, after they only link in the middle of the whole system, just has principal and subordinate's branch.The benefit of so doing is easy to use, and four cameras can arbitrarily exchange, and do not influence use.Introduce the hardware configuration of principal and subordinate's camera below in detail.
Imageing sensor 4: be the important component part of imaging system, with 5 interconnection of logic control chip.In the present embodiment, all parameters of imageing sensor 4 all are the I by ternary form
2The C signal is provided with.After providing power supply and clock signal to imageing sensor, imageing sensor will output image data and relevant synchronous control signal.
Digital coding chip 7: it links to each other with connector 8 with logic control chip 5 respectively, is used for the data of imageing sensor output and row, a useful signal are encoded into the code signal of difference form, passes to connector 8 then.Present embodiment adopts LVDS coding chip BU8254KVT, it export 6 road signal X0 ±～X4 ±, XCLK ±.Adopt the LVDS signal to prolong the effectively distance of transmission of signal, significantly strengthened the ability of signal opposing common mode disturbances, can also reduce the quantity of the signal of transmission course simultaneously.
Data decode chip 6: link to each other with logic control chip 5 with connector 8 respectively, be used for the conversion of signals of low voltage difference (LVDS) form that obtains from connector 8 is become the single-ended signal of low-voltage TTL (LVTTL) form, and be transferred to logic control chip 5.In order to have interference free performance in the data transmission procedure, the clock signal of high frequency has adopted the difference form of LVDS, and generally all need single-ended LVTTL form the actual use of imageing sensor the time, used this chip of BU8255KVT to finish this work in the present embodiment.
Logic control chip 5: this is a slice CPLD (CPLD, Complex Programmable LogicDevice) chip, is used for data-signal, row field signal, a row feedback signal are done logical process, and present embodiment uses EPM3032.
Connector 8: be used for connecting main image-generating unit and control unit or from image-generating unit and control unit.Present embodiment uses RJ45, and it is a kind of network interface socket of standard.Each connector 8 adopts two RJ45 to realize, one is used for transferring input signal, and another is used for transmission output signal.
Though the hardware configuration of principal and subordinate's camera is in full accord, but after in receiving system, it is different that their part signal flows to.To go control signal, control signal and exposure control signal is example, and these three signals are from imageing sensor output in the principal phase machine, and from camera, these three signals are input picture transducers.This also is the ingenious part of this design, fully multiplexing limited interconnection resources.
If principal and subordinate's image-generating unit is the digital camera of some standard interfaces, the data of principal and subordinate's image-generating unit output will convert the receivable signal of control unit to by a boxcar so, pass to control unit by connector RJ45 afterwards.
If the output of principal and subordinate's image-generating unit is analog signal, analog signal will directly pass to control unit by BNC socket and coaxial cable so.In control unit, adopt the independently analog signal digital of analog-to-digital conversion module to importing, give field programmable gate array unified processing then.
Fig. 5 shows the block diagram of the utility model embodiment control unit.Control unit comprises:
Principal phase machine connector 8, principal phase machine data decoding chip 9, principal phase machine data coding chip 10,
Respectively from camera connector 8, respectively from camera data decoding chip 9, respectively from camera data coding chip 10,
Principal phase machine connector 8 links to each other with described principal phase machine, and passes through principal phase machine data decoding chip 9 with synchronizing signal, picture signal, sends to programmable logic array 11 such as view data, row, field, exposure signal; Programmable logic array 11 sends to the principal phase machine after by principal phase machine data coding chip 10 the parameter signalization being encoded;
Link to each other from camera with described from camera connector 8, and by from camera data decoding chip 9, will be from the image of camera signal, send to from camera connector 8 such as view data, row, field, exposure control signal with from the parameter of camera; By from camera data decoding chip 10, programmable logic array 1 sends to from camera after with parameter signalization, above-mentioned synchronizing signal coding;
Pin-saving chip 13 and programmable logic array 11 interconnection are used for each frame image data of principal and subordinate's camera of receiving by programmable logic array 11 is carried out buffer memory.
Further, many orders camera also comprises the PC data-interface 12 that links to each other with described programmable logic array 11.
Introduce the hardware configuration of control unit below in detail.
Connector 8: be used for connecting principal and subordinate's camera.What wherein, connector-A connected is the principal phase machine; Connector-B, C, what D connected is from camera.That describes in the signal above this connector 8 and the principal and subordinate's camera is the same.That present embodiment uses is standard network opening connector RJ45.
Data decode chip 9: it links to each other with FPGA 11 with connector 8 respectively.Its effect is opposite with the effect of magazine digital coding chip 7, and the differential signal after it encodes digital coding chip 7 is decoded into single-ended view data, sends FPGA 11 then to.Present embodiment uses BU8255KVT.
Digital coding chip 10: it links to each other with FPGA 11 with connector 8 respectively.It sends the difference form that the LVTTL of the single-ended format of FPGA 11 outputs converts LVDS to connector 8 then.That present embodiment uses is BU8254KVT.
Programmable logic array (FPGA, Field-Programmable Gate Array) 11: its input is connected to the output of digital coding chip 9, the output of metadata cache chip 13 respectively; Its output is connected to the input of PC data-interface 12, digital coding chip 10 and the input of metadata cache chip 13 respectively.FPGA is the core of The whole control unit, the control of all parameter, synchronously and the merging of image or the like all finish by it.FPGA 11 receives picture signal, the synchronizing signal that data decode chip 9 transmits, wherein, picture signal comprises view data, row, field, exposure control signal, view data is sent to metadata cache chip buffer memory earlier, after frame data of multiway images all receive fully, again view data is taken out from storage chip,, pass to PC by PC data-interface 12 then principal and subordinate's image of camera data and become piece image.FPGA 11 sends to digital coding chip 10 to clock signal, passes to image-generating unit by connector then, and the data decode chip on the image-generating unit is decoded out with clock signal and supplied with imaging sensor and use.Provide because the employed clock of multichannel camera is same clock source, so just on microcosmic, guaranteed the synchronous of picture signal.
Metadata cache chip 13: the principal and subordinate's image of camera data that receive by programmable logic array 11 are carried out buffer memory.View data is that the form according to a frame one frame transmits, and when the multiway images data all were filled with a frame in metadata cache chip 13 after, FPGA read these frames from metadata cache chip 13, then these view data and become piece image, passes to PC.
PC data-interface 12: it is the data-interface between many orders camera system and the PC.The PC data-interface preferred embodiment is network signal transducer and the network interface that is attached thereto.The effect of network signal transducer is view data to be converted to network signal send out.In the present embodiment, the network signal transducer adopts iPort PT1000-VB, and network interface is the gigabit network interface.What adopt in the time of the iPortPT1000-VB transmit image data is udp protocol, and this agreement can effectively be utilized bandwidth, increases payload, makes bandwidth availability ratio reach maximum.Effectively the transmission rate of image can reach 960Mbps.Because the image data amount that principal and subordinate's camera obtains is very big, the benefit of doing like this is to improve transmission speed, adapts to the application of many orders camera better.
In the present embodiment, the main effect of control unit 3 is to be responsible for the control of each camera and synchronously, also from the principal phase machine, carry out buffer memory from the data of 4 cameras such as camera, is merged into piece image afterwards simultaneously, is transferred to PC by PC data-interface 12.
Control unit 3 is responsible for being provided with the various parameters of 4 cameras, comprises the time for exposure, gain or the like.Control unit 3 after receiving the control command that PC sends here, simultaneously or timesharing each camera is set.Because each camera is to come same object image-forming from different angles, actual residing environment may have very big difference, so be provided with can be different for the parameter of each camera.So control unit can be according to actual conditions, decision is that each camera or the setting of timesharing are set simultaneously.So-called setting simultaneously is exactly that each camera is provided with action in the parameter that synchronization receives main control unit; Timesharing is provided with, and is exactly each camera that is provided with of precedence, and parameter may be different.
For accomplish each camera synchronously, control unit 3 has played important effect aspect following four:
1. synchronization of clock signals: the clock signal that each camera uses is all sent by control unit, that is to say that the clock signal that each camera uses is synchronous, and fixed phase relation is arranged.Do like this, can go up at " microcosmic " and guarantee the synchronous of each camera.
2. triggering signal is synchronous: when camera was operated in triggering mode, user's triggering signal of outside input was issued each camera after going dithering process through control unit 3 simultaneously, guaranteed that each camera begins exposure, imaging from synchronization.This can regard as on " macroscopic view " synchronously.
3. camera is divided into master slave mode.Main magazine imageing sensor 4 can be exported three synchronizing signals: control frame signal (FCTRL, Frame Control), go control signal (LCTRL, Line Control) and exposure control signal (ECTRL, Explosure Control) three signals, these three signals directly send to control unit 3, be used for successively synchronously from frame, row and the exposure of camera image transducer 4, as shown in Figure 6 by control unit 3.Shown in Figure 7 is the utility model embodiment receives external synchronization signal from camera image transducer 4 sequential chart.As can be seen from Figure 7, after image of camera transducer 4 receives the synchronizing signal that control unit 3 sends, produce the sequential of the row useful signal of oneself.From the rising edge of exposure control signal to the rising edge of control frame signal being time for exposure from image of camera transducer 4.Exposure control signal is produced by control unit 3, and the capable control signal that receives from camera, control frame signal also is through the signal after control unit 3 processing.
4. to have guaranteed that control unit is issued the multiway images of PC synchronous for the metadata cache chip in the control unit, and avoided the phenomenon of wrong frame, frame losing.
Control unit 3 is after receiving each image of camera data, and advanced row cache is spliced into the big figure of a width of cloth to them then, is transferred to PC by kilomega network.The mode of splicing can be varied, as long as the assembly mode of separating of the connecting method of assurance control unit and PC is consistent.Joining method commonly used is, from left to right four figure arranged, and this final big figure resolution in the horizontal direction is 4 times of an independent figure.PC after receiving the good image of splicing, it resolve into 4 independently image be used for handling.
What need explanation a bit is that the utility model embodiment can also realize that each camera is changed into according to preset time asynchronous triggering at interval by synchronous triggering by the programming to FPGA.
In the present embodiment, FPGA 11 has adopted in the combined diagram picture and has improved point is realized 4 times of speed frequently with the way of transmitting two pixels simultaneously transmission.The point of supposing imageing sensor 4 dateouts is X frequently, and FPGA 11 is exactly 2X in the clock frequency of output combined diagram picture so.Imageing sensor 4 is the output in order of a pixel, a pixel in dateout, and just a clock cycle is only exported a pixel; FPGA 11 is to transmit two pixels simultaneously after merging.By these two ways, just can realize 4 groups of images are merged into an image, the time is the same with the time of input picture.Shown in Figure 8 is the sequential that FPGA 11 adopts 4 times of speed transmission.
The utility model principal and subordinate image-generating unit both can be the digital signal camera of standard interface, also can be the digital camera of self defined interface, perhaps the analog signal camera of mode standard.Under the situation that adopts different cameral, the design of side circuit is different, but interface shape and data format that final main control unit is transferred to PC all are identical.
The image-generating unit of the utility model embodiment also can be industrial camera.The PC data-interface also can be the Cameralink interface, and at this moment the PC end needs supporting use Cameralink capture card.
By in many orders of the utility model embodiment camera system, control unit being set, receive the synchronizing signal of main image-generating unit and send it to respectively from image-generating unit, can realize the control of each image-generating unit and synchronously reducing system cost.Control unit is after receiving the view data of each image-generating unit simultaneously, advanced row cache, when the multiway images data all are filled with a frame in the metadata cache chip after, from the metadata cache chip, read again, then these view data and become piece image to pass to PC, further improve the synchronism of each image-generating unit view data, thereby improved certainty of measurement.
The above only is preferred embodiment of the present utility model, and is in order to restriction the utility model, not all within spirit of the present utility model and principle, any modification of being done, is equal to replacement, improvement etc., all should be included within the protection range of the present utility model.
Claims (7)
1. order camera more than a kind is characterized in that, comprising: main image-generating unit, at least one is from image-generating unit and control unit, and described control unit comprises cache chip,
Wherein said control unit links to each other from image-generating unit with described with described main image-generating unit respectively, described main image-generating unit is described from the image-generating unit synchronous imaging by described control unit and all, described control unit receives described main image-generating unit and all described view data from image-generating unit, by after the described cache chip buffer memory described view data being merged.
2. many orders camera according to claim 1 is characterized in that, described control unit comprises:
Main image-generating unit connector, main image-generating unit data decode chip, digital coding chip,
Respectively from the image-generating unit connector, respectively from image-generating unit data decode chip, respectively from image-generating unit digital coding chip,
And metadata cache chip, programmable logic array; Wherein,
Described main image-generating unit connector links to each other with described main image-generating unit, and link to each other with described programmable logic array by described main image-generating unit data decode chip, the parameter of picture signal, synchronizing signal and the described main image-generating unit of described main image-generating unit is sent to described programmable logic array; Described programmable logic array links to each other with described main image-generating unit by described main image-generating unit digital coding chip, sends to described main image-generating unit after by described main image-generating unit digital coding chip the parameter signalization being encoded;
Describedly link to each other from the image-generating unit connector with described from the image-generating unit connector, and link to each other with described programmable logic array from image-generating unit data decode chip by described, described picture signal and described parameter from image-generating unit from image-generating unit sent to described programmable logic array; Described programmable logic array links to each other from image-generating unit with described from image-generating unit digital coding chip by described, sends to after with parameter signalization, described synchronizing signal coding described from image-generating unit by described from image-generating unit digital coding chip;
Described metadata cache chip and described programmable logic array direct interconnection are used for each frame image data of described principal and subordinate's image-generating unit of receiving by described programmable logic array is carried out buffer memory.
3. many orders camera according to claim 1 and 2 is characterized in that, described main image-generating unit and describedly be all the digital imagery unit from image-generating unit perhaps is all the analog imaging unit.
4. many orders camera according to claim 3, it is characterized in that, when described main image-generating unit and described when image-generating unit is all the analog imaging unit, described many orders camera also comprises analog to digital converter, after being used for described main image-generating unit and described analog picture signal from image-generating unit be converted to digital signal, send to described control unit.
5. many orders camera according to claim 1 and 2 is characterized in that, described many orders camera also comprises the PC data-interface that links to each other with described programmable logic array.
6. many orders camera according to claim 5 is characterized in that, described PC data-interface is network signal transducer and the network interface that is attached thereto.
7. many orders camera according to claim 6 is characterized in that, described network interface is the gigabit network interface.
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| CNU2009201059011U CN201349262Y (en) | 2009-02-11 | 2009-02-11 | Multi-eye camera |
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| CNU2009201059011U CN201349262Y (en) | 2009-02-11 | 2009-02-11 | Multi-eye camera |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103442178A (en) * | 2013-09-12 | 2013-12-11 | 电子科技大学 | High-speed multi-data path splicing system |
| CN104320597A (en) * | 2014-10-29 | 2015-01-28 | 江西瑞林电气自动化有限公司 | Driving device and method for synchronous signal collection for multiple CCD cameras |
| CN104378548A (en) * | 2014-10-31 | 2015-02-25 | 北京空间机电研究所 | Space multi-spectrum-section imager video circuit system |
| CN104427218A (en) * | 2013-09-02 | 2015-03-18 | 北京计算机技术及应用研究所 | Ultra high definition CCD (charge coupled device) multichannel acquisition and real-time transmission system and method |
| CN104717480A (en) * | 2014-01-28 | 2015-06-17 | 杭州海康威视数字技术股份有限公司 | Binocular camera pixel-level synchronous image acquisition device and method thereof |
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| CN104427218A (en) * | 2013-09-02 | 2015-03-18 | 北京计算机技术及应用研究所 | Ultra high definition CCD (charge coupled device) multichannel acquisition and real-time transmission system and method |
| CN104427218B (en) * | 2013-09-02 | 2017-11-21 | 北京计算机技术及应用研究所 | Ultra high-definition ccd image multichannel collecting and RTTS and method |
| CN103442178A (en) * | 2013-09-12 | 2013-12-11 | 电子科技大学 | High-speed multi-data path splicing system |
| CN104717480A (en) * | 2014-01-28 | 2015-06-17 | 杭州海康威视数字技术股份有限公司 | Binocular camera pixel-level synchronous image acquisition device and method thereof |
| CN104320597A (en) * | 2014-10-29 | 2015-01-28 | 江西瑞林电气自动化有限公司 | Driving device and method for synchronous signal collection for multiple CCD cameras |
| CN104378548A (en) * | 2014-10-31 | 2015-02-25 | 北京空间机电研究所 | Space multi-spectrum-section imager video circuit system |
| CN104378548B (en) * | 2014-10-31 | 2017-10-24 | 北京空间机电研究所 | A kind of space multi-spectral imaging instrument video circuit system |
| CN107552413A (en) * | 2017-08-15 | 2018-01-09 | 昆山易分蓝电子科技有限公司 | Polyethylene particle raw material inspects the organization and management method of hierarchy system by random samples |
| CN107552413B (en) * | 2017-08-15 | 2020-03-31 | 昆山易分蓝电子科技有限公司 | Organization management method of polyethylene particle raw material sampling inspection grading system |
| CN109714550A (en) * | 2018-12-17 | 2019-05-03 | 中国科学院长春光学精密机械与物理研究所 | The imaging control circuitry and multiple use area camera of multiple use area camera |
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