CN104717480A - Binocular camera pixel-level synchronous image acquisition device and method thereof - Google Patents
Binocular camera pixel-level synchronous image acquisition device and method thereof Download PDFInfo
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Abstract
The invention relates to the field of video monitoring, and discloses a binocular camera pixel-level synchronous image acquisition device and a method thereof. The device comprises a timing sequence control unit, a first image sensor, a second image sensor and an image processing unit, wherein the timing sequence control unit is achieved through programmable logic devices and used for generating a row and field synchronization signal according to an input reference clock signal; the first image sensor and the second image sensor work in a driven mode and are used for generating synchronous parallel data through being driven by the row and field synchronization signal, and the image processing unit is used for conducting image processing on the synchronous parallel data to obtain synchronous image data, wherein the first image sensor and the second sensor both work on the reference clock signal and have the same operating parameters. By means of the binocular camera pixel-level synchronous image acquisition device and the method thereof, the pixel-level synchronous image data can be obtained, depth data can be obtained from the pixel-level synchronous image data, and accurate intelligent analysis can be conducted on an object.
Description
Technical field
The present invention relates to field of video monitoring, particularly the Pixel-level synchronous images acquiring technology of binocular camera.
Background technology
Binocular stereo vision refers to and passes through mobile or the same width scene of rotary taking by two of diverse location or an image sensors, and by computer memory point parallax in two images, obtains the D coordinates value of this point.
Binocular camera refers to by two apish eyes of imageing sensor, carries out the device of camera work simultaneously.The video content of its shooting comprises the video of two angles, and delivered to respectively in two eyes of beholder by 3D presentation apparatus when showing, beholder can produce the stereoscopic vision of being in the action.
The present inventor finds, current binocular camera, and the time for exposure difference of two imageing sensor is comparatively large, and about about 0.5 row, the synchronous images data syn-chronization precision of acquisition is not high, should not be used for acquisition and the intellectual analysis of picture depth data.
Summary of the invention
The object of the present invention is to provide a kind of Pixel-level synchronous images acquisition device and method thereof of binocular camera, the view data that obtainable Pixel-level is synchronous, and obtain depth data from these Pixel-level synchronous images data, intellectual analysis is accurately carried out to object.
For solving the problems of the technologies described above, embodiments of the present invention disclose a kind of Pixel-level synchronous images acquisition device of binocular camera, comprising:
Timing control unit, realizes with programmable logic device, generates row field sync signal for the reference clock signal according to input;
First and second imageing sensors, work in follower mode, to run simultaneously data for generation under the driving of field sync signal of being expert at;
Graphics processing unit, obtains synchronous images data after carrying out image procossing for data of running simultaneously;
Wherein, the first and second imageing sensors all work in reference clock signal and have identical running parameter.
Embodiments of the present invention also disclose a kind of Pixel-level synchronous images acquisition methods of binocular camera, this binocular camera comprises the timing control unit, the first imageing sensor and the second imageing sensor that realize with programmable logic device, timing control unit, the first and second imageing sensors all work in reference clock signal, and the method comprises the following steps:
Timing control unit is made to generate row field sync signal according to reference clock signal;
The first and second imageing sensors making to work under follower mode be expert at field sync signal driving under generation to run simultaneously data;
Data of running simultaneously obtain synchronous images data after carrying out image procossing;
Wherein, the first and second imageing sensors have identical running parameter.
Compared with prior art, the main distinction and effect thereof are embodiment of the present invention:
Under the timing control unit generating row field sync signal all works in identical reference clock signal with two imageing sensors, and two imageing sensors have identical running parameter, thus ensure that the time of exposure of imageing sensor and output image can accomplish the synchronous of Pixel-level, simultaneously, synchronized sampling and transmission are carried out to the data of running simultaneously produced, can ensure that the data of running simultaneously that two imageing sensors produce remain synchronous, and then make the view data obtained finally by process be that Pixel-level is synchronous.In addition, depth data can be obtained from these Pixel-level synchronous images data and intellectual analysis is accurately carried out to object.
Further, two sampling clocks are adopted can to guarantee the Complete Synchronization of two channel datas while guarantee sampling is correct.
Accompanying drawing explanation
Fig. 1 is the structural representation of the Pixel-level synchronous images acquisition device of a kind of binocular camera in first embodiment of the invention;
Fig. 2 is the structural representation of the Pixel-level synchronous images acquisition device of a kind of binocular camera in second embodiment of the invention.
Fig. 3 is the structural representation of a kind of imageing sensor in second embodiment of the invention;
Fig. 4 is a kind of hardware connection mode of imageing sensor in second embodiment of the invention;
Fig. 5 is the operating diagram of the timing control unit of the Pixel-level synchronous images acquisition device of a kind of binocular camera in second embodiment of the invention;
Fig. 6 is that the imageing sensor of the Pixel-level synchronous images acquisition device of a kind of binocular camera in second embodiment of the invention is at pixel distribution schematic diagram physically;
Fig. 7 is the master control of Pixel-level synchronous images acquisition device and the structural representation of arithmetic element of a kind of binocular camera in second embodiment of the invention;
Fig. 8 is the operating diagram of the Pixel-level synchronous images acquisition device of a kind of binocular camera in second embodiment of the invention;
Fig. 9 is that in second embodiment of the invention, a kind of synchronized sampling is run simultaneously the mode of data;
Figure 10 is that in second embodiment of the invention, a kind of synchronized sampling is run simultaneously the mode of data;
Figure 11 is the operating diagram of the Pixel-level synchronous images acquisition device of a kind of binocular camera in second embodiment of the invention;
Figure 12 is the schematic flow sheet of the Pixel-level synchronous images acquisition methods of a kind of binocular camera in third embodiment of the invention.
Embodiment
In the following description, many ins and outs are proposed in order to make reader understand the application better.But, persons of ordinary skill in the art may appreciate that even without these ins and outs with based on the many variations of following execution mode and amendment, also can realize each claim of the application technical scheme required for protection.
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, embodiments of the present invention are described in further detail.
First embodiment of the invention relates to a kind of Pixel-level synchronous images acquisition device of binocular camera.Fig. 1 is the structural representation of the Pixel-level synchronous images acquisition device of this binocular camera.
Specifically, as shown in Figure 1, the Pixel-level synchronous images acquisition device of this binocular camera comprises:
Timing control unit, realizes with programmable logic device, generates row field sync signal for the reference clock signal according to input.
First and second imageing sensors, work in follower mode, to run simultaneously data for generation under the driving of field sync signal of being expert at.Wherein, this first and second imageing sensor all works in reference clock signal and has identical running parameter.
Graphics processing unit, obtains synchronous images data after carrying out image procossing for data of running simultaneously.
In the present invention, said Pixel-level synchronously refers to the time difference of running simultaneously between data (pixel clock period is the integral multiple of reference clock cycle) in a pixel clock period of two imageing sensor shootings.
The present invention is in the process of practical application, timing control unit can be independent programmable logic device, as FPGA(Field-Programmable Gate Array, field programmable gate array), PLD(programmable logic device), CPLD(CPLD) etc., also can be the control chip integrated with other unit of this device.
In addition, the Pixel-level synchronous images acquisition device of this binocular camera also comprises with lower unit:
Parameter set unit, has identical running parameter for arranging the first and second imageing sensors.
Resolve cutting unit, for resolve and cutting is run simultaneously data, wherein, cut out the non-effective data part referring to removal view data.
Intelligent processing unit, for obtaining depth information from the synchronous images data after graphics processing unit process, and carries out the intellectual analysis of image based on this depth information.Wherein, intellectual analysis comprises Distance positioning, object height acquisition etc.
Synchronized sampling unit, for the data of running simultaneously that synchronized sampling first and second imageing sensor produces.The synchronized sampling of this synchronized sampling unit realizes in the following manner:
Adopt two source synchronous clocks simultaneously exported by the first and second imageing sensors with data of running simultaneously, synchronized sampling is carried out to the data of running simultaneously of two corresponding respectively data channel.
In the embodiments of the present invention, these two sampling clocks are that (source synchronous clock is herein the clock exported together with parallel data to the source synchronous clock of parallel data that exports of each sensor, the source synchronous clock frequency of the data of two passages is consistent, but phase relation is inconsistent), with respective parallel data, there is best phase relation, to ensure the correct of sampling.Therefore, adopt two sampling clocks, the Complete Synchronization of two channel datas can be ensured while guarantee sampling is correct.
In addition, be appreciated that in other execution modes of the present invention, also the data assemblies of two passages can be got up, be separated again after graphics processing unit receives.
In the present embodiment, image procossing refers to picture signal process (ISP).The running parameter of imageing sensor comprises exposure rate, gain and pixel output frequency etc.Imageing sensor is CMOS(complementary metal oxide semiconductors (CMOS)) transducer, timing control unit is field programmable gate array.
In the present invention, the timing control unit generating row field sync signal and two imageing sensors all work in identical reference clock signal under, and two imageing sensors have identical running parameter, ensure that the time of exposure and the output image of imageing sensor can accomplish the synchronous of Pixel-level, simultaneously, synchronized sampling and transmission are carried out to the data of running simultaneously produced, can ensure that the data of running simultaneously that two imageing sensors produce remain synchronous, and then make the view data obtained finally by process be that Pixel-level is synchronous.In addition, depth data can be obtained from these Pixel-level synchronous images data and intellectual analysis is accurately carried out to object.
It should be noted that, the each unit mentioned in the present invention's each equipment execution mode is all logical block, physically, a logical block can be a physical location, also can be a part for a physical location, can also realize with the combination of multiple physical location, the Physical realization of these logical blocks itself is not most important, and the combination of the function that these logical blocks realize is only the key solving technical problem proposed by the invention.In addition, in order to outstanding innovative part of the present invention, the unit not too close with solving technical problem relation proposed by the invention is not introduced by the above-mentioned each equipment execution mode of the present invention, and this does not show that the said equipment execution mode does not exist other unit.
Second embodiment of the invention relates to a kind of acquisition device of Pixel-level synchronous images of binocular camera, can realize binocular image sensor pixel level synchronously high-precision.
Figure 2 shows that a kind of structural scheme of mechanism of Pixel-level synchronous images acquisition device of binocular camera.Include imageing sensor daughter board, infrared light board, mainboard and interface circuit (as flexible PCB (FPC) interface).Imageing sensor daughter board (comprising imageing sensor daughter board 1 and imageing sensor daughter board 2) is mainly IMX138CMOS imageing sensor and interface circuit, and infrared light board is infrared LED (light-emitting diode) lamp, can irradiation distance 20m; Mainboard includes the control chip etc. of timing control unit, master control and arithmetic element and peripheral hardware, and the corresponding control unit of mainboard is responsible for connecting the imageing sensor daughter board of two-way and infrared light board and external device and interface.Timing control unit uses FPGA(field programmable gate array), master control and arithmetic element use a chip of TI DM8147(Texas Instruments).Timing control unit in order to produce timing control signal to front end two-way imageing sensor daughter board and sampling input data of running simultaneously, and ensure that two-way is run simultaneously the synchronous of data, then data of running simultaneously are divided into two-way (data channel 0 and data channel 1) and export to DM8147(video input mouth 0 and video input mouth 1).Master control and arithmetic element DM8147 can support two-way to run simultaneously the input of data and process, ISP process (Image Signal Processor is carried out to bayer data (bayer data), picture signal process), be transferred to rear end equipment by network interface after compressed encoding.DM8147 can also complete acquisition and the analysis of depth map in this locality, carry out the intellectual analysis based on depth information.This hardware platform also supports built-in binary channels MIC(microphone) input, external audio frequency output, warning input and output, Micro SD card (flash memory cards) storage, network interface connection, RS-485(communication interface) communicate and RS-232(communication interface, be the asynchronous transmission standard interface formulated by Electronic Industries Association) debug and reset key.
Particularly, this synchronous images acquisition device comprises:
(1) imageing sensor
Imageing sensor that this device uses is IMX138CMOS transducer.Pixel resolution is 1280*960.Under cmos image sensor is operated in follower mode, receive the V(of FPGA vertical), H(level) row field sync signal, export the signal of the data of running simultaneously of 12 bits.Because the row field drive singal of two cmos image sensors is all controlled by FPGA, the Pixel-level of the data that can ensure to run simultaneously is synchronous.Figure 3 shows that the structured flowchart of IMX138 imageing sensor, the structure of this imageing sensor is prior art, repeats no more here, and important information related to the present invention can provide in explanation afterwards.
Fig. 4 is the hardware connection mode of IMX138 imageing sensor.In this synchronous images acquisition device, according to Fig. 4, cmos image sensor is set, wherein, power input voltage, Mode(mode of operation) be fixed as high level and under being operated in follower mode, reference clock signal (Mclk) is from mainboard, frequency is 37.125MHz, reset, SPI(Serial Peripheral Interface, Serial Peripheral Interface (SPI)), V(field synchronization) and H(capable synchronous) signal is all controlled by timing control unit (FPGA), the frequency of imageing sensor output pixel clock (Dclk) and 12 bit synchronous parallel datas (D [11:0]) is 74.125MHz.
Camera lens that this device uses is tight shot, according to application scenarios, can select the camera lens of 4mm, 6mm and 12mm.
(2) timing control unit
The timing control unit that this device uses is FPGA programmable logic device.Figure 5 shows that the work block diagram of this timing control unit.FPGA, cmos image sensor 0 and cmos image sensor 1 use identical work clock, i.e. reference clock signal Mclk.It produces cmos image sensor 0 and the row field sync signal needed for cmos image sensor 1 by transducer 0V/H and transducer 1V/H sequential logic under Mclk, is divided into two-way and outputs on cmos image sensor 0 and cmos image sensor 1.And master control is connected with cmos image sensor 1 with cmos image sensor 0 by SPI1 mouth with arithmetic element, sheet selects CS0 to be used for sensors configured 0, sheet selects CS1 to be used for sensors configured 1, two cmos sensors are set to identical parameter, ensure that cmos image sensor 0 and cmos image sensor 1 work completely the same.The data of running simultaneously that cmos image sensor 0 and cmos image sensor 1 export (namely comprise data of running simultaneously " transducer 0 [11:0] " and the source synchronous clock " transducer 0_clk " corresponding with parallel data, in like manner, for transducer 1, comprise " transducer 1_clk " and " transducer 1 [11:0] ") carry out sampling acquisition by FPGA again.On fpga logic device, the parsing to data of running simultaneously can be realized, obtain uncorrected data to extract, thus realize the cutting to image size, to remove the non-effective data part of image.Fig. 6 is that imageing sensor is in pixel distribution situation physically.As shown in Figure 6 the non-effective data outside recording pixel district is rejected, only retain valid pixel respectively beyond the mode of synchrodata export.Outer synchrodata comprises respectively: the image valid data of row field sync signal, clock signal and parallel 12 bits.
SPI2 register is in order to the frame per second register in modularization design control unit.Different register values, corresponding different frame per second.Implementation is under identical reference clock, changes the length of row field sync signal.Configuration signal is carried out program by master control and arithmetic element to timing control unit and is loaded configuration.Reset signal is sent timing control unit by master control and arithmetic element, and after having resetted, timing control unit is started working.
(3) master control and arithmetic element
As shown in Figure 7, the master control that this device uses and arithmetic element are TI(Texas Instrument) DM8147 of company, it is by DSP(Digital Signal Processing)+arm processor forms.The arithmetic section i.e. DSP of its inside of this master control and arithmetic element mainly comprises Channel Image process and transducer controls subelement, depth information computation subunit, intellectual analysis subelement and coded sub-units.Channel Image process and transducer control subelement in order to process the view data of two-way, comprise the parameter configuration (resolution, output frequency etc.) of cmos image sensor 0 and cmos image sensor 1, ISP image procossing (white balance etc.), image sensor exposure control etc., two passage is completely independent, algorithm process is also simultaneous operation.To the parameter configuration of two imageing sensors, SPI serial communication mode is used to be connected on two cmos image sensors.Depth information can be obtained by the two Channel Synchronous view data obtained.Intellectual analysis is carried out, as obtained Distance positioning, object height etc. based on depth information.Above-mentioned DSP arithmetic section can also complete the compression coding of Parallel image data to two passages, depth data, is input to ARM main control part carries out net and pass by internal interface.The information of DSP arithmetic section real-time analysis synchronous images data, realizes the control to infrared lamp and ICR.DSP arithmetic section is also by audio frequency CODEC(codec) chip realizes the capturing and coding of local outside Mike's audio frequency, and net can be passed the voice data obtained and be play at local external loudspeaker or earphone by audio frequency CODEC chip by DSP arithmetic section simultaneously.The work of simultaneously master control and arithmetic element also control section peripheral hardware, comprises RS485/232 serial communication port, warning input/output interface and SD card (safe digital card) etc.
(4) peripheral hardware
Peripheral hardware mainly includes infrared lamp, reset button, network interface, audio output port, ICR, RS485/232 serial communication port and warning input/output interface.
Infrared lamp and control circuit for infrared lamp are controlled by the DSP arithmetic section of master control and arithmetic element, carry out opening or closing when day and night mode of operation is different.
ICR and drive circuit are controlled by above-mentioned DSP arithmetic section, switch, realize the optical filtering to light when day and night mode of operation is different.
Audio frequency includes the MIC of left and right acoustic channels, audio frequency CODEC chip and audio stereo output interface.MIC and output interface all need to be connected by the audio interface of CODEC chip with above-mentioned DSP.Be designed with the MIC of left and right acoustic channels in a device, stereosonic audio frequency input effect can be realized.
Warning is that 1 tunnel warning input and the warning of 1 tunnel export.Be controlled by ARM main control part.
Under RS485 is operated in half-duplex mode, be controlled by ARM main control part.
(5) power supply and POE(Power Over Ethernet, active Ethernet)
This device input power is 12V DC power supply, is converted by internal electric source, provides power supply needed for each module.
Device supports that POE powers, AF(Power over Ethernet standard A F) working method.
The specific works mode of this Pixel-level synchronous images device is as follows:
Working method case study on implementation one:
More than to the Pixel-level synchronous images acquisition device basic composition framework of the implementation case one and elaborating of every part thereof.Again the acquisition how realizing Pixel-level synchronous images is described in detail below.
Realize the acquisition of Pixel-level synchronous images, need two cmos image sensors and Channel Image processing unit module.Figure 8 shows that the apparatus structure block diagram realizing Pixel-level synchronous images and obtain.
Under cmos image sensor 0 and cmos image sensor 1 are all operated in follower mode, mainboard includes the timing control unit (FPGA circuit) and master control and arithmetic element (possessing the DM8147 circuit of two PASS VIDEO ports) that produce CMOS Timing driver signal.Under cmos image sensor 0 and cmos image sensor 1 and fpga logic are operated in identical clock frequency, provide unified reference clock signal Mclk by crystal oscillator.FPGA produces identical V, H drive singal to cmos sensor 0 and cmos sensor 1 by transducer V/H sequential logic, CMOS0 with CMOS1 to be run simultaneously data in the exposure of identical moment and output, and two transducers are controlled by master control and arithmetic element by SPI interface, the parameter (exposure, gain and pixel output frequency etc.) that unified configuration is identical.Under two cmos image sensors are all operated in follower mode, drive singal is identical, and the parameter of configuration is also completely the same, and so working method is also completely the same, and the data of running simultaneously of the time of exposure and output can accomplish the synchronous of Pixel-level.
The parallel data d [11:0] of cmos image sensor 0 and cmos image sensor 1 output pixel clock Dclk and 12 bits is on timing control unit, due to the cause of board design, holding wire length Length discrepancy from two imageing sensors to timing control unit, there is little deviation in the moment that signal arrives timing control unit, namely the time delay transmitted in plate level of two tunnel data transport is different, when arriving FPGA pin and the phase relation of sampling clock also inconsistent.As shown in Figure 9, what transducer 0 and transducer 1 existed Pixel-level at the input of timing control unit does not line up situation, uses same sampling clock to carry out sampling and likely cause wherein having the data sampling mistake of a passage, does not namely meet and set up and the retention time.In timing control unit, adopt two sampling clocks to sample to transducer 0 and transducer 1, ensure that sampling is correct, then on internal logic, use the mode of playing bat or fifo queue, ensure the complete matching of two channel datas.
In timing control unit, also can carry out the data of cutting (rejecting in transducer OB district (optical black area) out and dummy(dummy argument) to data of running simultaneously).Mode (Vin0/1V/H, Vin0/1_clk and D [11:0]) synchronous beyond data is passed to two video ports of master control and arithmetic element by FPGA again.Video port 0 and video port 1 are the input interfaces of Channel Image process and sensor control unit, synchronously can complete the reception to FPGA data, the storage of data and image procossing and the two-way that walked abreast in DSP arithmetic section inside is run simultaneously, obtain depth map and intellectual analysis result further.Whole hardware design methods can ensure the view data that the generation Pixel-level of binocular camera is synchronous.
Case study on implementation two:
Case study on implementation two mainly exists inconsistent with case study on implementation one on timing control unit and master control and arithmetic element.
In FPGA inside, the data of two passages can be combined in this case study on implementation, namely passage merges, basic skills as shown in Figure 10, requirement output frequency is double, the original pixels clock of input is 74.25MHz, merging pixel clock after exporting is that in 148.5MHz(figure, 1x and 2x is corresponding, represents that the frequency of 2x is the twice of 1x).Export data according to transducer 0, the staggered output of transducer 1.Export data and enter master control and arithmetic element by video port, require that this unit only needs to possess a video port, as shown in figure 11.After data to the DSP inside of master control and arithmetic element, then be separated, separately carry out two-way and to run simultaneously the ISP image procossing of data.Such benefit is, this end of DSP does not need to possess two video ports, DM8147 can be changed into DM8127 and save cost.In addition, bus can minus a road, is also beneficial to placement-and-routing, and in this case study on implementation, other workflows of Pixel-level synchronous images acquisition device and identical in case study on implementation one, repeat no more.
Third embodiment of the invention relates to a kind of Pixel-level synchronous images acquisition methods of binocular camera.Figure 12 is the schematic flow sheet of the Pixel-level synchronous images acquisition methods of this binocular camera.This binocular camera of Pixel-level synchronous images acquisition methods of this binocular camera comprises timing control unit, the first imageing sensor and the second imageing sensor, timing control unit, the first and second imageing sensors all work in reference clock signal, specifically, as shown in figure 12, the method comprises the following steps:
In step 1201, timing control unit is made to generate row field sync signal according to reference clock signal.
After this enter step 1202, the first and second imageing sensors making to work under follower mode be expert at field sync signal driving under generation to run simultaneously data.Wherein, the first and second imageing sensors have identical running parameter.
After this enter step 1203, data of running simultaneously obtain synchronous images data after carrying out image procossing.
Before step 1203, further comprising the steps of:
Synchronized sampling is carried out by the data of running simultaneously of two sampling clocks to two data channel that the first and second imageing sensors produce; To resolve and cutting is run simultaneously data.
After step 1203, further comprising the steps of:
From the synchronous images data after image procossing, obtain depth information, and carry out the intellectual analysis of image based on this depth information.
Present embodiment is the method execution mode corresponding with the first execution mode, and present embodiment can be worked in coordination with the first execution mode and be implemented.The relevant technical details mentioned in first execution mode is still effective in the present embodiment, in order to reduce repetition, repeats no more here.Correspondingly, the relevant technical details mentioned in present embodiment also can be applicable in the first execution mode.
Each method execution mode of the present invention all can realize in modes such as software, hardware, firmwares.No matter the present invention realizes with software, hardware or firmware mode, instruction code can be stored in the addressable memory of computer of any type (such as permanent or revisable, volatibility or non-volatile, solid-state or non-solid, fixing or removable medium etc.).Equally, memory can be such as programmable logic array (Programmable Array Logic, be called for short " PAL "), random access memory (Random Access Memory, be called for short " RAM "), programmable read only memory (Programmable Read Only Memory, be called for short " PROM "), read-only memory (Read-Only Memory, be called for short " ROM "), Electrically Erasable Read Only Memory (Electrically Erasable Programmable ROM, be called for short " EEPROM "), disk, CD, digital versatile disc (Digital Versatile Disc, be called for short " DVD ") etc.
It should be noted that, in the claim and specification of this patent, the such as relational terms of first and second grades and so on is only used for an entity or operation to separate with another entity or operating space, and not necessarily requires or imply the relation that there is any this reality between these entities or operation or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thus make to comprise the process of a series of key element, method, article or equipment and not only comprise those key elements, but also comprise other key elements clearly do not listed, or also comprise by the intrinsic key element of this process, method, article or equipment.When not more restrictions, the key element " being comprised " limited by statement, and be not precluded within process, method, article or the equipment comprising described key element and also there is other identical element.
Although by referring to some of the preferred embodiment of the invention, to invention has been diagram and describing, but those of ordinary skill in the art should be understood that and can do various change to it in the form and details, and without departing from the spirit and scope of the present invention.
Claims (10)
1. a Pixel-level synchronous images acquisition device for binocular camera, is characterized in that, comprising:
Timing control unit, realizes with programmable logic device, generates row field sync signal for the reference clock signal according to input;
First and second imageing sensors, work in follower mode, for producing data of running simultaneously under the driving of described row field sync signal;
Graphics processing unit, obtains synchronous images data after described data of running simultaneously are carried out image procossing;
Wherein, described first and second imageing sensors all work in reference clock signal and have identical running parameter.
2. the Pixel-level synchronous images acquisition device of binocular camera according to claim 1, is characterized in that, also comprise with lower unit:
Synchronized sampling unit, data of running simultaneously described in producing for synchronized sampling first and second imageing sensor.
3. the Pixel-level synchronous images acquisition device of binocular camera according to claim 2, is characterized in that, the synchronized sampling of described synchronized sampling unit realizes in the following manner:
Adopt two source synchronous clocks simultaneously exported by the first and second imageing sensors with data of running simultaneously, synchronized sampling is carried out to the data of running simultaneously of two corresponding respectively data channel.
4. the Pixel-level synchronous images acquisition device of binocular camera according to claim 1, is characterized in that, also comprise with lower unit:
Parameter set unit, has identical running parameter for arranging described first and second imageing sensors;
Resolve cutting unit, for resolving and run simultaneously described in cutting data.
5. the Pixel-level synchronous images acquisition device of binocular camera according to claim 1, is characterized in that, also comprise with lower unit:
Intelligent processing unit, for obtaining depth information from the synchronous images data after graphics processing unit process, and carries out the intellectual analysis of image based on this depth information.
6. the Pixel-level synchronous images acquisition device of binocular camera according to any one of claim 1 to 5, is characterized in that, described imageing sensor is cmos sensor, and described timing control unit is field programmable gate array.
7. the Pixel-level synchronous images acquisition methods of a binocular camera, it is characterized in that, this binocular camera comprises the timing control unit, the first imageing sensor and the second imageing sensor that realize with programmable logic device, described timing control unit, the first and second imageing sensors all work in reference clock signal, and the method comprises the following steps:
Timing control unit is made to generate row field sync signal according to reference clock signal;
The first and second imageing sensors making to work under follower mode produce data of running simultaneously under the driving of described row field sync signal;
Synchronous images data are obtained after described data of running simultaneously are carried out image procossing;
Wherein, the first and second imageing sensors have identical running parameter.
8. the Pixel-level synchronous images acquisition methods of binocular camera according to claim 7, is characterized in that, described described data of running simultaneously are carried out image procossing after obtain the step of synchronous images data before, further comprising the steps of:
Adopt two source synchronous clocks simultaneously exported by the first and second imageing sensors with data of running simultaneously, synchronized sampling is carried out to the data of running simultaneously of two corresponding respectively data channel.
9. the Pixel-level synchronous images acquisition methods of binocular camera according to claim 7, is characterized in that, described described data of running simultaneously are carried out image procossing after obtain the step of synchronous images data after, further comprising the steps of:
From the synchronous images data after image procossing, obtain depth information, and carry out the intellectual analysis of image based on this depth information.
10. the Pixel-level synchronous images acquisition methods of binocular camera according to claim 7, is characterized in that, described described data of running simultaneously are carried out image procossing after obtain the step of synchronous images data before, further comprising the steps of:
To resolve and cutting is run simultaneously data.
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