CN2912166Y - Multi-rute video inputting device - Google Patents
Multi-rute video inputting device Download PDFInfo
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- CN2912166Y CN2912166Y CN 200620120855 CN200620120855U CN2912166Y CN 2912166 Y CN2912166 Y CN 2912166Y CN 200620120855 CN200620120855 CN 200620120855 CN 200620120855 U CN200620120855 U CN 200620120855U CN 2912166 Y CN2912166 Y CN 2912166Y
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Abstract
The utility model discloses a multi channel video input device, comprising a synthesizing element and a video processing unit with DRAM. The synthesizing element synthesizes the input multi channel standard digital video signals into a digital video signal flow through a clock frequency doubling technology; the synthesized digital video signal flow is received and stored by the DRAM of the video processing unit, and multi channel digital video signals are obtained through separation and restoration, and the data of multi channel video signal corresponding to the input signal is outputted after being processed or compressed. Because the input multi channel standard digital video signals are synthesized into a digital video signal flow by the synthesizing element through a clock frequency doubling technology and multi channel digital video signals are obtained through separation and restoration, and the data of multi channel video signal corresponding to the input signal is outputted after being processed or compressed, multi channel video signals can be passed through a video port under the precondition of ensuring the image quality.
Description
Technical field
The utility model relates to a kind of multi-channel video input unit, and it comprises the video processing unit of compound component and band DRAM.
Background technology
The multi-channel video treatment technology is widely used in fields such as video monitoring, long-distance education, remote automation management, has obtained deep application in industries such as bank, traffic, electric power, telecommunications.At present can finish functions such as video compression, image recognition, video storage and remote transmission according to different application demands.
The normal video image through resolution after the digitlization is: PAL 720 * 576, and NTSC 720 * 480, or PAL 768 * 576, and NTSC 640 * 480, are called D1; For CIF resolution is PAL 352 * 288 or 384 * 288, NTSC 352 * 240 or 320 * 240.Common video processing unit can insert the normal video image and handle, and has following two kinds for the multipath digital video processing method:
1, adopt an independent cover treatment circuit for each road video, Fig. 1 represents the formation block diagram of this kind treatment circuit.Video processing unit is dsp chip or video dedicated processes chip, and normal video can be reduced into the CIF form in video processing unit, carries out various video images then and handles.The shortcoming of this mode is that each road all needs independent video processing unit, system complex, and cost height.
2, adopt four picture synthetic technologys, then composograph is handled, Fig. 2 represents the formation block diagram of this kind treatment circuit.The normal video image is reduced into the CIF form in four picture parts, then four CIF pictures are synthesized a standard picture, is input to video processing unit and carries out various video images processing.The shortcoming of this mode is that the video of input is reduced, therefore causes video resolution to reduce, and the while is the video of CIF picture if desired, can only realize the input of four road videos, thereby define range of application.
Summary of the invention
For overcoming the defective of prior art, the technical problems to be solved in the utility model has provided a kind of multi-channel video input unit of importing multi-channel video signal under the prerequisite that guarantees picture quality by a video port.
The technical solution of the utility model is: this multi-channel video input unit comprises the video processing unit of compound component and band DRAM, wherein said compound component, its multichannel standard digital vision signal with input synthesizes a digital video signal flow by the clock multiplier technology; Described video processing unit, its DRAM receives, stores the digital video signal stream after above-mentioned synthesizing, obtain the multipath digital video signal by separating reduction, and after these signals were handled respectively or compress, the output multichannel was corresponding to the data of the vision signal of input.
Because compound component synthesizes multi-channel video signal a video signal flow and obtains the data of multichannel corresponding to the vision signal of input by video processing unit separation reduction processing by the clock multiplier technology, thereby passes through a video port input multi-channel video signal under the prerequisite that guarantees picture quality.
Description of drawings
Fig. 1 is the formation block diagram of individual processing circuit of the prior art;
Fig. 2 is the synthetic formation block diagrams of handling of four pictures of the prior art;
Fig. 3 is a The general frame of the present utility model;
Fig. 4 is the block diagram of generated data of the present utility model;
Fig. 5 is the block diagram of another kind of generated data of the present utility model;
Fig. 6 is data synthetic waveform figure of the present utility model (is example with the two-way);
Data separating section processes schematic diagram in Fig. 7 video processing unit of the present utility model;
Data separating unit component software flow chart in Fig. 8 video processing unit of the present utility model;
Fig. 9 is the block diagram of embodiment of the Audio and Video Processing Card of employing pci interface of the present utility model;
Figure 10 is the block diagram of the embodiment of the Embedded video processing module of employing of the present utility model.
Embodiment
With reference to the accompanying drawings, will be described in detail embodiment of the present utility model.
Fig. 3 is a The general frame of the present utility model.After the digitlization of multi-channel video process A/D converter, compound component is combined into a data flow by the clock multiplier synthetic technology, outputs to video processing unit then, and video processing unit is the multi-channel video image with this data stream separation, does other processing of video again.Certainly, if multi-channel video signal itself is a digital signal, then need not to connect A/D converter and directly insert compound component and be combined into a data flow by the clock multiplier synthetic technology, output to video processing unit then, video processing unit is the multi-channel video image with this data stream separation, can carry out corresponding Video processing respectively to each road then.
Fig. 4 is the block diagram of generated data of the present utility model.The multi-channel analog vision signal is converted into the digital video signal that multichannel contains synchronizing information through A/D, adds approach information in each road video data, and being input to compound component again, to finish data synthetic.
Fig. 5 is the block diagram of another kind of generated data of the present utility model.What this mode adopted is the chip that multi-channel a/d converter and picture compound component become one.
Fig. 6 is data synthetic waveform figure of the present utility model.The 0th circuit-switched data and the 1st circuit-switched data are undertaken obtaining generated data after 2 frequencys multiplication are synthesized by the CLK clock frequency.
Data separating section processes schematic diagram in Fig. 7 video processing unit of the present utility model.Video data stream after synthetic enters in the DRAM memory of video processing unit, it is arranged as each road by the byte mode sequence arrangement, the road information that adds in advance by identification is determined first via Data Position earlier, then each byte being copied to different addresses respectively just can be with each road video data separately, pass through the analysis of synchronizing information again, just can obtain multi-path video data.
Data separating unit component software flow chart in Fig. 8 video processing unit of the present utility model.
Below in conjunction with two embodiment technology of the present utility model is further specified:
Fig. 9 is the block diagram of embodiment of the Audio and Video Processing Card of employing pci interface of the present utility model.N (N is the integer more than or equal to 1) road analog video signal is directly inputted to compound component, comprise N A/D converter in the compound component, N road analog video signal is converted to N way word vision signal through A/D, synthesize a video data stream then, must comprise synchronous identification code in this data flow, in the video data on every road, add approach information.Then video data is adopted the clock multiplier technology synthetic.Concrete principle is: insert N road video if desired, then at first with clock signal N frequency multiplication, then at first clock along output first via video data, at second clock along output the second road video data.The rest may be inferred, at N clock along output N road video data.Can only insert N road vision signal for video processing unit like this with a video interface.If after the N frequency multiplication, frequency has surpassed the receptible maximum of video processing unit, it is also conceivable that earlier video to be dwindled again to handle.N road simulated audio signal is converted to N way word audio signal by A/D, all digital video and audio signals are input to video processing unit, synthetic video signal flow is divided into the independent video data in N road by video processing unit, finish Video processing and compression then, audio frequency is also handled compression through video processing unit simultaneously, and rear video is handled in each road compression at last and audio sync synthesizes a data flow.The independent audio frequency and video generated data in last N road is sent to main frame through pci interface.
Figure 10 is the block diagram of the embodiment of the Embedded video processing module of employing of the present utility model.N road analog video signal is directly imported compound component, comprises N A/D converter in the compound component, and N road analog video synthesizes a video data stream then through being converted to N way word vision signal, and synthetic principle is with the clock multiplier technology among Fig. 9.N road simulated audio signal is converted to N way word audio signal by A/D.All digital video and audio signals are input to video processing unit, synthetic video signal flow is divided into the independent video data in N road by video processing unit, finish Video processing and compression then, audio frequency is also handled and compression through video processing unit simultaneously, and compression processed video and audio sync synthesize data.The independent audio frequency and video generated data corresponding to the audio-video signal of importing in last each road is sent to master control unit.Master control unit is the core control part of module, finishes the initialization and the work control of whole module, deposits data in hard disk by ide interface as required behind the receiving compressed data or sends on the network by network interface.Master control unit is finished and is shown control and input/output interface control simultaneously.
In circuit, compound component adopts TW2815, TW2816 or NV1000E, and video processing unit adopts TMS320DM64x series DSP, PNX-1500 series DSP or PNX-1700 series DSP.Certainly, the utility model is not limited to above chip model, all belongs to protection range of the present utility model as long as can realize the chip of Fig. 3-Figure 10.
Claims (6)
1, a kind of multi-channel video input unit, it comprises the video processing unit of compound component and band DRAM, it is characterized in that:
Described compound component, its multichannel standard digital vision signal with input synthesizes a digital video signal flow by the clock multiplier technology;
Described video processing unit, its DRAM receives, stores the digital video signal stream after above-mentioned synthesizing, obtain the multipath digital video signal by separating reduction, and these signals are handled respectively or compressed, the output multichannel is corresponding to the data of the vision signal of input.
2, according to the described multi-channel video input unit of claim 1, it is characterized in that: described compound component also comprises A/D converter, and it is converted to multichannel standard digital vision signal with the multi-channel analog vision signal.
3, according to the described multi-channel video input unit of claim 1, it is characterized in that: also be provided with the A/D converter that another kind of input signal is converted to digital signal, described another kind of input signal is the multipath audio signal corresponding to multi-channel video signal, multi-path digital audio signal after the conversion, be input to described video processing unit, distinguish described each the road audio signal of stored at corresponding each of the digital video signal of described correspondence with different addresses.
4, according to the described multi-channel video input unit of claim 3, it is characterized in that: the output termination pci interface parts of described video processing unit.
5, according to the described multi-channel video input unit of claim 3, it is characterized in that: the output termination master control unit of described video processing unit, the output termination of master control unit with data deposit in hard disk ide interface, data are sent to network of network interface, display interface or input and output control interface.
6, according to each described multi-channel video input unit of claim 1-5, it is characterized in that: compound component adopts TW2815, TW2816 or NV1000E, and video processing unit adopts TMS320DM64x series DSP, PNX-1500 series DSP or PNX-1700 series DSP.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200620120855 CN2912166Y (en) | 2006-07-05 | 2006-07-05 | Multi-rute video inputting device |
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| CN 200620120855 CN2912166Y (en) | 2006-07-05 | 2006-07-05 | Multi-rute video inputting device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103167267A (en) * | 2011-12-14 | 2013-06-19 | 北京铭智佳华通信技术有限公司 | Monitoring communication control desk |
| CN103581609A (en) * | 2012-07-23 | 2014-02-12 | 中兴通讯股份有限公司 | Video processing method, device and system |
| CN105187735A (en) * | 2015-07-23 | 2015-12-23 | 柳州永旺科技有限公司 | Synthesis method for multiple paths of dynamic images |
| CN107749299A (en) * | 2017-09-28 | 2018-03-02 | 福州瑞芯微电子股份有限公司 | A kind of multi-audio-frequencoutput output method and device |
-
2006
- 2006-07-05 CN CN 200620120855 patent/CN2912166Y/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103167267A (en) * | 2011-12-14 | 2013-06-19 | 北京铭智佳华通信技术有限公司 | Monitoring communication control desk |
| CN103581609A (en) * | 2012-07-23 | 2014-02-12 | 中兴通讯股份有限公司 | Video processing method, device and system |
| CN105187735A (en) * | 2015-07-23 | 2015-12-23 | 柳州永旺科技有限公司 | Synthesis method for multiple paths of dynamic images |
| CN107749299A (en) * | 2017-09-28 | 2018-03-02 | 福州瑞芯微电子股份有限公司 | A kind of multi-audio-frequencoutput output method and device |
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Owner name: BEIJING HANBANG TECHNOLOGY CORP., LTD. Free format text: FORMER NAME: BEIJING HANBANGGAOKE DIGITAL TECHNOLOGY CO., LTD. |
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| CP01 | Change in the name or title of a patent holder |
Address after: 100080, Room 403, block A, Zhongke building, 22 Zhongguancun street, Haidian District, Beijing Patentee after: Beijing Hanbang Gaoke Digital Technology Co., Ltd. Address before: 100080, Room 403, block A, Zhongke building, 22 Zhongguancun street, Haidian District, Beijing Patentee before: Beijing Hanbanggaoke Digital Technology Co.,Ltd. |
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Date of cancellation: 20120116 Granted publication date: 20070613 Pledgee: Zhongguancun Beijing science and technology Company limited by guarantee Pledgor: The Milky Way Albert Beijing Digital Technology Co. Ltd.|Beijing Hanbang Technology Co. Ltd. Registration number: 2009110000518 |
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Address after: 100089 Beijing City, Haidian District Changchun Road No. 11 Building No. 4 room 1-12 on the south side of the podium Patentee after: Beijing Hanbang Gaoke Digital Technology Co., Ltd. Address before: 100080, Room 403, block A, Zhongke building, 22 Zhongguancun street, Haidian District, Beijing Patentee before: Beijing Hanbang Gaoke Digital Technology Co., Ltd. |
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