CN103475843A - Method for converting double-LINK LVDS video signals into MIPI video signals - Google Patents
Method for converting double-LINK LVDS video signals into MIPI video signals Download PDFInfo
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Abstract
The invention discloses a method for converting double-LINK LVDS video signals into MIPI video signals. The method includes the following steps that first, video signals of all links of the double-LINK LVDS video signals are respectively received and demodulated at the same time, and parallel demodulation data of two links and a LVDS pixel clock are generated; second, video decoding is conducted on the parallel demodulation data of the two links to generate LVDS video source signals of the two links, the LVDS video source signals of each link comprise LVDS video source data and LVDS video source synchronizing signals, and the LVDS pixel clock is converted into an LVDS video source pixel clock; third, sampling and caching are simultaneously carried out on the LVDS video source signals of the two links by the LVDS video source pixel clock, and the LVDS video source signals are converted into RGB video signals; fourth, the RGB video signals are converted into the MIPI video signals. The method for converting the double-LINK LVDS video signals into the MIPI video signals has the advantages of being simple to operate, high in detection efficiency and low in cost.
Description
Technical field
The present invention relates to demonstration field and the field tests of liquid crystal module, refer to that particularly the LVDS vision signal of a kind of couple of LINK is converted to MIPI vision signal method.
Background technology
Liquid crystal display module (Liquid Crystal Display Module, hereinafter to be referred as liquid crystal module) is the critical component that liquid crystal display can normally show, it is by liquid crystal display screen, original paper backlight, Graphics Processing chip and the electric circuit constitute.Liquid crystal display module structure is accurate, processing procedure is complicated, manufacturing technique requirent is high, in order to guarantee yields when producing, need to produce various test video signals by special liquid crystal module testing apparatus and be input in liquid crystal module and show, strictly, comprehensively detect its display effect.Its display interface of common liquid crystals module of using on TV, display product at present and inner Graphics Processing circuit are used LVDS(Low-Voltage Differential Signaling, Low Voltage Differential Signal) signal carrys out work.And existing liquid crystal module testing device also corresponding output be that the LVDS vision signal is to realize the test of module.Because common liquid crystals module production time is of a specified duration, output is large, so its module testing apparatus also uses in a large number.
Constantly pursue high definition more, display effect more true to nature on mobile device, portable equipment along with people, therefore the common liquid crystals module can't meet the need gradually.So occurred on market that a kind of novel liquid crystal module with ultrahigh resolution and very-high solution density meets people's demand.The interface of this liquid crystal module and inner Graphics Processing circuit adopt MIPI(Mobile Industry Processor Interface to move the industry processor interface) signaling interface.This interface is formulated by the MIPI alliance that comprises the companies such as ARM, Samsung, Intel, purpose is that handle movement, inner each assembly of portable equipment are as nuclear interface standardizings and open each other such as camera, display screen, processors, thereby improved performance, reduced cost and power consumption.The MIPI interface can not only be supported ultrahigh resolution and refresh rate, and has farther transmission range, better Electro Magnetic Compatibility, and therefore the liquid crystal module with the MIPI interface has become development trend.
Yet the testing apparatus of MIPI liquid crystal module need to be exported same MIPI test signal, but existing common liquid crystals module testing apparatus does not have this function, and the common liquid crystals module also continues to produce, its testing apparatus does not enter the replacement cycle yet will be continued to use.Although the module manufacturer also produces the MIPI liquid crystal module, in order to protect investment, to reduce production costs, can not eliminate existing equipment, again make a big purchase expensive MIPI module Special testing device in large quantities.In order to produce cheaply the MIPI liquid crystal module in enormous quantities within short-term and to guarantee its yields, just still reuse on a large scale existing common module testing apparatus.
Therefore, need a kind of technical scheme the LVDS vision signal of two LINK can be converted to the MIPI vision signal, common liquid crystals module testing apparatus can be tested the MIPI module by this conversion equipment.
Summary of the invention
The object of the present invention is to provide the LVDS vision signal of a kind of couple of LINK to be converted to MIPI vision signal method, it has characteristics simple to operate, that detection efficiency is high, cost is low.
For achieving the above object, the LVDS vision signal of two LINK that the present invention is designed is converted to MIPI vision signal method, and its special character is, comprises the following steps:
Preferably, the LVDS vision signal of described couple of LINK comprises LINK1 and two links of LINK2, transmit respectively strange, the dual pixel data of the LVDS vision signal of two LINK, the LVDS vision signal of described each link comprises LVDS receive clock and LVDS data, described LVDS is transmitted by the LVDS data/address bus, described LVDS data/address bus comprises some root holding wires, and every holding wire transmits the serial code signal; Described MIPI vision signal shows module for the MIPI of 4LANE type.
Preferably, before in described step 1, the vision signal of each link being carried out to receiving demodulation, according to the characteristic of the LVDS vision signal of two LINK that will receive, LVDS vision signal decoding parametric is set, synchronous mode is controlled parameter; Receive MIPI video conversion configurations parameter, the configuration operation and the MIPI that carry out the MIPI conversion process show the module initialization operation; Produce LVDS coding standard control signal, LVDS video color range bit wide control signal, LVDS odd even pixel reverse control signal according to described LVDS vision signal decoding parametric; Control parameter generating LVDS synchronous mode control signal according to described synchronous mode; According to described MIPI video conversion configurations parameter generating MIPI conversion initialization command and MIPI module initialization command.
Preferably, the process of in described step 1, the vision signal of each link being carried out to receiving demodulation comprises: the serial code signal to LVDS data in described each link received is terminated respectively, demodulation, dynamic calibration, produces LVDS parallel demodulation data; The process of described termination comprises: LVDS terminating resistor coupling, LVDS signal level coupling, LVDS signal equalization and postemphasis, the signal buffering with rebuild; The process of described demodulation comprises: described LVDS receive clock is carried out to demodulation, produce demodulation clock and demodulation enable signal, serial code signal to the LVDS data of described each link is demodulated to separately parallel data respectively, and described LVDS receive clock is demodulated into described LVDS pixel clock simultaneously simultaneously.
Preferably, the process of in described step 2, described two link parallel demodulation data being carried out to video decode comprises: with described LVDS pixel clock, the first buffer memory of the parallel demodulation data of described each link is synchronously read again, then respectively the parallel demodulation data of described two links are decoded with the operation of sequential logic, obtained LVDS video source data and the LVDS video source synchronizing signal of two links.
While preferably, in described decode procedure, in described LVDS video decode control signal, receiving described odd even pixel reverse control signal, the data of LINK1 and LINK2 in described two links are exchanged.
Whether preferably, after forming described rgb video signal in described step 3, receive described LVDS synchronous mode control signal, detecting described rgb video signal is Low level effective, if described rgb video signal is Low level effective, by described rgb signal output; If described rgb video signal is that high level is effective, described rgb signal is transferred to after Low level effective described rgb signal output, send MIPI video conversion starting signal during output.
Preferably, the configuration operation of described execution MIPI conversion process and MIPI show that the module initialization operation comprises and receive after MIPI conversion initialization command the configuration operation of carrying out the MIPI conversion process, confirm to carry out again described MIPI module initialization command after configuration operation completes, and MIPI module initialization command is transferred to MIPI with the form of MIPI order shows module, complete the module initialization operation, send afterwards MIPI video conversion starting command when receiving described MIPI video conversion starting signal.
Preferably, phase place to described rgb video clock is adjusted, make its effective edge along near can the center in described rgb video source data, carry out again de-jitter, when described rgb signal output, compare effective edge of the described rgb video clock after debounce is moved and the deviation between described rgb video source data center, and utilize time delay to do trim process so that effective edge of described rgb video clock and described rgb video source data center remain alignment.
Preferably, the process that in described step 4, described rgb video signal is converted to the MIPI vision signal comprises: the configuration operation and the MIPI that carry out the MIPI conversion process show that the described rgb video signal that starts to receive after the module initialization operation when receiving described MIPI video conversion starting command is converted to the MIPI video signal transmission to described MIPI demonstration module.
Beneficial effect of the present invention is:
(1) the present invention can be converted to the MIPI vision signal by the LVDS vision signal of two LINK.The present invention is by arranging, and to different qualities such as the multiple color range of LVDS vision signal, transmission means, coded systems, all can well mate.
(2) the LVDS vision signal of convertible 6,8,10 color ranges of the present invention, the convertible LVDS signal based on VESA and JEIDA transfer encoding, can be changed the LVDS transmission mode of two LINK, is applicable to the MIPI liquid crystal module of 4LANE type.
(3) the present invention is before use only by manually changing the toggle switch state applicable to different LVDS vision signals; Before the different MIPI liquid crystal module of application, need to receive MIPI video conversion configurations parameter by jtag interface.
(4) single FPGA(field programmable logic array for the present invention) chip just can be realized described repertoire; FPGA is a kind of programmable semicustom chip, can realize the synchronous processing of multilink video data, parallel conversion, can reach higher performance, not only working stability, realization are easily, and low price, avoided the problems such as design complexity because using various special chips to cause, poor stability, design cost height.
(5) video resolution that the present invention supports is higher, not only integrated level is high, reliable operation, antijamming capability are strong, and simple to operate, economical and practical, can not only promote the detection efficiency of MIPI liquid crystal module, reduce its equipment cost and production cost, also will further improve the universal of MIPI display device.
The accompanying drawing explanation
Fig. 1 is flow chart of the present invention;
Fig. 2 is block diagram of the present invention;
The circuit block diagram of the LVDS video signal decoding unit of the LVDS video reception unit that Fig. 3 a is two LINK in Fig. 2 and two LINK;
The circuit block diagram that Fig. 3 b is rgb video signal converting unit in Fig. 2, MIPI vision signal converting unit and video conversion configurations unit;
The circuit diagram that Fig. 4 is rgb video modular converter in Fig. 3 b;
The LVDS vision signal that Fig. 5 is two LINK is converted to the signal graph of rgb video signal;
In figure: 1. the LVDS video reception unit of couple LINK, 1-1.LVDS video signal interface, 1-2.LVDS video reception termination module, the LVDS clock signal demodulation module of the two LINK of 1-3., 1-4. the LVDS demodulated data signal module of two LINK, 1-5.LVDS demodulation dynamic calibration module;
2. the LVDS video signal decoding unit of two LINK, 2-1.LVDS audio video synchronization buffer module, the LVDS odd even vision signal control module of the two LINK of 2-2., 2-3.LVDS video synchronization signal decoder module, the LVDS video data decoding module of the two LINK of 2-4.;
3.RGB the vision signal converting unit, 3-1.RGB video clock generation module, 3-2.RGB video conversion module, 3-2-1.LVDS signal sampling, 3-2-2.DC-FIFO buffer memory, 3-2-3.RGB signal sampling, 3-3.RGB video clock output adjusting module, 3-4.RGB vision signal output module;
4.MIPI the vision signal converting unit, 4-1.MIPI register module, 4-2.MIPI vision signal modular converter, 4-3.MIPI liquid crystal display module connector;
5. video conversion configurations unit, the manual toggle switch of 5-1., 5-2.JTAG interface, 5-3.MIPI video conversion configurations module;
6.MIPI demonstration module.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
As shown in Figures 1 to 5, the LVDS vision signal of a kind of couple of LINK of the present invention is converted to MIPI vision signal method, comprises the following steps:
The LVDS vision signal of two LINK comprises LINK1 and two links of LINK2, transmit respectively strange, the dual pixel data of the LVDS vision signal of two LINK, the LVDS vision signal of each link comprises LVDS receive clock and LVDS data, LVDS is transmitted by the LVDS data/address bus, the LVDS data/address bus comprises some root holding wires, and every holding wire transmits the serial code signal; The MIPI vision signal shows module for the MIPI of 4LANE type.
The LVDS vision signal refers to take the general name of the signal that the LVDS electrical characteristic be to characterize, and has the combination of the signal of string of different video pixel color range, signal transfer encoding standard, signal transmission link mode.The LVDS video signal characteristic of the two LINK that receive comprises: the color range of the LVDS video source pixel of two LINK that receive (consisting of tri-kinds of color components of RGB) can have 6 or 8 or 10, each pixel is all according to VESA or the JEIDA coding standard of LVDS transmission of video, by stringization and be encoded into one group of homochromy component level number corresponding 3 or 4 or 5 s' data signal line forms one group of data/address bus, with the electrical form of LVDS, transmit.
According to the characteristic of the LVDS vision signal of four LINK that will receive, LVDS vision signal decoding parametric is set, synchronous mode is controlled parameter; Receive MIPI video conversion configurations parameter, the configuration operation and the MIPI that carry out the MIPI conversion process show the module initialization operation; Produce LVDS coding standard control signal, LVDS video color range bit wide control signal, odd even pixel reverse control signal according to LVDS vision signal decoding parametric; Control parameter generating LVDS synchronous mode control signal according to synchronous mode; According to MIPI video conversion configurations parameter generating MIPI conversion initialization command and MIPI module initialization command.
LVDS vision signal decoding parametric comprises: LVDS video signal transmission coding standard has VESA and JEIDA; The pixel color component level of LVDS video source is wide 6,8,10; Synchronous mode is controlled parameter and is comprised high level effectively and Low level effective; MIPI video conversion configurations parameter comprises: the signal sequence of MIPI modular converter, transmission frequency, group pack mode, the display timing generator of MIPI liquid crystal display module, time delay Synchronization Control, initialization directive.By the manual toggle switch 5-1 in video conversion configurations unit 5, LVDS vision signal decoding parametric is set, by jtag interface 5-2, according to MIPI, shows that the type of module 6 receives MIPI video conversion configurations parameter.
Carry out the configuration operation of MIPI conversion process and MIPI and show that the module initialization operation comprises that MIPI video conversion configurations module 5-3 in video conversion configurations unit 5 receives after MIPI conversion initialization command the configuration operation of carrying out the MIPI conversion process, confirm to carry out again MIPI module initialization command after configuration operation completes, and MIPI module initialization command is transferred to liquid crystal module 6 with the form of MIPI order, complete the module initialization operation, when receiving the MIPI video conversion starting signal transmitted from rgb video signal converting unit 3, MIPI video conversion configurations module 5-3 sends MIPI video conversion starting command to MIPI vision signal converting unit 4 afterwards.
MIPI video conversion configurations module 5-3 first will receive MIPI conversion initialization command and write one by one in MIPI register module 4-1, read the state value of MIPI register module 4-1 after often writing an order, to guarantee that command execution completes, when confirm MIPI vision signal modular converter 4-2 complete configure and start normal operation after write again the order of MIPI demonstration module initialization register, the form that MIPI vision signal modular converter 4-2 is converted into the MIPI order is transferred to MIPI demonstration module 6, completes the module initialization operation.
Complete the configuration of decoding parametric, conversion parameter and produce corresponding control signal before the LVDS vision signal that receives two LINK.
The process of in step 1, the vision signal of each link being carried out to receiving demodulation comprises: the serial code signal to LVDS data in each link received is terminated respectively, demodulation, dynamic calibration, produces LVDS parallel demodulation data; The process of termination comprises: LVDS terminating resistor coupling, LVDS signal level coupling, LVDS signal equalization and postemphasis, the signal buffering with rebuild; The process of demodulation comprises: the LVDS receive clock is carried out to demodulation, produce demodulation clock and demodulation enable signal, serial code signal to the LVDS data of each link is demodulated to separately parallel data respectively, and the LVDS receive clock is demodulated into the LVDS pixel clock simultaneously simultaneously.
The LVDS vision signal of two LINK receives by the LVDS video signal interface 1-1 in the LVDS video reception unit 1 of two LINK, then by LVDS video reception termination module 1-2, is terminated.Purpose to LVDS vision signal termination is: the LVDS video signal quality of guaranteeing two LINK of receiving is high, noiseless.The process of termination comprises: before the LVDS vision signal that receives two LINK, carry out ESD(Electro Static Discharge static discharge) protective treatment disturbs with the strong discharge impact of eliminating moment, then carries out common-mode noise filtering processing to suppress line noise, to improve anti-electromagnetic interference capability.The distortion caused with the erasure signal transmission is processed in the impedance matching that is terminated when receiving signal, and also the additional interference of further erasure signal is carried out equilibrium and the processing of postemphasising to signal simultaneously, to eliminate the signal attenuation because loss was caused.Afterwards again to the signal Hyblid Buffer Amplifier, and reconstruct the LVDS vision signal of high-quality couple of LINK through the judgement of reference level.
The LVDS clock signal demodulation module 1-3 of two LINK carries out demodulation to the LVDS receive clock process of the LVDS vision signal of the two LINK by termination, and the LVDS data are carried out demodulation through the LVDS demodulated data signal module 1-4 of two LINK.LVDS receive clock demodulating process to each link comprises: the LVDS receive clock is carried out after speed buffering to frequency multiplication operation and high-frequency clock conversion process, produce with the LVDS demodulation clock of LVDS data same frequency and with the LVDS receive clock with LVDS pixel clock, LVDS demodulation gating signal frequently, and output in the high-frequency clock network, make them there is very low delay and jitter, very strong driving force, guarantee reliable and stable the LVDS data to be carried out to demodulation.Also carry out the moving calibration of clock jitter removing when the LVDS receive clock is carried out to the frequency multiplication operation, think that the subsequent operation generation is not affected by input jiffer, stable frequency-doubled signal.
LVDS data demodulation process to two LINK comprises: to each data independently demodulation respectively in the LVDS serial data bus of two LINK, by each LVDS data-signal its phase delay half-bit bit period after the speed buffering input, make this data value that samples that the LVDS demodulation clock can be correct at the center of each LVDS data bit, and according to the demodulation gating signal, it is periodically blocked to the bunchiness data, doing string with the LVDS pixel clock again turns and processes the parallel demodulation data that obtain this LVDS signal, each LVDS demodulating data is merged into to the LVDS demodulating data.The demodulation that each LVDS holding wire is all run simultaneously, make each holding wire no matter how data all can the phase mutual interference not cause the demodulation mistake.Also carry out the data dithering removal calibration the LVDS data being carried out to demodulation simultaneously, to produce, not affected by input jiffer, reliable and stable demodulating data.Phase delay process in the data input is subject to LVDS data flow phase alignment signal controlling all the time, when the phase place between demodulation clock and LVDS data has deviation, the phase alignment signal is made its delay adjustment contrary with phase deviation on data delay half period basis, make data center align along maintenance with the sampling of demodulation clock all the time, guarantee correctly to sample data.When the demodulation gating signal is blocked serial data, the bit that is subject to byte-aligned moves calibrating signal and controls, and the start bit that makes it the parallel data that will cut apart moves on next serial data position.
For guaranteeing that bits per inch is according to correctness and the reliability of separating timing, LVDS receive clock and each LVDS data of each link are carried out to dynamic calibration by LVDS demodulation dynamic calibration module 1-5 respectively in demodulation,
The process of in step 2, the parallel demodulation data of two links being carried out to video decode comprises: with the LVDS pixel clock to the parallel demodulation data/address bus of each link first in the LVDS audio video synchronization buffer module 2-1 in the LVDS of two LINK video signal decoding unit 2 buffer memory synchronously read again, then the LVDS video data decoding module of LVDS video synchronization signal decoder module 2-3 and two LINK is decoded with the operation of sequential logic to the parallel demodulation data/address bus of two links respectively, obtains LVDS video source data and the LVDS video source synchronizing signal of two links.The LVDS pixel clock of LINK1 is converted to LVDS video source pixel clock by the global clock path, with this, produces LVDS video source data and synchronizing signal.
Delay, the asynchronous situation that cause subsequent treatment mistake are arranged between for the LVDS signal of avoiding occurring two links in the LVDS vision signal in transmission, need to LVDS pixel clock separately, it be sampled and buffer memory respectively to the parallel demodulation data of each link, the buffer memory degree of depth is large as far as possible, so that all links have abundant data to be buffered to offset maximum delay between them, carry out synchronized sampling with LVDS video source pixel clock in the mode of fifo queue again, make it to become synchrodata.
When the LVDS odd even vision signal control module 2-2 of two LINK receives the odd even pixel reverse control signal in LVDS video decode control signal in decode procedure, the data of LINK1 and LINK2 are exchanged.
Because LVDS video signal transmission coding standard (VESA or JEDIA standard) is all supported 6 bits, 8 bits, the coding of 10 bit pixel color ranges, its LVDS video synchronization signal also together is encoded with video pixel data, and its coding rule separately is unique, therefore can obtain unique LVDS decoded video data according to LVDS video standard control signal and LVDS video bit wide control signal, pass through thus LVDS video source pixel clock respectively to LINK1, the demodulating data of LINK2 is decoded with the operation of sequential logic, recover LVDS video source synchronizing signal and the LVDS video source data signal of two LINK.
LVDS video source synchronizing signal comprises video level line synchronizing signal (Hsync), video perpendicualr field synchronizing signal (Vsync), video data useful signal (DE).Due in VESA and JEIDA coding standard, the mode of the coding of the synchronizing signal of each link with sequential identical, therefore only need will sequence after the synchronizing signal of the LINK1 that decode as LVDS video source synchronizing signal, also export.
Rgb video clock generating module 3-1 in rgb video signal converting unit 3 produces the rgb video clock of the twice that frequency is LVDS video source pixel clock; Rgb video modular converter 3-2 is combined into the parallel data of a link by the LVDS data of the LVDS video source synchronizing signal of two LINK and synchronous LINK1, LINK2 according to the form of " LINK1-data, synchronizing signal, LINK2-data, synchronizing signal ", sample in LVDS signal sampling 3-2-1 with LVDS video source pixel clock, and write buffer memory in DC-FIFO buffer memory 3-2-2; Rgb signal sampling 3-2-3 reads parallel data with the rgb video clock, and isolates rgb video source data and rgb video synchronizing signal, thereby completes conversion process.For data, because LINK1, LINK2 transmit respectively very, even data (being determined by the odd even reverse control signal), therefore the RGB data are actual is alternately to export LINK1,2(very-occasionally) data, thereby complete the conversion of all data, for synchronizing signal, because the RGB clock has read twice to it at each LVDS in the clock cycle, so the video sequential of RGB and LVDS is consistent; For transfer process, because DC-FIFO writes the data volume of twice a unit interval with the clock of a times, and by the data volume of one times of the Clockreading of twice, the throughput that is read-write operation equates, therefore not there will be and write completely or read empty situation, i.e. the carrying out of conversion operations energy continous-stable.
With DC-FIFO buffer memory 3-2-2 buffer memory the time, need the certain data volume of buffer memory to occur that with the delay of canceling DC-FIFO id reaction and LVDS signal transfer rate the caused read-write speed of fluctuation has fine difference (this fluctuation only causes that the data transmission rate that current video is capable changes, at line blanking period without affecting).
After forming rgb video signal, receiving LVDS synchronous mode control signal, whether be Low level effective, if rgb video signal is Low level effective, rgb signal is exported if detecting rgb video signal; If rgb video signal is that high level is effective, rgb signal is transferred to after Low level effective rgb signal output, send MIPI video conversion starting signal during output.
By in the process of rgb signal output, the processing of the rgb video clock being carried out with rgb video clock output adjusting module 3-3, comprise: the phase place to the rgb video clock is adjusted, make its effective edge along near can the center in the rgb video source data, carry out again de-jitter, when rgb signal is exported, compare effective edge of the rgb video clock after debounce is moved and the deviation between rgb video source data center, and utilize time delay to do trim process so that effective edge of rgb video clock and rgb video source data center remain alignment.
Due to rgb video data and rgb video clock synchronous, therefore the rgb video clock phase of input is postponed to half clock cycle as the RGB clock signal, make it effectively along near can the center in the rgb video data, thereby guarantee that follow-up conversion operations is by this clock RGB data of correctly sampling, this signal carries out de-jitter more afterwards, and by the high speed signal interface assembly of rgb video signal output module 3-4, it is exported, to guarantee this output clock, higher stability and signal quality are preferably arranged.
When starting to export RGB data and synchronizing signal, postpone to produce MIPI video conversion starting signal after some rgb video clocks, start 4 work of follow-up MIPI vision signal converting unit, doing like this is in order to make MIPI vision signal converting unit 4 receive at the very start normal video data, improves the reliability of MIPI conversion.
The process that in step 4, rgb video signal is converted to the MIPI vision signal comprises: after MIPI video conversion configurations module 5-3 carries out the configuration operation and MIPI demonstration module initialization operation of MIPI conversion process, MIPI video conversion configurations module 5-3 sends MIPI video conversion starting command after receiving MIPI video conversion starting signal, after MIPI register module 4-1 in MIPI vision signal converting unit 4 receives MIPI video conversion starting command, the rgb video signal that MIPI vision signal modular converter 4-2 starts to receive is converted to the MIPI vision signal, be transferred to MIPI by MIPI liquid crystal display module connector 4-4 and show module 6.
Transfer process comprises: when starting to carry out the MIPI conversion configurations, MIPI vision signal modular converter 4-2 is configured operation according to the MIPI register command write, and these MIPI register command comprise: the order of MIPI conversion configurations, MIPI show module initialization command, the order of MIPI conversion and control; After configuration completes, show the module initialization command according to the MIPI of write register, MIPI vision signal modular converter 4-2 is converted to these orders respectively the MIPI command signal and is transferred to the MIPI demonstration module 6 that MIPI liquid crystal display module connector 4-4 connects, and makes MIPI show that module 6 carries out initialization operation; When the order of MIPI video conversion and control writes MIPI register module 4-1, MIPI vision signal modular converter 4-2 is converted to the MIPI video signal transmission by the rgb video signal of input and shows that to the MIPI be connected with MIPI liquid crystal display module connector 4-4 module 6 shows afterwards.
The present invention is not limited to above-mentioned execution mode; for those skilled in the art, also be considered as the protection range of patent of the present invention according to know-why of the present invention and scheme or some improvement of making, change, retouching, distortion, replacement under enlightenment of the present invention within.
The content be not described in detail in this specification, write a Chinese character in simplified form, term belongs to the known prior art of professional and technical personnel in the field.
Claims (10)
1. the LVDS vision signal of two LINK is converted to MIPI vision signal method, it is characterized in that: comprise the following steps:
Step 1, the vision signal of each link of the LVDS vision signal of two LINK is carried out respectively to receiving demodulation simultaneously, produce parallel demodulation data and the LVDS pixel clock of two links;
Step 2, the parallel demodulation data of described two links are carried out to video decode, generate the LVDS video source signal of two links, the LVDS video source signal of described each link comprises LVDS video source data and LVDS video source synchronizing signal, and described LVDS pixel clock is converted into LVDS video source pixel clock;
Step 3, with described LVDS video source pixel clock, the LVDS video source signal of described two links is sampled and buffer memory simultaneously, and described LVDS video source signal is converted to rgb video signal; The process that described LVDS video source signal is converted to rgb video signal comprises: generate the rgb video clock, the twice that the frequency that makes described rgb video clock is described LVDS video source pixel clock, alternately read successively the signal of two links with described rgb video clock from buffer area, isolate rgb video source data and rgb video synchronizing signal, the difference Sequential output, thus described rgb video signal formed together with described rgb video clock;
Step 4, described rgb video signal is converted to the MIPI vision signal.
2. the LVDS vision signal of according to claim 1 couple of LINK is converted to MIPI vision signal method, it is characterized in that: the LVDS vision signal of described couple of LINK comprises LINK1 and two links of LINK2, transmit respectively strange, the dual pixel data of the LVDS vision signal of two LINK, the LVDS vision signal of described each link comprises LVDS receive clock and LVDS data, described LVDS is transmitted by the LVDS data/address bus, described LVDS data/address bus comprises some root holding wires, and every holding wire transmits the serial code signal; Described MIPI vision signal shows module for the MIPI of 4LANE type.
3. the LVDS vision signal of according to claim 1 couple of LINK is converted to MIPI vision signal method, it is characterized in that: before in described step 1, the vision signal of each link being carried out to receiving demodulation, according to the characteristic of the LVDS vision signal of two LINK that will receive, LVDS vision signal decoding parametric is set, synchronous mode is controlled parameter; Receive MIPI video conversion configurations parameter, the configuration operation and the MIPI that carry out the MIPI conversion process show the module initialization operation; Produce LVDS coding standard control signal, LVDS video color range bit wide control signal, LVDS odd even pixel reverse control signal according to described LVDS vision signal decoding parametric; Control parameter generating LVDS synchronous mode control signal according to described synchronous mode; According to described MIPI video conversion configurations parameter generating MIPI conversion initialization command and MIPI module initialization command.
4. the LVDS vision signal of according to claim 2 couple of LINK is converted to MIPI vision signal method, it is characterized in that: the process of in described step 1, the vision signal of each link being carried out to receiving demodulation comprises: the serial code signal to LVDS data in described each link received is terminated respectively, demodulation, dynamic calibration, produces LVDS parallel demodulation data; The process of described termination comprises: LVDS terminating resistor coupling, LVDS signal level coupling, LVDS signal equalization and postemphasis, the signal buffering with rebuild; The process of described demodulation comprises: described LVDS receive clock is carried out to demodulation, produce demodulation clock and demodulation enable signal, serial code signal to the LVDS data of described each link is demodulated to separately parallel data respectively, and described LVDS receive clock is demodulated into described LVDS pixel clock simultaneously simultaneously.
5. the LVDS vision signal of according to claim 2 couple of LINK is converted to MIPI vision signal method, it is characterized in that: the process of in described step 2, described two link parallel demodulation data being carried out to video decode comprises: with described LVDS pixel clock, the first buffer memory of the parallel demodulation data of described each link is synchronously read again, then respectively the parallel demodulation data of described two links are decoded with the operation of sequential logic, obtain LVDS video source data and the LVDS video source synchronizing signal of two links, described LVDS pixel clock is converted into LVDS video source pixel clock.
6. the LVDS vision signal of according to claim 3 couple of LINK is converted to MIPI vision signal method, it is characterized in that: while in described decode procedure, in described LVDS video decode control signal, receiving described odd even pixel reverse control signal, the data of LINK1 and LINK2 in described two links are exchanged.
7. the LVDS vision signal of according to claim 3 couple of LINK is converted to MIPI vision signal method, it is characterized in that: after forming described rgb video signal in described step 3, receive described LVDS synchronous mode control signal, whether detect described rgb video signal is Low level effective, if described rgb video signal is Low level effective, by described rgb signal output; If described rgb video signal is that high level is effective, described rgb signal is transferred to after Low level effective described rgb signal output, send MIPI video conversion starting signal during output.
8. the LVDS vision signal of according to claim 3 couple of LINK is converted to MIPI vision signal method, it is characterized in that: the configuration operation of described execution MIPI conversion process and MIPI show that the module initialization operation comprises and receive after MIPI conversion initialization command the configuration operation of carrying out the MIPI conversion process, confirm to carry out again described MIPI module initialization command after configuration operation completes, and MIPI module initialization command is transferred to MIPI with the form of MIPI order shows module (6), complete the module initialization operation, send afterwards MIPI video conversion starting command when receiving described MIPI video conversion starting signal.
9. the LVDS vision signal of according to claim 7 couple of LINK is converted to MIPI vision signal method, it is characterized in that: by the process of described rgb signal output, the processing that described rgb video clock is carried out comprises: the phase place to described rgb video clock is adjusted, make its effective edge along near can the center in described rgb video source data, carry out again de-jitter, when described rgb signal output, compare effective edge of the described rgb video clock after debounce is moved and the deviation between described rgb video source data center, and utilize time delay to do trim process so that effective edge of described rgb video clock and described rgb video source data center remain alignment.
10. the LVDS vision signal of according to claim 8 couple of LINK is converted to MIPI vision signal method, it is characterized in that: the process that in described step 4, described rgb video signal is converted to the MIPI vision signal comprises: the configuration operation and the MIPI that carry out the MIPI conversion process show that the described rgb video signal that starts to receive after the module initialization operation when receiving described MIPI video conversion starting command is converted to the MIPI video signal transmission and shows module (6) to described MIPI.
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