CN104717447A - Method for achieving 16LANE module multiple channel MIPI synchronous transmission - Google Patents
Method for achieving 16LANE module multiple channel MIPI synchronous transmission Download PDFInfo
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Abstract
The invention discloses a method for achieving 16LANE module multiple channel MIPI synchronous transmission. The method comprise the following steps: 1, receiving a serial video image signal of each channel from an image signal source, demodulating each serial video image signal of the corresponding channel into a four-LINK image signal, and adjusting the four-LINK image signals synchronously and conducting buffer memory; 2, reading the four-LINK image signals in the channels simultaneously and converting the four-LINK image signals into four-LINK RGB sub-module video data respectively; 3, switching each four-LINK RGB sub-module video datum of the corresponding channel to a corresponding output channel; 4, converting each four-LINK RGB sub-module video datum of the corresponding output channel into a four-LINK MIPI signal; 5, transmitting the four-LINK MIPI signals of the output channels simultaneously to modules to which the output channels are connected respectively.
Description
Technical field
The present invention relates to display and the field tests of MIPI liquid crystal module, refer to that one realizes 16LANE module multichannel MIPI synchronization transfer method particularly.
Background technology
MIPI vision signal is widely used in portable display device at present, the display module (hereinafter referred to as MIPI module or module) of traditional use MIPI signal, according to MIPI DSI agreement, uses the MIPI holding wire of 4Lane or 8Lane to transmit and display video image.But along with the raising of display resolution and transmission of video rate, the MIPI module of the 16Lane that market has occurred, the signal namely by the picture of ultrahigh resolution being split into four 1/4th submodule groups gives module displays respectively by four 4Lane MIPI holding wires.Four sub-module signal are encapsulated into comes together to show complete high definition picture, and a part for wherein each submodule group only display frame, and be the 4LANE module of MIPI agreement defined, thus form 16LANE module.
Due to the raising of the increase of MIPI signal Lane number and display resolution, transfer rate, the research and development technology of module and production technology is caused to become day by day complicated, thus make production cost increase, output reduction, in order to keep production efficiency, other unnecessary link and time must be reduced, and in module production testing link, still adopt the conventional method that each module is detected respectively, there is a large amount of repetitive operations as changed module, reloading image etc. in period, thus cause the Product checking time to increase, directly reduce production rate.
Therefore need a kind of invention to detect multiple 16Lane module simultaneously, and the signal source that can be switched to very easily on different passage is to detect different images, in order to ensure testing result reliability, avoid metrical error, need the tested module that the MIPI signal on each passage synchronously can reach connected.
Summary of the invention
For the deficiencies in the prior art, one provided by the invention realizes 16LANE module multichannel MIPI synchronization transfer method, can by the MIPI Signal transmissions of multichannel 16LANE to module, not only incoming video signal can be the picture signal of multiple passage, and the MIPI signal exported synchronously can be transferred to module.
For achieving the above object, the one designed by the present invention realizes 16LANE module multichannel MIPI synchronization transfer method, and its special character is, comprises the steps:
1) receive the serial video picture signal of each passage from image signal source (9), the serial video picture signal of described each passage is demodulated into the picture signal of four LINK, by the picture signal synchronous adjustment of described four LINK and buffer memory;
2) picture signal simultaneously reading four LINK in described each passage is also converted to the RGB submodule group video data of four LINK respectively;
3) the RGB submodule group video data of four LINK of described each passage is switched to corresponding output channel respectively;
4) the RGB submodule group video data of four LINK of described each output channel is converted to the MIPI signal of four LINK;
5) the MIPI signal of four LINK of described each output channel is transferred to simultaneously the module (8) be connected with each output channel respectively.
Preferably, in the picture signal of described four LINK, the picture signal of each LINK comprises a pair clock transfer line and four pairs of serial data lines.
Preferably, described step 1) in synchronous adjustment, described step 2) in while read and described step 5) in while transmit and all controlled by synchronous control signal.Synchronous control signal comprises synchronous conditioning signal, RGB synchronous switching control signal, MIPI transmitting synchronous control signal be respectively used to control described step 1) in synchronous adjustment, described step 2) in while read and described step 5) in while transmit.
Preferably, described step 1) in the video signal of buffer memory be half frame images signal in the video image of each passage.
Preferably, described step 1) before also comprise reset process: multichannel MIPI module reset signal is sent to the module be connected with each output channel respectively, makes synchronously to carry out reset operation with each channel attached module.
Preferably, the number of described passage is 1 ~ 12.The present invention is applicable to 1 ~ 12 passage transmission video signal simultaneously, to realize synchronously receiving MIPI vision signal with each channel attached liquid crystal module.
Preferably, described RGB submodule group video data comprises the serial data line of a pair clock transfer line and four pairs of split screen mode arrangements.
Preferably, described RGB submodule group video data comprises a pair clock transfer line and four to a point serial data line for pixel-wise arrangement.
Preferably, also comprise synchronous adjustment step before described reset process: receive according to MIPI module the transmission electric parameter that synchronous conditioning signal arranges each output channel, described MIPI module receives synchronous conditioning signal and comprises the output time delay of each passage, drives the electric parameter of intensity, level, impedance matching, transmission attenuation.
Preferably, described multichannel MIPI module reset signal comprises the poorest sequential of module reset, and the poorest sequential of described module reset is the reset timing maximum of the module of each passage.For guaranteeing each module reliable reset, the poorest sequential that the sequential of MIPI module reset signal resets by the module that upper strata provides produces, and issue each module by multichannel MIPI synchronous output module, make the reset operation receiving identical signal quality that each module energy is synchronous.
Beneficial effect of the present invention is:
(1) the present invention can detect multiple module simultaneously, and the signal source that can be switched to very easily on different passage is to detect different images, and guarantee testing result reliability, avoid metrical error.
(2) the present invention can input the signal source image of multiple passage and convert thereof into MIPI Signal transmissions to the MIPI module of each passage.By the switching controls of upper layer software (applications), both the image of a certain input channel can be switched the module outputted on a certain passage, the image of a certain input channel can be outputted to again the module on whole passage, form one to one and one to many MIPI transmission.
(3) the present invention is by Synchronization Control, the input and output adjusting each passage, makes each module all can receive MIPI signal in the same time mutually, avoids asynchronous a caused metrical error of screen.
(4) the present invention can detect 16Lane module, and the module characteristic on all passages needs identical with resolution, transmits input to the signal transmission in different images source by the configuration realization of upper layer software (applications).
(5) the present invention is by realizing with fpga chip, and not only working stability, reliability are high, realizes easily, and low price, easy and simple to handle.
Accompanying drawing explanation
Fig. 1 realizes the circuit block diagram realizing 16LANE module multichannel MIPI synchronous transmission device of the present invention;
Fig. 2 is the flow chart that the present invention realizes 16LANE module multichannel MIPI synchronization transfer method.
Fig. 3 is the schematic diagram of the RGB submodule group video data split screen arrangement in a Link.
Fig. 4 is the schematic diagram of the RGB submodule group video data point pixel arrangement in a Link.
In figure: MIPI synchronization control module 1, multichannel LINK transmits input module 2, input synchronization module 3, RGB modular converter 4, multichannel RGB synchronism switching module 5, MIPI modular converter 6, multichannel MIPI synchronous output module 7, module 8, image signal source 9.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
As shown in Figure 1, the present invention realizes by realizing 16LANE module multichannel MIPI synchronous transmission device, and this device comprises MIPI synchronization control module 1, multichannel LINK transmits input module 2, input synchronization module 3, RGB modular converter 4, multichannel RGB synchronism switching module 5, MIPI modular converter 6 and multichannel MIPI synchronous output module 7.
MIPI synchronization control module 1 transmits input module 2, RGB synchronism switching module 5, MIPI modular converter 6 and multichannel MIPI synchronous output module 7 respectively input with multichannel LINK is connected; The input that multichannel LINK transmits input module 2 is also connected with image signal source 9, and output is connected with input synchronization module 3; The input of input synchronization module 3 transmits input module 2 with multichannel LINK and is connected, and output is connected with RGB modular converter 4; The input of RGB modular converter 4 is connected with input synchronization module 3, and output is connected with multichannel RGB synchronism switching module 5; The input of multichannel RGB synchronism switching module 5 is also connected with RGB modular converter 4, and output is connected with MIPI modular converter 6; The input of MIPI modular converter 6 is also connected with multichannel RGB synchronism switching module 5, and output is connected with multichannel MIPI synchronous output module 7; The input of multichannel MIPI synchronous output module 7 is also connected with MIPI modular converter 6, and output is connected with module 8.Transmission channel number is identical with the number of module 8, and each output channel of multichannel MIPI synchronous output module 7 is connected with a module 8 respectively.Such as, the number of passage is 5, then five liquid crystal module 8 can synchronously receive MIPI signal.
Refer to particularly, MIPI synchronization control module 1 sends MIPI module to multichannel MIPI synchronous output module 7 and receives synchronous conditioning signal and multichannel MIPI module reset signal, transmit input module 2 to multichannel LINK and send LINK signal transmission parameters signalization and LINK signal input electric synchronization adjustment signal, send RGB synchronous switching control signal to multichannel RGB synchronism switching module 5, send multichannel MIPI to MIPI modular converter 6 and to spread its tail instruction and MIPI transmitting synchronous control signal.
Multichannel LINK transmits input module 2 for receiving the video signal of each passage from image signal source 9, and according to the video signal of each passage of LINK signal transmission parameters signalization demodulation, the video signal adjusting each passage according to LINK signal input electric synchronization adjustment signal, then the video signal of each passage is transferred to input synchronization module 3.
The video signal of each passage that input synchronization module 3 receives for buffer memory.
RGB modular converter 4 is converted to RGB data respectively for the video signal simultaneously reading each passage from input synchronization module 3 and is sent to multichannel RGB synchronism switching module 5.
Multichannel RGB synchronism switching module 5 for according to RGB synchronous switching control signal by the RGB data synchronous driving of each passage to MIPI modular converter 6.
MIPI modular converter 6 sends to each passage of multichannel MIPI synchronous output module 7 command M IPI signal of spreading its tail for spread its tail according to multichannel MIPI instruction and MIPI transmitting synchronous control signal simultaneously, and is sent to multichannel MIPI synchronous output module 7 according to MIPI transmitting synchronous control signal again after the RGB data of each passage is converted to MIPI signal respectively.
Multichannel MIPI synchronous output module 7 arranges the transmission electric parameter of each passage for receiving synchronous conditioning signal according to MIPI module, and multichannel MIPI module reset signal and MIPI signal are sent to respectively with each channel attached module 8.
Realize the flow chart of multichannel MIPI synchronization transfer method as shown in Figure 2 by the above-mentioned multichannel MIPI synchronous transmission device that realizes, concrete steps comprise:
Step 1), before powering on, first the 16Lane module 8 of each passage is connected in multichannel MIPI synchronous output module 7.Synchronous adjustment step: according to the connecting line of the module 8 be connected on each passage or the parameter such as length, transmission characteristic, material of connector, carry out arranging (its physical characteristic can be variant when reality uses for each connecting line) in upper layer software (applications), and its MIPI that arranges to connecting line is exported electric synchronization adjustment signal and issues multichannel MIPI synchronous output module 7 by MIPI synchronization control module 1 again after electricity on the invention.
Multichannel MIPI synchronous output module 7 then adjusts carrying out the electric parameter such as output time delay, driving intensity, level, impedance matching, transmission attenuation between each output channel according to this control signal, object is the MIPI signal making to export is completely simultaneously when being transferred to each module 8, the MIPI signal that module 8 receives is identical on electrical quality, thus avoids the point caused because of transmission line characteristics difference to shield the difference of effect.
Inerrancy is shielded for making to light 16Lane in a passage, need to guarantee that multichannel MIPI synchronous output module 7 li of each passages are identical on physical layer, during as realized in FPGA, need guarantee that the logical design of each passage exports in same BANK, same layout clock unit, identical work schedule, identical voltage, electric current, variations in temperature with IO.
Step 2), after multichannel MIPI synchronous output module 7 has configured, upper layer software (applications) sends upper strata input control signal to MIPI synchronization control module 1 li, the poorest sequential that upper strata input control signal comprises the instruction of spreading its tail (because each module 8 is same type, instruction is also identical therefore it is spread its tail) of each module 8, module resets, LINK signal transmission parameters signalization, the adjustment of LINK signal input electric synchronization signal, image switching controls; Start apparatus of the present invention work afterwards.
Reset process: MIPI synchronization control module 1 produces multichannel to MIPI module reset signal, for guaranteeing each module 8 reliable reset, therefore the poorest sequential that the sequential of this reset signal resets by the module that upper strata provides produces, and issue each module 8 by multichannel MIPI synchronous output module 7, make the reset operation receiving identical signal quality that each module 8 energy is synchronous.
Step 3), MIPI synchronization control module 1 postpone after having produced reset signal the sufficiently long time carry out next step operation with the reseting procedure making each module 8 can complete self completely.Afterwards, the instruction of spreading its tail of each module 8 is issued the MIPI modular converter 6 of each passage to produce the corresponding MIPI signal containing instruction of spreading its tail by MIPI synchronization control module 1, module 8 is sent in feeding multichannel MIPI synchronous output module 7 respective channel, terminate for taking into account module 8 the spread its tail real-time of instruction and synchronism, MIPI synchronization control module 1 synchronously carries out the operation such as reading, generation, output, time delay of each instruction by the MIPI modular converter 6 that MIPI transmitting synchronous control signal controls each passage.
Step 4), after instruction of spreading its tail all sends to module, MIPI synchronization control module 1 again delayed startup multichannel LINK transmission input module 2 has guaranteed that modules all can accept completely and perform the configuration of instruction of spreading its tail.After multichannel LINK transmits input module 2 startup, multichannel LINK transmits the serial video picture signal that input module 2 receives each passage of image signal source 9, according to LINK signal transmission parameters signalization, the serial video picture signal of each passage is demodulated into the picture signal of four LINK, in the picture signal of four LINK, the picture signal of each LINK comprises a pair clock transfer line and four pairs of serial data lines.Multichannel LINK transmits input module guarantees the Signal transmissions timing synchronization of four LINK and identical (generally decomposing multiple LINK on transmission to reduce transmission rate, raising transmission reliability to the vision signal of large resolution and big data quantity) according to LINK signal input electric synchronization adjustment signal again in physical electrical characteristic.
Step 5), multichannel LINK transmits input synchronization module 3 buffer memory that four of each passage LINK restituted signals are sent into respective channel by input module 2, for guaranteeing that the resource restriction in FPGA is considered again in reliable synchronization process, each LINK is buffer memory half frame images data respectively, read the picture signal of four LINK in each passage by RGB modular converter 4 more simultaneously and be converted to the RGB submodule group video data of four LINK respectively, and sending into multichannel RGB synchronism switching module 5.
The RGB submodule group video data picture signal of four LINK being converted to four LINK that 16Lane module 8 needs has split screen arrangement and a point pixel to arrange two kinds of methods.The picture signal of each LINK comprises a pair clock transfer line and four pairs of serial data lines, wherein often pair of serial data line can arrange according to split screen arrangement and point pixel the RGB submodule group video data that two kinds of modes are converted to 1/4 submodule group video data, 2/4 submodule group video data, 3/4 submodule group video data, 4/4 these four Lane of submodule group video data, i.e. the RGB submodule group video data of four Link formation 16Lane.When arranging according to split screen, as shown in Figure 3, the pixel in each Link is arranged in order as RGB submodule group video data according to four Lane; During according to the arrangement of point pixel, as shown in Figure 4, the pixel in each Link first arranges and then enters next Lane and arrange in a Lane, formation RGB submodule group video data.
Step 6), the RGB submodule group data being transfused to each passage of multichannel RGB synchronism switching module 5 are because of in the transmission time, the demodulation process time, logical sequence, or the difference on physical circuit causes having time delay each other to during multichannel RGB synchronism switching module 5, accumulate in time, time delay strengthens gradually, therefore buffer memory half frame data are needed again, multichannel RGB synchronism switching module 5 reads simultaneously again afterwards, and according to RGB synchronous switching control handshaking on required passage, this switching forms the switching matrix of n × n, both can export one to one, can export by one-to-many again.After multichannel RGB synchronism switching module 5, the output of each passage has been the RGB submodule group video data of the 16Lane of Complete Synchronization.
Step 7), MIPI modular converter 6 is sent to multichannel MIPI synchronous output module 7 according to MIPI transmitting synchronous control signal after the RGB submodule group data of the 16Lane of each passage are converted to MIPI signal respectively more simultaneously.
The RGB submodule group data of the 16Lane of input are carried out MIPI conversion with the MIPI signal producing 16Lane by the MIPI modular converter 6 of each passage, and the MIPI transmitting synchronous control signal of all giving by MIPI synchronization control module 1 in the operation such as reading, conversion, sequencing control, transmission state change of conversion is carried out, the equal Complete Synchronization of each operating procedure of each passage controls, and on physical circuit realizes, the MIPI modular converter 6 of each passage is all on same structure or BANK, use same system clock work, thus ensure that transfer process Complete Synchronization.
Step 8), multichannel MIPI synchronous output module 7 the MIPI signal of 16Lane is sent to respectively with each channel attached module 8, the MIPI signal of the 16Lane that module 8 simultaneous display receives.
Multichannel MIPI synchronous output module 7 ditto described by the MIPI Signal transmissions of 16Lane to module.MIPI code book is as LP state and HS state alternate transport simultaneously, this two states is electrical characteristic of different nature (the former be LVDS for LVCOMS, the latter) respectively, therefore in multichannel MIPI synchronous output module 7 output procedure, MIPI synchronization control module 1 still informs its current MIPI signal condition, multichannel MIPI synchronous output module 7 is corresponding does different electric adjustment, thus guarantees that module 8 receives the MIPI signal of the 16Lane of complete synchronization.
Below be only the preferred embodiment of the present invention, it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention, can also design some improvement, these improvement also should be considered as protection scope of the present invention.
The content that this specification is not described in detail belongs to the known prior art of professional and technical personnel in the field.
Claims (10)
1. realize a 16LANE module multichannel MIPI synchronization transfer method, it is characterized in that: comprise the steps:
1) receive the serial video picture signal of each passage from image signal source (9), the serial video picture signal of described each passage is demodulated into the picture signal of four LINK, by the picture signal synchronous adjustment of described four LINK and buffer memory;
2) picture signal simultaneously reading four LINK in described each passage is also converted to the RGB submodule group video data of four LINK respectively;
3) the RGB submodule group video data of four LINK of described each passage is switched to corresponding output channel respectively;
4) the RGB submodule group video data of four LINK of described each output channel is converted to the MIPI signal of four LINK;
5) the MIPI signal of four LINK of described each output channel is transferred to simultaneously the module (8) be connected with each output channel respectively.
2. according to claim 1ly realize 16LANE module multichannel MIPI synchronization transfer method, it is characterized in that: in the picture signal of described four LINK, the picture signal of each LINK comprises a pair clock transfer line and four pairs of serial data lines.
3. according to claim 1ly realize 16LANE module multichannel MIPI synchronization transfer method, it is characterized in that: described step 1) in synchronous adjustment, described step 2) in while read and described step 5) in while transmit and all controlled by synchronous control signal.
4. according to claim 1ly realize 16LANE module multichannel MIPI synchronization transfer method, it is characterized in that: described step 1) in the video signal of buffer memory be half frame images signal in the video image of each passage.
5. according to claim 1ly realize 16LANE module multichannel MIPI synchronization transfer method, it is characterized in that: described step 1) before also comprise reset process: multichannel MIPI module reset signal is sent to the module (8) be connected with each output channel respectively, makes synchronously to carry out reset operation with each channel attached module (8).
6. according to claim 1ly realize 16LANE module multichannel MIPI synchronization transfer method, it is characterized in that: the number of described passage is 1 ~ 12.
7. according to claim 2ly realize 16LANE module multichannel MIPI synchronization transfer method, it is characterized in that: described RGB submodule group video data comprises the serial data line of a pair clock transfer line and four pairs of split screen mode arrangements.
8. according to claim 2ly realize 16LANE module multichannel MIPI synchronization transfer method, it is characterized in that: described RGB submodule group video data comprises a pair clock transfer line and four to point serial data lines for pixel-wise arrangement.
9. according to claim 5ly realize 16LANE module multichannel MIPI synchronization transfer method, it is characterized in that: also comprise synchronous adjustment step before described reset process: receive according to MIPI module the transmission electric parameter that synchronous conditioning signal arranges each output channel, described MIPI module receives synchronous conditioning signal and comprises the output time delay of each passage, drives the electric parameter of intensity, level, impedance matching, transmission attenuation.
10. according to claim 9ly realize 16LANE module multichannel MIPI synchronization transfer method, it is characterized in that: described multichannel MIPI module reset signal comprises the poorest sequential of module reset, the poorest sequential of described module reset is the reset timing maximum of the module (8) of each passage.
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| CN110138761A (en) * | 2019-05-09 | 2019-08-16 | 深圳吉迪思电子科技有限公司 | Communication between devices method and apparatus topological structure based on MIPI agreement |
| CN110138761B (en) * | 2019-05-09 | 2021-10-15 | 豪威触控与显示科技(深圳)有限公司 | MIPI (Mobile industry processor interface) protocol-based inter-device communication method and equipment topological structure |
| CN111770520A (en) * | 2020-07-22 | 2020-10-13 | Oppo广东移动通信有限公司 | MIPI-based data transmission method, device, equipment and medium |
| CN111770520B (en) * | 2020-07-22 | 2023-02-28 | Oppo广东移动通信有限公司 | MIPI-based data transmission method, device, equipment and medium |
| CN114286133A (en) * | 2021-12-28 | 2022-04-05 | 京东方科技集团股份有限公司 | Image data processing method and device and display system |
| CN115955589A (en) * | 2022-12-16 | 2023-04-11 | 苏州华兴源创科技股份有限公司 | Optimized video splicing method, system and storage medium based on MIPI |
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