CN104717447B - Realize 16LANE module multichannel MIPI synchronization transfer methods - Google Patents
Realize 16LANE module multichannel MIPI synchronization transfer methods Download PDFInfo
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Abstract
The invention discloses a kind of realization 16LANE module multichannel MIPI synchronization transfer methods to include the following steps：1) the serial video picture signal of each channel is received from image signal source, the serial video picture signal of each channel is demodulated into the picture signal of four LINK, by the picture signal synchronous adjustment of four LINK and is cached；2) it while reads the picture signal of four LINK in each channel and is respectively converted into the RGB submodule group video datas of four LINK；3) the RGB submodule group video datas of four LINK of each channel are switched into corresponding output channel respectively；4) the RGB submodule group video datas of four LINK of each output channel are converted into the MIPI signals of four LINK；5) by the MIPI signals simultaneous transmission of four LINK of each output channel to the module being connect respectively with each output channel.
Description
Technical field
Display and testing field the present invention relates to MIPI liquid crystal modules, it is mostly logical in particular to a kind of realization 16LANE modules
Road MIPI synchronization transfer methods.
Background technology
MIPI vision signals are widely used in portable display device at present, traditional display mould using MIPI signals
Group (hereinafter referred to as MIPI modules or module) is passed according to MIPI DSI agreements using the MIPI signal wires of 4Lane or 8Lane
It is defeated and show video image.But with the raising of display resolution and transmission of video rate, the 16Lane's occurred in the market
MIPI modules, i.e., by the way that the picture of ultrahigh resolution to be split into the signal of four a quarter submodule groups respectively by four
4Lane MIPI signal wires give module displays.Four sub- module signals are packaged together showing complete high definition picture, and its
In each submodule group only show the part of picture, and be the 4LANE modules of MIPI agreement defineds, thus form 16LANE
Module.
Due to the increase of MIPI signal Lane numbers and display resolution, the raising of transmission rate, lead to the research and development technology of module
Become increasingly complicated with production technology, so that the production cost increases, yield reduces, in order to keep production efficiency, it is necessary to subtract
Other few unnecessary links and time, and still using the biography detected respectively to each module in module produces detection
During which system method such as replaces module there are a large amount of repetitive operation, reloads image, increase so as to cause the product testing time
Add, directly reduce production rate.
Therefore need a kind of invention that can be detected simultaneously to multiple 16Lane modules, and can very easily be switched to not
With the signal source on channel to detect different images, reliability in order to ensure testing result avoids detection error, needs each
MIPI signals on channel can synchronize the tested module for reaching and being connected.
Invention content
In view of the deficiencies of the prior art, a kind of realization 16LANE module multichannel MIPI synchronous transfer sides provided by the invention
Method, can be by the MIPI signal transmissions of multichannel 16LANE to module, and not only incoming video signal can be that the image of multiple channels is believed
Number, and the MIPI signals exported can be synchronously transferred to module.
To achieve the above object, a kind of realization 16LANE modules multichannel MIPI synchronous transfer sides designed by the present invention
Method is characterized in that, is included the following steps：
1) the serial video picture signal of each channel is received from image signal source (9), by the serial of each channel
Video signal is demodulated into the picture signal of four LINK, by the picture signal synchronous adjustment of four LINK and caches；
2) it while reads the picture signal of four LINK in each channel and is respectively converted into RGB of four LINK
Module video data；
3) the RGB submodule group video datas of four LINK of each channel are switched to corresponding output respectively to lead to
Road；
4) the RGB submodule group video datas of four LINK of each output channel are converted into the MIPI of four LINK
Signal；
5) by the MIPI signals simultaneous transmission of four LINK of each output channel to respectively with each output channel
The module (8) of connection.
Preferably, in the picture signal of four LINK the picture signal of each LINK include a pair of of clock transfer line and
Four pairs of serial data lines.
Preferably, the synchronous adjustment in the step 1), in the step 2) while read and the step 5) in
Simultaneous transmission is controlled by synchronous control signal.Synchronous control signal includes synchronous conditioning signal, RGB synchronous switching controls are believed
Number, MIPI transmission synchronous control signals be respectively used to control synchronous adjustment in the step 1), in the step 2) while
It is transmitted while reading in the step 5).
Preferably, the video signal cached in the step 1) is the half frame images in the video image of each channel
Signal.
Preferably, reset process is further included before the step 1)：The module being connect respectively with each output channel is sent out
Send multichannel MIPI module reset signals, make with each channel attached module synchronize carry out reset operation.
Preferably, the number of the channel is 1~12.The present invention is suitable for 1~12 channel simultaneous transmission vision signal,
MIPI vision signals are received so that realization is synchronous with each channel attached liquid crystal module.
Preferably, the RGB submodules group video data includes a pair of of clock transfer line and the string of four pairs of split screen mode arrangements
Row data line.
Preferably, the RGB submodules group video data is arranged including a pair of of clock transfer line and four pairs of points of pixel-wises
Serial data line.
Preferably, synchronous adjustment step is further included before the reset process：Synchronous adjustment letter is received according to MIPI modules
The transmission electric parameter of number each output channel of setting, the MIPI modules receive synchronous conditioning signal and include the defeated of each channel
Go out the electric parameter of delay, driving intensity, level, impedance matching, transmission attenuation.
Preferably, the multichannel MIPI modules reset signal includes the worst sequential of module reset, and the module resets most
Reset timing maximum value of the poor sequential for the module of each channel.To ensure each module reliable reset, MIPI modules reset letter
Number sequential generated by the worst sequential that the module that upper strata provides resets, and pass through multichannel MIPI synchronous output modules and issue respectively
A module so that each module can synchronize receives the reset operation of identical signal quality.
The beneficial effects of the present invention are：
(1) present invention can be detected multiple modules, and the letter that can be very easily switched on different channels simultaneously
Number source ensures the reliability of testing result, avoids detection error to detect different images.
(2) present invention can input the signal source images of multiple channels and convert thereof into MIPI signal transmissions to each channel
MIPI modules.By the switching control of upper layer software (applications), the image of a certain input channel can both be switched and be output to a certain channel
On module, and the module that can be output to the image of a certain input channel on whole channels forms one to one and one to more
MIPI is transmitted.
(3) present invention passes through Synchronization Control, the input and output of each channel of adjustment so that each module can be received mutually in the same time
To MIPI signals, the asynchronous caused detection error of a screen is avoided.
(4) present invention can detect 16Lane modules, and the module characteristic and resolution ratio needs on all channels are identical, to not
Transmission signal with image source can realize transmission input by the configuration of upper layer software (applications).
(5) present invention can be realized by using fpga chip, and not only the operation is stable, reliability are high, and it is easy to realize, and valency
Lattice are cheap, easy to operate.
Description of the drawings
The circuit block diagram of the realization 16LANE module multichannel MIPI synchronous transmission devices of Fig. 1 to realize the present invention；
Fig. 2 is the flow chart that the present invention realizes 16LANE module multichannel MIPI synchronization transfer methods.
Fig. 3 is the schematic diagram of the RGB submodule group video datas split screen arrangement in a Link.
Fig. 4 divides the schematic diagram of pixel arrangement for the RGB submodule group video datas in a Link.
In figure：MIPI synchronization control modules 1, multichannel LINK transmission input modules 2 input synchronization module 3, RGB conversions
Module 4, multichannel RGB synchronism switchings module 5, MIPI modular converters 6, multichannel MIPI synchronous output modules 7, module 8, image
Signal source 9.
Specific embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
As shown in Figure 1, the present invention can be by realizing that 16LANE module multichannel MIPI synchronous transmission devices are realized, the device
Including MIPI synchronization control modules 1, multichannel LINK transmission input module 2, input synchronization module 3, RGB modular converters 4, lead to more
Road RGB synchronism switchings module 5, MIPI modular converters 6 and multichannel MIPI synchronous output modules 7.
MIPI synchronization control modules 1 transmit input module 2, RGB synchronism switchings module 5, MIPI with multichannel LINK respectively
Modular converter 6 is connected with the input terminal of multichannel MIPI synchronous output modules 7；Multichannel LINK transmits the input of input module 2
End is also connect with image signal source 9, and output terminal is connect with input synchronization module 3；Input the input terminal and multichannel of synchronization module 3
LINK transmission input modules 2 connect, and output terminal is connect with RGB modular converters 4；The input terminal of RGB modular converters 4 is synchronous with input
Module 3 connects, and output terminal is connect with multichannel RGB synchronism switchings module 5；The input terminal of multichannel RGB synchronism switchings module 5 is also
It is connect with RGB modular converters 4, output terminal is connect with MIPI modular converters 6；The input terminal of MIPI modular converters 6 also with multichannel
RGB synchronism switchings module 5 connects, and output terminal is connect with multichannel MIPI synchronous output modules 7；Multichannel MIPI synchronism output moulds
The input terminal of block 7 is also connect with MIPI modular converters 6, and output terminal is connect with module 8.Transmission channel number and the number of module 8
Identical, each output channel of multichannel MIPI synchronous output modules 7 is connect respectively with a module 8.For example, the number of channel
It is 5, then five liquid crystal modules 8, which can synchronize, receives MIPI signals.
In particular to MIPI synchronization control modules 1 send MIPI modules to multichannel MIPI synchronous output modules 7 and receive together
Step entire signal and multichannel MIPI module reset signals send LINK signal transmissions to multichannel LINK transmission input modules 2
Parameter setting signal and LINK signals input electric synchronization adjustment signal, it is same to send RGB to multichannel RGB synchronism switchings module 5
Switch-over control signal is walked, sending spread its tail instruction and MIPI of multichannel MIPI to MIPI modular converters 6 transmits synchronous control signal.
Multichannel LINK transmission input modules 2 are used to receive the video signal of each channel from image signal source 9, and
It is inputted according to the video signal of each channel of LINK signal transmission parameters setting signal demodulation, according to LINK signals electrical same
Step entire signal adjusts the video signal of each channel, and it is same that the video signal of each channel then is transmitted to input
Walk module 3.
The video signal of each channel that input synchronization module 3 is received for caching.
RGB modular converters 4 are converted respectively for reading the video signal of each channel from input synchronization module 3 simultaneously
For RGB data and it is sent to multichannel RGB synchronism switchings module 5.
Multichannel RGB synchronism switchings module 5 is used for the RGB data of each channel according to RGB synchronous switching controls signal
Synchronous driving is to MIPI modular converters 6.
MIPI modular converters 6 are used to spread its tail instruction and MIPI transmission synchronous control signals simultaneously to more according to multichannel MIPI
Each channel of channel MIPI synchronous output modules 7 sends command M IPI signals of spreading its tail, and the RGB data of each channel is distinguished
It is converted to and is sent to multichannel MIPI synchronous output modules 7 further according to MIPI transmission synchronous control signals after MIPI signals.
Multichannel MIPI synchronous output modules 7 are used to receive each channel of synchronous conditioning signal setting according to MIPI modules
Transmit electric parameter, and by multichannel MIPI modules reset signal and MIPI signals be sent to respectively with each channel attached mould
Group 8.
Implement the stream of realization multichannel MIPI synchronization transfer methods by above-mentioned realization multichannel MIPI synchronous transmission devices
Journey figure is as shown in Fig. 2, specific steps include：
The 16Lane modules 8 of each channel before powering on, are first connected to multichannel MIPI synchronous output modules by step 1)
On 7.Synchronous adjustment step：According to the length of the connecting line for the module 8 being connected on each channel or connector, transmission characteristic,
The parameters such as material are configured (its physical characteristic can be variant in actual use for each connecting line) in upper layer software (applications), and
Its output electric synchronization adjustment signal of setting MIPI to connecting line is passed through into MIPI Synchronization Control moulds again after the power is turned in the present invention
Block 1 issues multichannel MIPI synchronous output modules 7.
Multichannel MIPI synchronous output modules 7 then carry out output according to the control signal between each output channel and prolong
When, driving intensity, level, impedance matching, the electric parameters such as transmission attenuation are adjusted, it is therefore an objective to so as to be exported
MIPI signals be when being transferred to each module 8 completely simultaneously, the MIPI signals that module 8 is received on electrical quality completely
It is identical, so as to avoid the difference of the point screen effect caused by transmission line characteristics difference.
To light 16Lane screen inerrancies in a channel, therefore, to assure that multichannel MIPI synchronous output modules 7
In each channel it is identical on physical layer, when such as being realized in FPGA, the logical design and IO that need to ensure each channel export
In same BANK, same layout clock unit, identical work schedule, identical voltage, electric current, temperature change.
Step 2), after the completion of the configuration of multichannel MIPI synchronous output modules 7, upper layer software (applications) is to MIPI synchronization control modules
1 inner transmission upper strata input control signal, upper strata input control signal include the instruction of spreading its tail of each module 8 (because each module 8 is equal
For same type, therefore it is spread its tail, instruction is also identical), module reset worst sequential, LINK signal transmission parameters setting signal,
LINK signals input electric synchronization adjustment signal, image switching control；Start apparatus of the present invention work later.
Reset process：MIPI synchronization control modules 1 generate multichannel to MIPI module reset signals, to ensure each module
8 reliable resets, therefore the sequential of the reset signal is generated, and pass through multichannel by the worst sequential that the module that upper strata provides resets
MIPI synchronous output modules 7 issue each module 8 so that the reset for receiving identical signal quality that each module 8 can synchronize
Operation.
Step 3), MIPI synchronization control modules 1 postpone sufficiently long time progress in next step after reset signal has been generated
The reseting procedure of itself can be fully finished by being operable so that each module 8.Later, MIPI synchronization control modules 1 are by each module 8
Instruction of spreading its tail issue the MIPI modular converters 6 of each channel to generate accordingly containing the MIPI signals of instruction of spreading its tail, be sent into
7 corresponding channel of multichannel MIPI synchronous output modules is sent to module 8, for take into account module 8 terminate spread its tail instruction real-time and
Synchronism, MIPI synchronization control modules 1 transmit synchronous control signal by MIPI and control the MIPI modular converters 6 of each channel same
Walk the operations such as reading, generation, output, the delay each instructed.
Step 4), after instruction of spreading its tail all is sent to module, the delayed startup multichannel again of MIPI synchronization control modules 1
LINK transmission input modules 2 have ensured that modules can receive and perform the configuration for instruction of spreading its tail completely.In multichannel LINK
After transmitting the startup of input module 2, multichannel LINK transmission input modules 2 receive the serial video of 9 each channel of image signal source
The serial video picture signal of each channel is demodulated into four by picture signal according to LINK signal transmission parameters setting signal
The picture signal of LINK, the picture signal of each LINK includes a pair of of clock transfer line and four pairs in the picture signal of four LINK
Serial data line.Multichannel LINK transmits input module and adjusts signal in physical electrical further according to LINK signals input electric synchronization
The signal transmission timing synchronization of four LINK and identical (general to the vision signal of big resolution ratio and big data quantity is ensured in characteristic
It decomposes and transmits to reduce transmission rate, improve transmission reliability on multiple LINK).
Step 5), multichannel LINK transmit input module 2 and four LINK demodulated signals of each channel are sent into corresponding lead to
The input synchronization module 3 in road caches, to ensure that reliable synchronization handles the resource constraint it is also contemplated that in FPGA, each LINK difference
Half frame images data are cached, then is read the picture signal of four LINK in each channel simultaneously by RGB modular converters 4 and is turned respectively
The RGB submodule group video datas of four LINK are changed to, and are sent into multichannel RGB synchronism switchings module 5.
The picture signal of four LINK is converted to the RGB submodule group video counts for four LINK that 16Lane modules 8 need
According to have split screen arrange and two methods of point pixel arrangement.The picture signal of each LINK includes a pair of of clock transfer line and four pairs
Serial data line, wherein each pair of serial data line can be arranged according to split screen and a point pixel arrangement two ways is converted to 1/4 submodule
Group video data, 2/4 submodule group video data, 3/4 submodule group video data, 4/4 submodule group video data this four Lane
RGB submodule group video datas, i.e. four Link form the RGB submodule group video datas of 16Lane.When being arranged according to split screen, such as scheme
Shown in 3, the pixel in each Link is arranged in order according to four Lane as RGB submodule group video datas；According to dividing pixel arrangement
When, as shown in figure 4, first arrangement arranges the pixel in each Link subsequently into next Lane in a Lane, form RGB
Submodule group video data.
Step 6) is entered the RGB submodule group data of each channel of multichannel RGB synchronism switchings module 5 because transmitting
When difference on time, demodulation process time, logical sequence or physical circuit leads to multichannel RGB synchronism switching modules 5 that
This has delay, accumulates at any time, and delay is gradually increased, therefore need to cache half frame data again, and multichannel RGB, which is synchronized, later cuts
Mold changing block 5 is read, and simultaneously again according in RGB synchronous switching controls signal exchange to required channel, and switching composition n ×
The switching matrix of n one-to-one can not only export, but also can a pair of of multi output.After multichannel RGB synchronism switchings module 5, Ge Getong
Road output has been the RGB submodule group video datas of fully synchronized 16Lane.
Step 7), the RGB submodule group data of the 16Lane of each channel are respectively converted into MIPI by MIPI modular converters 6 to be believed
It is sent to multichannel MIPI synchronous output modules 7 simultaneously further according to MIPI transmission synchronous control signals after number.
The RGB submodule groups data of the 16Lane of input are carried out MIPI conversions to generate by the MIPI modular converters 6 of each channel
The MIPI signals of 16Lane, and it is same by MIPI in the operations such as the reading in conversion, conversion, timing control, transmission state change
The MIPI transmission synchronous control signals that step control module 1 is given carry out, the fully synchronized control of each operating procedure of each channel,
And in physical circuit realization, the MIPI modular converters 6 of each channel use same system on same structure or BANK
Clock work ensures that transfer process is fully synchronized.
Step 8), multichannel MIPI synchronous output modules 7 by the MIPI signals of 16Lane be sent to respectively with each channel
The module 8 of connection, the MIPI signals for the 16Lane that 8 simultaneous display of module is received.
Multichannel MIPI synchronous output modules 7 are as described above by the MIPI signal transmissions of 16Lane to module.MIPI simultaneously
For signal sheet as LP states and HS state alternate transports, both states are that (the former is electrical characteristic of different nature respectively
LVCOMS, the latter LVDS), therefore during the output of multichannel MIPI synchronous output modules 7, MIPI synchronization control modules 1
Still inform its current MIPI signal condition, multichannel MIPI synchronous output modules 7 then accordingly do different electrical adjustment, so as to really
Protect the MIPI signals that module 8 receives the 16Lane of complete synchronization.
It the above is only the preferred embodiment of the present invention, it is noted that those skilled in the art are come
It says, without departing from the principle of the present invention, can be devised by several improvement, these improvement also should be regarded as the guarantor of the present invention
Protect range.
The content that this specification is not described in detail belongs to the prior art well known to professional and technical personnel in the field.
Claims (10)
1. a kind of realization 16LANE module multichannel MIPI synchronization transfer methods, it is characterised in that：Include the following steps：
1) the serial video picture signal of each channel is received from image signal source (9), by the serial video of each channel
Picture signal is demodulated into the picture signal of four LINK, by the picture signal synchronous adjustment of four LINK and caches；
2) the RGB submodule group data of each channel are because on transmission time, demodulation process time, logical sequence or physical circuit
Difference, therefore cache half frame data again, synchronism switching reads the image letter of four LINK in each channel simultaneously again
Number and be respectively converted into the RGB submodule group video datas of four LINK；
3) the RGB submodule group video datas of four LINK of each channel are switched into corresponding output channel respectively；
4) MIPI that the RGB submodule group video datas of four LINK of each output channel are converted to four LINK believes
Number；
5) by the MIPI signals simultaneous transmission of four LINK of each output channel to being connect respectively with each output channel
Module (8), the number of output channel is identical with the number of module (8).
2. realization 16LANE module multichannel MIPI synchronization transfer methods according to claim 1, it is characterised in that：It is described
The picture signal of each LINK includes a pair of of clock transfer line and four pairs of serial data lines in the picture signal of four LINK.
3. realization 16LANE module multichannel MIPI synchronization transfer methods according to claim 1, it is characterised in that：It is described
Transmission passes through synchronous control while reading while in synchronous adjustment, the step 2) in step 1) in the step 5)
Signal control processed.
4. realization 16LANE module multichannel MIPI synchronization transfer methods according to claim 1, it is characterised in that：It is described
The video signal cached in step 1) is the half frame images signal in the video image of each channel.
5. realization 16LANE module multichannel MIPI synchronization transfer methods according to claim 1, it is characterised in that：It is described
Reset process is further included before step 1)：Multichannel MIPI modules are sent to the module (8) being connect respectively with each output channel
Reset signal, make with each channel attached module (8) synchronize carry out reset operation.
6. realization 16LANE module multichannel MIPI synchronization transfer methods according to claim 1, it is characterised in that：It is described
The number of channel is 1~12.
7. realization 16LANE module multichannel MIPI synchronization transfer methods according to claim 2, it is characterised in that：It is described
RGB submodule groups video data includes a pair of of clock transfer line and the serial data line of four pairs of split screen mode arrangements.
8. realization 16LANE module multichannel MIPI synchronization transfer methods according to claim 2, it is characterised in that：It is described
RGB submodule groups video data includes a pair of of clock transfer line and the serial data line of four pairs of points of pixel-wise arrangements.
9. realization 16LANE module multichannel MIPI synchronization transfer methods according to claim 5, it is characterised in that：It is described
Synchronous adjustment step is further included before reset process：Synchronous conditioning signal is received according to MIPI modules, each output channel is set
Electric parameter is transmitted, the MIPI modules receive output delay of the synchronous conditioning signal comprising each channel, driving intensity, level
Size, impedance matching, transmission attenuation electric parameter.
10. realization 16LANE module multichannel MIPI synchronization transfer methods according to claim 9, it is characterised in that：Institute
It states multichannel MIPI modules reset signal and includes the worst sequential of module reset, the module resets worst sequential for each channel
The reset timing maximum value of module (8).
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| CN105023549B (en) * | 2015-07-15 | 2017-05-31 | 武汉精测电子技术股份有限公司 | The MIPI figure signals generation device and method of resolution ratio self adaptation |
| CN110720206B (en) * | 2018-08-23 | 2021-06-04 | 深圳市大疆创新科技有限公司 | Data acquisition system, transmission conversion circuit and mobile platform |
| CN109640003B (en) * | 2018-12-27 | 2021-03-19 | 北京中科大洋科技发展股份有限公司 | Multi-path static switching method for ultra-high definition television broadcasting |
| CN110138761B (en) * | 2019-05-09 | 2021-10-15 | 豪威触控与显示科技(深圳)有限公司 | MIPI (Mobile industry processor interface) protocol-based inter-device communication method and equipment topological structure |
| CN111770520B (en) * | 2020-07-22 | 2023-02-28 | Oppo广东移动通信有限公司 | MIPI-based data transmission method, device, equipment and medium |
| CN114286133A (en) * | 2021-12-28 | 2022-04-05 | 京东方科技集团股份有限公司 | Image data processing method and device and display system |
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