CN103813107A - Multichannel high-definition video overlapping method based on FPGA (field programmable gata array) - Google Patents

Multichannel high-definition video overlapping method based on FPGA (field programmable gata array) Download PDF

Info

Publication number
CN103813107A
CN103813107A CN201410078394.2A CN201410078394A CN103813107A CN 103813107 A CN103813107 A CN 103813107A CN 201410078394 A CN201410078394 A CN 201410078394A CN 103813107 A CN103813107 A CN 103813107A
Authority
CN
China
Prior art keywords
video
fpga
road
data
module
Prior art date
Application number
CN201410078394.2A
Other languages
Chinese (zh)
Inventor
江荣
陈军
李旭勇
张德明
陈和平
Original Assignee
湖南兴天电子科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 湖南兴天电子科技有限公司 filed Critical 湖南兴天电子科技有限公司
Priority to CN201410078394.2A priority Critical patent/CN103813107A/en
Publication of CN103813107A publication Critical patent/CN103813107A/en

Links

Abstract

The invention relates to the video overlapping technology, in particular to a multichannel high-definition video overlapping method based on a FPGA (field programmable gata array). The multichannel high-definition video overlapping method based on the FPGA includes that a video source is converted to a digital signal through an A/D (analog to digital) chip and then enters into the FPGA, the FPGA collects effective pixels, clock domain conversion processing is performed on each channel of the video through an FIFO, all the video is unified to an inner clock of the FPGA, a video zooming module is built inside the FPGA and caches a frame of data in each channel of the video which is zoomed into a DDR3, a traveling field synchronization module of a VESA (video electronics standards association) standard is built inside the FPGA, and simultaneously data of each channel of the video is red from the DDR3, frame synchronization is performed on the data, an alhpa mixture overlapping module is built inside the FPGA and used overlap the video, and the video after being overlapped is output through a D/A (digital to analog) chip. The multichannel high-definition video overlapping method based on the FPGA facilitates implementation of hardware and software, and low in cost, strong in flexibility, small in size of a system, and low in power consumption.

Description

A kind of based on FPGA multi-path high-definition video superimpose method

Technical field

The present invention relates to video superimpose technology, is based on FPGA multi-path high-definition video superimpose method specifically.

Background technology

Video and graph compound technology can superpose multiple paths of video images signal and output on a display and show.In multiple paths of video images signal, a road is as superimposed signal (being background), remaining as superposed signal (being prospect), can incorporate prospect video image and show in same terminal in background video image.This technology has a wide range of applications in fields such as television system, video monitoring system, advertisement recreational, traffic administrations.Domestic production video superimpose device mainly adopts video matrix, image splitter to realize at present, mostly adopts special video superimpose chip design to form, and its flexibility is poor, and cost is high.

For the design of multi-path high-definition video superimpose, the method adopting mostly at present is and uses multiple dsp chips, or uses the mode of FPGA+DSP.But, adopt multiple dsp chips to carry out multi-path high-definition video superimpose, because the data volume of HD video is very large, requirement of real-time is high, also just very high to the performance requirement of DSP, like this, its cost can improve greatly, and the complexity of system also can improve; The words that adopt FPGA+DSP to process, conventionally DSP is as master controller, video is carried out to overlap-add procedure computing, FPGA is used for carrying out the frequency reducing of video data acquiring and vision signal, this method can increase equipment cost, and can increase the time loss that between Main Processor Unit, collaborative work produces, increase the complexity of circuit.

Summary of the invention

For above-mentioned technical problem, the invention provides a kind of simple in structure, cost is low be easy to that hardware and software realizes based on FPGA multi-path high-definition video superimpose method.

The present invention solves the problems of the technologies described above adopted technical scheme: a kind of based on FPGA multi-path high-definition video superimpose method, it comprises the following steps:

(1) multi-path high-definition video source through A D chip be converted to digital signal and enter FPGA, FPGA is according to the valid pixel of the each road of VESA standard acquisition video, each road video carries out clock zone conversion process through a FIFO respectively, and unified under FPGA internal clocking;

(2) CPU is by the parameter setting of pci bus control FPGA inside;

(3), in FPGA internal build video scaling module, video scaling module is controlled video scaling parameter Dui Ge road, Ge road video according to CPU and is carried out convergent-divergent processing;

(4) respectively Ba Mei road through the data volume of video cache one frame of convergent-divergent processing to DDR3;

(5) in the row field synchronization module of FPGA internal build VESA standard, and the row field signal producing according to this row field synchronization module reads each road video data from DDR3, carries out frame synchronization process;

(6) at FPGA internal build alhpa mixing laminating module, video is carried out to overlap-add procedure;

(7) video that carries out overlap-add procedure through D A chip carry out video output.

As preferably, in step (3), described video scaling module adopts sampling of data method to carry out convergent-divergent processing to original video, and data after treatment are entered in FIFO, and translation data output format.

As preferably, in step (5), described row field synchronization module is selected according to CPUDui Mei road video the location parameter value in output video and background video after stack, reads video data from DDR3.

As preferably, in step (6), video superimpose formula is I=I1 α+I2 (1-α), wherein I is the pixel value of the video image pixel of output after stack, and I1 is the pixel value of background video image pixel, and I2 is the pixel value of prospect video image pixel, α ∈ [0,1].

As can be known from the above technical solutions, the present invention sends instruction by CPU, can adjust the ratio of prospect video in background, the position of adjusting prospect in background image, can select any road video as a setting, free switching prospect and background video, can realize 2-4 road video and superpose, output display; In addition can also be extended to HD video stacks more than 4 tunnels, output multi-channel overlay video, and the stacked system of every road output video can be different; This method is easy to hardware and software and realizes, and with low cost, flexibility is strong, and system bulk is little and low in energy consumption.

Accompanying drawing explanation

Fig. 1 is the schematic diagram of optimal way of the present invention.

Embodiment

Introduce in detail method of the present invention below in conjunction with Fig. 1, it comprises the following steps:

(1) multi-path high-definition video source through A D chip be converted to digital signal and enter FPGA, FPGA is according to VESA standard, utilize row field sync signal, gather the valid pixel of each road video, then each road video is respectively through a FIFO, utilize clock zone modular converter to carry out clock zone conversion process, and unified under FPGA internal clocking, for next step, to write DDR3 ready.

(2) CPU is by the parameter setting of the total line traffic control FPGA of pci interface inside, and CPU sends order by pci bus to FPGA, and FPGA realizes multi-path high-definition video data acquiring, convergent-divergent and overlaying function according to instruction.

(3), in FPGA internal build video scaling module, video scaling module is controlled video scaling parameter Dui Ge road, Ge road video according to CPU and is carried out convergent-divergent processing; Video scaling module adopts sampling of data method to carry out convergent-divergent processing to original video, and data after treatment are entered in FIFO, and translation data output format, thereby meets the read-write sequence logic of DDR3.

(4) in the internal memory that Ba Mei road distributes to DDR3 by the data volume of DDR3 controller cache one frame through the video of convergent-divergent processing respectively.

(5) in the row field synchronization module of FPGA internal build VESA standard, and the row field signal producing according to this row field synchronization module reads each road video data from DDR3, carries out frame synchronization process; Row field synchronization module, according to CPUDui Mei road video the location parameter value in output video and background video selection after stack, produces corresponding effective video data enable signal, reads video data from DDR3, realizes frame synchronization process.

(6) in FPGA internal build alhpa video superimpose module, video is carried out to overlap-add procedure; Video superimpose formula is I=I1 α+I2 (1-α), and wherein I is the pixel value of the video image pixel of output after stack, and I1 is the pixel value of background video image pixel, and I2 is the pixel value of prospect video image pixel, α ∈ [0,1]; Can carry out the additive fusion of video image by controlling the value of α; While realization, need first be converted into integer form in FPGA, then realize by the processing of bit wide cut position.

(7) video that carries out overlap-add procedure through D A chip carry out video and show output.

Operating process of the present invention is as follows: after system powers on, FPGA receives the data of multi-path high-definition video simultaneously, and according to the zooming parameter settings of CPUDui Mei road video, FPGA carries out convergent-divergent processing to video; Then buffer memory Yi Zhengge road video data is to the DDR3 internal memory distributing, the inner row field synchronization module that produces of FPGA, according to CPUDui Mei road video the location parameter value in output video and background video selection after stack, from DDR3, read video data, carry out video superimpose processing, finally carry out video and show output.The present invention sends instruction by CPU, can adjust the ratio of prospect video in background, the position of adjusting prospect in background image, can select any road video as a setting, can freely switch prospect and background video, can realize 2-4 road video and superpose, output display; In addition can also be extended to HD video stacks more than 4 tunnels, output multi-channel overlay video, and the stacked system of every road output video can be different.

Above-mentioned execution mode is used for illustrative purposes only, and be not limitation of the present invention, the those of ordinary skill in relevant technologies field, without departing from the spirit and scope of the present invention, can also make various variations and modification, therefore all technical schemes that are equal to also should belong to category of the present invention.

Claims (4)

1. based on a FPGA multi-path high-definition video superimpose method, it comprises the following steps:
(1) multi-path high-definition video source through A D chip be converted to digital signal and enter FPGA, FPGA is according to the valid pixel of the each road of VESA standard acquisition video, each road video carries out clock zone conversion process through a FIFO respectively, and unified under FPGA internal clocking;
(2) CPU is by the parameter setting of pci bus control FPGA inside;
(3), in FPGA internal build video scaling module, video scaling module is controlled video scaling parameter Dui Ge road, Ge road video according to CPU and is carried out convergent-divergent processing;
(4) respectively Ba Mei road through the data volume of video cache one frame of convergent-divergent processing to DDR3;
(5) in the row field synchronization module of FPGA internal build VESA standard, and the row field signal producing according to this row field synchronization module reads each road video data from DDR3, carries out frame synchronization process;
(6) at FPGA internal build alhpa mixing laminating module, video is carried out to overlap-add procedure;
(7) video that carries out overlap-add procedure through D A chip carry out video output.
2. method according to claim 1, is characterized in that: in step (3), described video scaling module adopts sampling of data method to carry out convergent-divergent processing to original video, and data after treatment are entered in FIFO, and translation data output format.
3. method according to claim 1, is characterized in that: in step (5), described row field synchronization module, according to CPUDui Mei road video the location parameter value in output video and background video selection after stack, is read video data from DDR3.
4. method according to claim 1, it is characterized in that: in step (6), video superimpose formula is I=I1 α+I2 (1-α), wherein I is the pixel value of the video image pixel of output after stack, I1 is the pixel value of background video image pixel, I2 is the pixel value of prospect video image pixel, α ∈ [0,1].
CN201410078394.2A 2014-03-05 2014-03-05 Multichannel high-definition video overlapping method based on FPGA (field programmable gata array) CN103813107A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201410078394.2A CN103813107A (en) 2014-03-05 2014-03-05 Multichannel high-definition video overlapping method based on FPGA (field programmable gata array)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410078394.2A CN103813107A (en) 2014-03-05 2014-03-05 Multichannel high-definition video overlapping method based on FPGA (field programmable gata array)

Publications (1)

Publication Number Publication Date
CN103813107A true CN103813107A (en) 2014-05-21

Family

ID=50709261

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410078394.2A CN103813107A (en) 2014-03-05 2014-03-05 Multichannel high-definition video overlapping method based on FPGA (field programmable gata array)

Country Status (1)

Country Link
CN (1) CN103813107A (en)

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104482885A (en) * 2014-12-04 2015-04-01 哈尔滨工业大学 Four-reading-head incremental circular grating coupler
CN104602029A (en) * 2014-08-27 2015-05-06 腾讯科技(北京)有限公司 Online video file generating method and device
CN104601910A (en) * 2015-01-26 2015-05-06 广州海昇计算机科技有限公司 Four-way full-high-definition video processing circuit based on field programmable gate array (FPGA)
CN104660918A (en) * 2015-03-11 2015-05-27 南京航空航天大学 Airborne system for mixing and displaying videos in real time
CN104836965A (en) * 2015-06-16 2015-08-12 深圳市邦彦信息技术有限公司 FPGA-based video synchronous switching system and method
CN104900204A (en) * 2015-06-12 2015-09-09 武汉精测电子技术股份有限公司 Logic frame overlapping device and method based on FPGA
CN105282597A (en) * 2015-10-17 2016-01-27 浙江宇视科技有限公司 Video stream scaling device and method
CN105430296A (en) * 2015-11-26 2016-03-23 深圳市捷视飞通科技股份有限公司 Solving method for multi-picture division cracked screen display of high-definition video
CN105554416A (en) * 2015-12-24 2016-05-04 深圳市捷视飞通科技股份有限公司 FPGA (Field Programmable Gate Array)-based high-definition video fade-in and fade-out processing system and method
CN106941617A (en) * 2017-04-26 2017-07-11 西安诺瓦电子科技有限公司 Video process apparatus and multi-window picture display methods
CN107019487A (en) * 2016-02-02 2017-08-08 深圳市巨烽显示科技有限公司 Medical imaging display methods and device
CN107360388A (en) * 2017-09-05 2017-11-17 成都德芯数字科技股份有限公司 Video format processing method and processing device
CN108055478A (en) * 2017-12-18 2018-05-18 天津津航计算技术研究所 A kind of multi-channel video superposed transmission method based on FC-AV agreements
CN108156396A (en) * 2016-12-06 2018-06-12 矽创电子股份有限公司 Display system and its video signal data display methods
CN109151341A (en) * 2018-09-27 2019-01-04 中国船舶重工集团公司第七0九研究所 A kind of embedded platform multi-source HD video fusion realization system and method

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
张多利: "一种通用的视频/图像混合器设计研究", 《电子测量与仪器学报》 *
朱艳亮: "实时视频缩放算法研究及FPGA实现", 《中国优秀硕士学位论文电子期刊网》 *
李翠娟: "基于FPGA的视频转换模块设计与实现", 《航空计算技术》 *

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104602029A (en) * 2014-08-27 2015-05-06 腾讯科技(北京)有限公司 Online video file generating method and device
CN104482885B (en) * 2014-12-04 2017-01-25 哈尔滨工业大学 Four-reading-head incremental circular grating coupler
CN104482885A (en) * 2014-12-04 2015-04-01 哈尔滨工业大学 Four-reading-head incremental circular grating coupler
CN104601910A (en) * 2015-01-26 2015-05-06 广州海昇计算机科技有限公司 Four-way full-high-definition video processing circuit based on field programmable gate array (FPGA)
CN104601910B (en) * 2015-01-26 2018-07-24 广州海昇计算机科技有限公司 A kind of full HD video processing circuits in four tunnels based on FPGA
CN104660918A (en) * 2015-03-11 2015-05-27 南京航空航天大学 Airborne system for mixing and displaying videos in real time
CN104660918B (en) * 2015-03-11 2018-09-21 南京航空航天大学 A kind of real-time mixed display system of Airborne Video System
CN104900204A (en) * 2015-06-12 2015-09-09 武汉精测电子技术股份有限公司 Logic frame overlapping device and method based on FPGA
CN104900204B (en) * 2015-06-12 2017-05-17 武汉精测电子技术股份有限公司 Logic frame overlapping device and method based on FPGA
CN104836965B (en) * 2015-06-16 2018-02-23 邦彦技术股份有限公司 A kind of audio video synchronization switching system and method based on FPGA
WO2016201892A1 (en) * 2015-06-16 2016-12-22 邦彦技术股份有限公司 Fpga-based synchronous video switching system and method
CN104836965A (en) * 2015-06-16 2015-08-12 深圳市邦彦信息技术有限公司 FPGA-based video synchronous switching system and method
CN105282597B (en) * 2015-10-17 2018-12-07 浙江宇视科技有限公司 A kind of video flowing device for zooming and method
CN105282597A (en) * 2015-10-17 2016-01-27 浙江宇视科技有限公司 Video stream scaling device and method
CN105430296A (en) * 2015-11-26 2016-03-23 深圳市捷视飞通科技股份有限公司 Solving method for multi-picture division cracked screen display of high-definition video
CN105554416A (en) * 2015-12-24 2016-05-04 深圳市捷视飞通科技股份有限公司 FPGA (Field Programmable Gate Array)-based high-definition video fade-in and fade-out processing system and method
CN107019487A (en) * 2016-02-02 2017-08-08 深圳市巨烽显示科技有限公司 Medical imaging display methods and device
CN108156396A (en) * 2016-12-06 2018-06-12 矽创电子股份有限公司 Display system and its video signal data display methods
CN106941617B (en) * 2017-04-26 2020-04-21 西安诺瓦星云科技股份有限公司 Video processing apparatus and multi-window screen display method
CN106941617A (en) * 2017-04-26 2017-07-11 西安诺瓦电子科技有限公司 Video process apparatus and multi-window picture display methods
CN107360388A (en) * 2017-09-05 2017-11-17 成都德芯数字科技股份有限公司 Video format processing method and processing device
CN108055478A (en) * 2017-12-18 2018-05-18 天津津航计算技术研究所 A kind of multi-channel video superposed transmission method based on FC-AV agreements
CN109151341A (en) * 2018-09-27 2019-01-04 中国船舶重工集团公司第七0九研究所 A kind of embedded platform multi-source HD video fusion realization system and method

Similar Documents

Publication Publication Date Title
US6353460B1 (en) Television receiver, video signal processing device, image processing device and image processing method
JP6023066B2 (en) Combining video data streams of different dimensions for simultaneous display
CN100514439C (en) High distinguishability split joint television set curtain wall and consist method thereof
US20110050850A1 (en) Video combining device, video display apparatus, and video combining method
EP2274739B1 (en) Video multiviewer system with serial digital interface and related methods
CN201608820U (en) Audio/video control system for large-scale LED display screen
US10089947B2 (en) Source driver, driving circuit and display apparatus
JP2008506295A (en) Method and system for displaying a series of image frames
US9135675B2 (en) Multiple graphics processing unit display synchronization system and method
CN103347163A (en) Ultra high definition video image processing and transmitting system and method thereof
JP5654134B2 (en) Parallel image processing using multiple processors
CN103021378B (en) A kind of device for multi-screen mosaic display and method
CN107249101B (en) High-resolution image acquisition and processing device
CN103269416A (en) Device and method for achieving video image tiled display by adoption of parallel processing mode
TWI681377B (en) Display driver integrated circuit, mobile device and driver apparatus
CN101516015B (en) Multi-path video data acquiring, processing and transmitting method
CN106415479B (en) Multiple display pipelines drive divided display
US10049642B2 (en) Sending frames using adjustable vertical blanking intervals
CN204836434U (en) Audio frequency and video playback devices
CN105100644A (en) Seamless switching method for video source
CN101977305A (en) Video processing method, device and system
TW200948046A (en) A video signal controlling system and method
CN101764981B (en) High-resolution video image controller for embedded LED display screen
CN103544130B (en) A kind of windows display equipment and display packing
CN103021329B (en) A kind of all-color LED panel system and brightness adjusting method thereof

Legal Events

Date Code Title Description
PB01 Publication
C06 Publication
SE01 Entry into force of request for substantive examination
C10 Entry into substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20140521

RJ01 Rejection of invention patent application after publication