WO2016201892A1

WO2016201892A1 - Fpga-based synchronous video switching system and method

Info

Publication number: WO2016201892A1
Application number: PCT/CN2015/095519
Authority: WO
Inventors: 杨磊
Original assignee: 邦彦技术股份有限公司
Priority date: 2015-06-16
Filing date: 2015-11-25
Publication date: 2016-12-22
Also published as: CN104836965B; CN104836965A

Abstract

The present invention provides an FPGA-based synchronous video switching system and method. The system comprises: an AD conversion module; a DA conversion module; a resolution detection module, configured to sample a digital video signal, and output a relevant sampling parameter; a central processing unit, configured to adjust output of the AD conversion module, and receive and transmit an external switching parameter; a CPU interface module; a first signal synchronization module, configured to perform multi-stage synchronization on multiple digital video signals; a synchronous logic switching module, configured to switch and output, according to the switching parameter, the multiple synchronized digital video signals; and a clock processing module, configured to perform frequency multiplication on an input clock signal, and output a high-speed detection clock signal to the resolution detection module. The present invention is capable of arbitrarily switching multi-video output, supporting switching of multiple resolution videos while guaranteeing the image quality, and solving the problems of reduction of the image quality, low integration level and inflexibility of a traditional switching mode. The present invention can be widely applied to the field of signal processing.

Description

FPGA-based video synchronous switching system and method

Technical field

The present invention relates to the field of signal processing, and more particularly to an FPGA-based video synchronization switching system and method.

Background technique

With the rapid expansion of the video field, more and more video formats, more and more resolution, users have higher and higher requirements for video clarity, and the field of video switching needs is more and more extensive.

Many video switching is currently based on analog devices, the implementation is very inflexible, and the integration is not high. The switching mode of the combination logic will cause the video channel delay to be too large, and can not effectively support the high-resolution and high-data rate video format, thereby reducing the image quality, especially for high-definition video, and the quality of the switched video is greatly reduced. The professional switching chip is not flexible enough to adapt to the video switching mode of a specific mode, and cannot support subsequent upgrades.

In view of this, it is an object of the present invention to provide a new technical solution to solve the existing technical problems.

Summary of the invention

In order to overcome at least one of the above-mentioned defects or shortcomings in the prior art, the present invention provides an FPGA-based video synchronous switching system and method, which does not require an external video signal buffer, and only requires a small internal FIFO unit to perform signal isolation and storage. Multi-channel video can be switched synchronously at any time, and supports switching of multiple high-resolution videos at the same time, with high integration and flexible mode.

In order to achieve the above beneficial effects, the technical solution of the present invention is as follows:

An FPGA-based video synchronous switching system, comprising an AD conversion module, which converts an input analog video signal into a digital video signal; a resolution detection module that samples a digital video signal and outputs relevant sampling parameters; a central processing unit, The AD conversion module adjusts the corresponding digital video signal according to the relevant sampling parameter, and receives and transmits the external switching parameter; the CPU interface module is used for connecting the central processor and the FPGA internal storage unit; the first signal synchronization module is more The circuit digital video signal performs multi-level synchronization; the synchronous logic switching module converts and outputs the synchronized multi-channel digital video signals according to the switching parameter; the DA conversion module converts the switched digital video signal into an analog video signal; A processing module that multiplies the input clock signal and outputs a high speed detection clock signal to the resolution detection module.

Further, the synchronous logic switching module includes a clock switching module and a video switching module; the clock switching module switches the pixel clocks of the synchronized multiple digital video signals to a video signal switching module and a DA conversion module, and according to The switching parameter outputs a multi-way reset signal to the video signal switching module; the video switching module buffers the synchronized multi-channel digital video signal, and selects and outputs the digital video signal to the DA conversion module according to the switching parameter.

Further, the clock switching module includes a reset signal module, a switching selection module, a global buffer module, and an ODDR module; the reset signal module generates a multi-way reset signal output to the video signal switching module according to the switching parameter; and the switching selection module pairs pixels The clock is switched to select the output to the global buffer module; the global buffer module outputs the pixel clock signal to the global clock network and the ODDR module; the ODDR module outputs the pixel clock to the DA Conversion module.

Further, the video switching module includes a video signal storage module, a synchronization selection module, and a second signal synchronization module; the video signal storage module buffers the synchronized multiple digital video signals, and correspondingly according to the multiple reset signals The storage module performs resetting; the synchronization selection module selects data in the corresponding buffer memory according to the switching parameter for output; and the second signal synchronization module performs multi-stage synchronization on the selected output data and outputs the data to the DA. Conversion module.

Further, the buffer storage uses an FPGA internal FIFO buffer isolation memory unit.

An FPGA-based video synchronization switching method includes the following steps:

S01. Converting the input analog video signal into a digital video signal; multiplying the input clock signal to obtain a high-speed detection clock signal;

S02. The high-speed detection clock signal is used to sample the digital video signal, obtain relevant sampling parameters, and simultaneously perform multi-level synchronization on the multi-channel digital video signals;

S03. Adjusting and outputting a corresponding digital video signal according to the relevant sampling parameter, and receiving an external switching parameter;

S04. switching the synchronized multi-channel digital video signals according to the switching parameters;

S05. Convert the digital video signal of the switched output to an analog video signal.

Further, before step S04, step A4 is further included. Obtaining a pixel clock in the synchronized multi-channel digital video signal, and acquiring a multi-channel reset signal according to the switching parameter; B. buffering the synchronized multi-channel digital video signal.

Specifically, the step S04 includes:

S401. Reset the corresponding storage address according to the multiple reset signal;

S402. Select data of a corresponding storage address according to the switching parameter.

S403. Perform multi-level synchronization on the selected data and output.

Further, the step B buffer is stored as a FIFO buffer isolation storage.

The invention has the beneficial effects that the invention realizes arbitrary synchronous switching of multiple video sources to multiple video outputs based on the manner of FPGA synchronous sequential logic, without compression and transformation in the process of internal video image transmission, the circuit is simple, and the integration degree is high. It does not require external memory, supports switching of multiple resolution videos while ensuring image quality, and solves the image quality degradation caused by the excessive extension of image lines caused by FPGA combination logic switching mode, and the analog device switching mode. The disadvantages of low integration and inflexibility of the device.

Drawing

1 is a schematic block diagram of an FPGA-based video synchronous switching system according to the present invention;

2 is a more detailed schematic diagram of an FPGA-based video synchronization switching system according to the present invention;

3 is a schematic diagram of a clock switching module;

4 is a schematic diagram of a video switching module;

5 is a flow chart of steps of a method for video synchronization switching based on FPGA according to the present invention;

Figure 6 is a flow chart of step S04;

Figure 7 is a schematic diagram of an embodiment of the present invention;

Figure 8 is a schematic block diagram of another embodiment of the present invention;

FIG. 9 is a schematic block diagram of a synchronous logic switching module for one video output of another embodiment.

detailed description

The technical solutions of the present invention are further described below with reference to the accompanying drawings and specific embodiments, but the present invention is not limited to the specific embodiments.

It will be apparent to those skilled in the art that certain known structures and their description may be omitted.

FIG. 1 is a schematic block diagram of an FPGA-based video synchronous switching system, including an AD conversion module, which converts an input analog video signal into a digital video signal; and a resolution detection module that performs digital video signals Sampling, outputting related sampling parameters; the central processing unit adjusts the corresponding digital video signal output by the AD conversion module according to the relevant sampling parameters, and receives and transmits external switching parameters; the CPU interface module is used to connect the central processing unit and the FPGA internal storage. a first signal synchronization module that performs multi-stage synchronization on the multi-channel digital video signal; a synchronous logic switching module that switches the synchronized multi-channel digital video signals according to the switching parameters; the DA conversion module switches the output The digital video signal is converted into an analog video signal; the clock processing module multiplies the input clock signal and outputs a high speed detection clock signal to the resolution detecting module.

Further, as a preferred embodiment of the present invention, as shown in FIG. 2, a more specific schematic diagram of an FPGA-based video synchronization switching system, the synchronous logic switching module includes a clock switching module and a video switching module; The switching module switches the pixel clock in the synchronized multi-channel digital video signal to the video signal switching module and the DA conversion module, and generates a multi-way reset signal to the video signal switching module according to the switching parameter; the video switching module will synchronize The subsequent multi-channel digital video signal is buffer-stored, and the output digital video signal is selected to the DA conversion module according to the switching parameter.

Further, as a preferred embodiment, as shown in the schematic diagram of the clock switching module shown in FIG. 3, the clock switching module includes a reset signal module, a switching selection module, a global buffer module, and an ODDR module; and the reset signal module is configured according to a switching parameter. Generating a multiple reset signal to the video signal switching module; the switching selection module switches the pixel clock to select the output to the global buffer module; the global buffer module outputs the pixel clock signal to the global clock network and the ODDR module; ODDR module output pixel clock to DA Conversion module.

As a preferred implementation manner, as shown in the schematic diagram of the video switching module shown in FIG. 4, the video switching module includes a video signal storage module, a synchronization selection module, and a second signal synchronization module; the video signal storage module will be synchronized. The multi-channel digital video signal is buffer-stored, and resets the corresponding storage module according to the multi-way reset signal; the synchronization selection module selects data in the corresponding buffer memory according to the switching parameter for output; the second signal synchronization module Multi-level synchronization of selected output data and output to DA Conversion module.

Further, as a preferred implementation manner, the buffer storage of the present invention uses an FPGA internal FIFO buffer isolation storage unit.

FIG. 5 is a flow chart showing the steps of an FPGA-based video synchronization switching method according to the present invention, including the following steps:

Further, as a preferred implementation manner, the step S04 further includes the step A. Obtaining a pixel clock in the synchronized multi-channel digital video signal, and acquiring a multi-channel reset signal according to the switching parameter; B. buffering the synchronized multi-channel digital video signal.

Specifically, the flowchart of step S04 shown in FIG. 6 includes:

S402. Select data of a corresponding storage address according to the switching parameter;

S403. Perform multi-level synchronization on the selected data and output.

Further as a preferred implementation manner, the step B buffer is stored as a FIFO buffer isolation storage.

Example 1

As shown in the schematic diagram of an embodiment of the present invention, the multi-channel analog video signal is converted into a multi-channel digital video signal by the AD conversion module, and the resolution detection module uses the high-speed detection clock generated by the clock processing module to the AD conversion module. The output multi-channel digital video signal is sampled, and the collected related parameters are submitted to the central processor through the CPU interface module, and the central processor performs relevant settings on the AD conversion module according to the corresponding parameters, and receives and transmits the external switching finger parameters. .

The first signal synchronization module performs multi-stage synchronization on multiple digital video signals by inserting multi-level registers in the path of signal transmission, thereby reducing line delay between registers, improving the operating frequency of the system, and meeting the requirements of input timing constraints. The switching selection module in the clock switching module switches and selects the pixel clock in the multi-level synchronized digital video signal according to the switching parameter output by the central processing unit, and introduces a pixel clock of the switching selection output into the logic through the global buffer module. The global clock network, which reduces the routing delay of the clock inside the logic. The pixel clock is output to the DA conversion module through the ODDR module, which reduces the output delay of the pixel clock. The reset signal module in the clock switching module generates a multi-way reset signal to the video signal storage module according to the switching parameter, and the video signal storage module resets the corresponding storage module.

Before implementing the video switching function, the video signal storage module performs FIFO buffer storage on the line synchronization signal, the field synchronization signal and the data signal of each video, and separates the input video signal from the output video signal to perform processing separately. The input timing constraint and output timing constraints of the video signal increase the operating frequency of the video interface. When switching the output, the synchronization selection module selects the data in the corresponding buffer memory in the video signal memory according to the switching parameter for output, and the clock output by the global buffer module is used as the system clock, and the second signal synchronization module passes the signal transmission. Multi-level registers are inserted into the path to synchronize multi-channel digital video signals, reduce line delay between registers, improve the operating frequency of the system, meet the requirements of output timing constraints, and output data signals to the DA conversion module.

The DA conversion module converts the input digital video signal and the pixel clock output from the ODDR module into an analog video signal output.

The invention is based on the FIFO buffer isolation of the line synchronization signal, the field synchronization signal and the data signal of the multi-channel video to realize the synchronization of the front and rear ends of the signal, and increases the working frequency of the system by adding appropriate timing constraints to the video input and output, and supports the HD video. . The FPGA realizes any synchronous switching output of multiple input video, the method is simple and easy to implement, has no influence on video quality, and is easy to expand, and occupies less logic resources.

Example 2

This embodiment is based on any synchronous switching output of 5 VGA video inputs to 4 VGA videos.

As shown in the block diagram of another embodiment shown in FIG. 8, five VGA video signals are input and converted into digital video information of the RGB888 color mode by the AD decoding chip. Since the VGA decoder chip cannot determine the effective area of the video output, it is necessary to set the effective area of the output through the central processing unit. If the central processor does not know the resolution, the effective area of the video output may be deviated. As a result, when the display is output, it will cause black edges of the video. The clock processing module multiplies the externally input clock to generate the high-speed detection clock required by the VGA resolution detection module. The clock logic block also eliminates duty cycle distortion of the external input clock and reduces clock jitter.

The VGA resolution detection module samples the relevant video signal output by the VGA decoder chip through the high-speed clock, and submits the collected related parameters to the central processor, and the central processor sets the VGA decoder chip according to the corresponding parameters, thereby outputting A valid video area that eliminates black edges. The switching parameters of the video can be set by the central processing unit.

The CPU interface module is based on the BUS bus read and write timing of the central processing unit, and realizes the interface of the central processing unit to operate the internal storage unit of the FPGA through the BUS bus. The CPU interface module can be modified according to the interface requirements of different CPUs.

Due to the large scale of the logic chip, the internal line delay is also relatively large. The first signal synchronization module performs multi-level synchronization on each input VGA digital video signal, and inserts a multi-level register in the path of the signal transmission, thereby reducing the register. The line delay between the lines increases the operating frequency of the system and meets the input timing constraints.

FIG. 9 is a schematic block diagram of a synchronous logic switching module for video output of another embodiment, and the synchronous logic switching module mainly includes a clock switching function and a video switching function. The clock switching function switches the pixel clock of the input 5 video channels, and introduces one clock of the switching selection output into the global clock network of the logic through the global buffer module, thereby reducing the wiring delay of the clock inside the logic. The pixel clock is output through the logic internal ODDR module, which reduces the output delay of the pixel clock. The clock switching module simultaneously generates 5 reset signals to the video signal storage module, and resets the corresponding storage modules according to the switching parameters.

The video signal storage module performs FIFO buffer storage on the line synchronization signal, the field synchronization signal and the data signal of each video, and separates the input video signal from the output video signal to separately process, thereby implementing input timing constraints of the front and rear end video signals. And output timing constraints to improve the operating frequency of the video interface. When switching the output, the data in the corresponding buffer memory is selected according to the switching parameter for output, and the clock outputted by the global buffer module is used as the system clock, and the data signal of the selected output is synchronized and output to the DA conversion chip, thereby reducing logic. The delay between internal sync registers.

The DA conversion chip converts the selected output data signal into an analog video signal output.

The invention realizes any synchronous switching of multiple video sources to multiple video outputs based on the manner of FPGA synchronous timing logic, without compression and transformation during internal video image transmission, and supports multiple resolutions while ensuring image quality. The switching of the video solves the image quality degradation caused by the excessive extension of the image line caused by the combination mode switching mode of the FPGA, and the disadvantages of low integration and inflexibility caused by the analog device switching mode.

The positional relationship described in the drawings is for illustrative purposes only and is not to be construed as limiting the invention.

It is apparent that the above-described embodiments of the present invention are merely illustrative of the present invention and are not intended to limit the embodiments of the present invention. Other variations or modifications of the various forms may be made by those skilled in the art in light of the above description. There is no need and no way to exhaust all of the implementations. Any modifications, equivalent substitutions and improvements made within the spirit and scope of the invention are intended to be included within the scope of the appended claims.

Claims

An FPGA-based video synchronization switching system, comprising:

An AD conversion module that converts the input analog video signal into a digital video signal;

a resolution detection module that samples a digital video signal and outputs relevant sampling parameters;

a central processing unit that adjusts an AD conversion module to output a corresponding digital video signal according to relevant sampling parameters, and receives and transmits an external switching parameter;

a CPU interface module for connecting a central processing unit and an FPGA internal storage unit;

a first signal synchronization module that performs multi-level synchronization on multiple digital video signals;

a synchronous logic switching module, which switches and outputs the synchronized multiple digital video signals according to the switching parameters;

a DA conversion module that converts the switched digital video signal into an analog video signal;

A clock processing module that multiplies the input clock signal and outputs a high speed detection clock signal to the resolution detection module.
The FPGA-based video synchronization switching system according to claim 1, wherein the synchronization logic switching module comprises a clock switching module and a video switching module;

The clock switching module switches the pixel clock in the synchronized multi-channel digital video signal to the video signal switching module and the DA conversion module, and outputs a multi-channel reset signal to the video signal switching module according to the switching parameter;

The video switching module buffers the synchronized multi-channel digital video signals, and selects and outputs the digital video signals to the DA conversion module according to the switching parameters.
The FPGA-based video synchronization switching system according to claim 2, wherein the clock switching module comprises a reset signal module, a switch selection module, a global buffer module, and an ODDR module;

The reset signal module generates a multi-way reset signal output to the video signal switching module according to the switching parameter;

The switching selection module switches and selects a pixel clock to output to the global buffer module;

The global buffer module outputs a pixel clock signal to the global clock network and the ODDR module;

The ODDR module outputs a pixel clock to the DA conversion module.
The FPGA-based video synchronization switching system according to claim 3, wherein the video switching module comprises a video signal storage module, a synchronization selection module, and a second signal synchronization module;

The video signal storage module buffers the synchronized multiple digital video signals, and resets the corresponding storage modules according to the multiple reset signals;

The synchronization selection module selects data in the corresponding buffer memory according to the switching parameter for output;

The second signal synchronization module performs multi-stage synchronization on the selected output data and outputs the data to the DA conversion module.
The FPGA-based video synchronization switching system according to claim 4, wherein the buffer storage uses an FPGA internal FIFO buffer isolation storage unit.
An FPGA-based video synchronization switching method, comprising the following steps:

S01. Converting the input analog video signal into a digital video signal;

Multiplying the input clock signal to obtain a high-speed detection clock signal;

S02. The high-speed detection clock signal is used to sample the digital video signal, obtain relevant sampling parameters, and simultaneously perform multi-level synchronization on the multi-channel digital video signals;

S03. Adjusting and outputting a corresponding digital video signal according to the relevant sampling parameter, and receiving an external switching parameter;

S04. switching the synchronized multi-channel digital video signals according to the switching parameters;

S05. Convert the digital video signal of the switched output to an analog video signal.
The FPGA-based video synchronization switching method according to claim 6, wherein the step S04 further comprises a step A. Obtaining a pixel clock in the synchronized multi-channel digital video signal, and acquiring a multi-channel reset signal according to the switching parameter; B. buffering the synchronized multi-channel digital video signal.
The FPGA-based video synchronization switching method according to claim 7, wherein the step S04 specifically includes:

S401. Reset the corresponding storage address according to the multiple reset signal;

S402. Select data of a corresponding storage address according to the switching parameter.

S403. Perform multi-level synchronization on the selected data and output.
The FPGA-based video synchronization switching method according to claim 8, wherein the step B buffer storage is FIFO buffer isolation storage.