CN113014838A - Multi-format high-speed digital video fusion system based on FPGA - Google Patents
Multi-format high-speed digital video fusion system based on FPGA Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
- H04N5/445—Receiver circuitry for the reception of television signals according to analogue transmission standards for displaying additional information
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The invention discloses a multi-format high-speed digital video fusion system based on FPGA, which is based on an embedded FPGA framework, realizes decoding of multi-format videos by using FPGA internal logic, uniformly converts the multi-format videos into digital RGB video signals, performs caching, noise reduction, scaling and superposition on multi-channel video images in parallel, encodes and outputs the fused video signals in the FPGA, supports synchronous encoding of HDMI format and LVDS format and outputs the encoded signals to a liquid crystal display screen for display, integrates OSD on-screen display control, and realizes adjustment of video parameters such as brightness, contrast, display size, display position and the like of each channel by four-key OSD. The system realizes the control of the operation logic of each unit of the system by building a MicroBlaze soft core in the FPGA. The method is suitable for occasions for fusion analysis of multi-format high-speed video monitoring images in the military field.
Description
Technical Field
The invention belongs to the technical field of embedded FPGA, the field of computer network communication, the field of electronic communication and the like, and the system technology is applied to the fields of military industry, military monitoring and military display.
Background
With the rapid development of the scientific and military level, the reliability test of the weaponry is especially important. Extensive research testing of weaponry is required to maintain its advancement. In the process of research and test of weaponry with fast flight characteristics, multiple high-speed cameras are needed to be used for measuring and controlling each path of relevant information of a trajectory of a fast flight target, and when relevant researchers analyze and process multi-channel high-speed video data captured in the test process, the timeliness is poor, the accuracy is low, the research work efficiency is low, and the actual requirements of tests on a trajectory measurement system at the present stage cannot be met.
Most of video fusion system schemes designed for embedded systems at present are based on a high-performance FPGA + ARM architecture, but most of existing multi-format video fusion systems are limited to low resolution, poor in instantaneity and mostly do not support LVDS interface output. In few schemes supporting LVDS interface output, conversion from digital RGB signals to LVDS signals is converted through special integrated chips, the chips depend on import and do not have substitutes of home-made chips, on the basis, military vehicle-mounted multi-format high-speed video fusion measurement and control equipment supporting high-definition resolution and meeting the real-time requirement and the home-made requirement is designed, multi-path different image processing and display control of a ballistic measurement system are achieved, multi-path videos are fused and analyzed, and researchers can analyze ballistic related information more visually and more conveniently.
Disclosure of Invention
The invention aims to realize multi-channel diversity high-speed digital video image processing and on-Screen display control under a military vehicle-mounted environment, and the design of a multi-format high-speed digital video fusion system based on FPGA and the decoding of multi-format (SDI format and HDMI format) videos are realized, the videos are uniformly converted into digital RGB video signals and then subjected to noise reduction, scaling and superposition, the superposed processed video signals are supported to be encoded and output, the HDMI format and the LVDS format are supported to be synchronously encoded and output to a high-definition liquid crystal display, meanwhile, a channel OSD (on Screen display) display and memory image is supported to be superposed, and the adjustment of video parameters such as brightness, contrast, display size, display position and the like of each channel is realized through four-key OSD.
The technical scheme adopted by the invention is a multi-format high-speed digital video fusion system based on FPGA, which mainly comprises a video input module, a video cache module, an image processing module, a video output module, a communication interface module and a clock power supply management module.
The Video input module inputs the two-channel HDMI format Video data and the two-channel SDI format Video data into the FPGA, the RGB Video data is obtained after preprocessing such as corresponding format decoding and chrominance space conversion, and four paths of Video data are respectively converted into AXI Stream Video streams through a Video in toaAXI Stream IP core. The video cache module adopts DDR3 for storage, the module carries out frame cache processing on four-channel AXI Stream video Stream data in the input module through VDMA, the VDMA provides high-bandwidth direct storage access between an external memory DDR3 and the image processing module, and four paths of images subjected to frame cache can be synchronously read. The image processing module mainly realizes image scaling of each channel video subjected to cache processing, and realizes fusion of an OSD video memory image and a multi-channel image through a data selection control logic. The Video output module converts AXI Stream Video streams fused and output in the image processing module into RGB digital signals through AXI Stream to Video out IP, time sequence signals are generated through Video timing control IP, the Video is synchronously encoded and converted into an HDMI format and an LVDS format, and the system realizes the functions of the HDMI interface and the LVDS interface in an IO simulation mode. The communication interface module supports GPIO, UART and other communication interfaces, GPIO hardware is connected with four control keys and is mainly used for four-key OSD operation, corresponding key values are obtained through different key operations, and corresponding GUI interface refreshing and algorithm processing are executed according to OSD software display control logic. The UART interface is used for debugging information printing. The clock management module provides working clock control for the system, and the video coding and decoding part of the system uses 1920 x 1080@60Hz format pixel clock 148.5 Mhz. The video-domain running clocks are all driven by 300Mhz clocks. The working clock of the external memory DDR3 is 800Mhz, and the working mode that reading and writing operations are carried out on rising edges and falling edges is adopted. Power management supports 12V input.
The realization of the multi-format high-speed digital video fusion system provides a real-time, intuitive and reliable monitoring platform for monitoring the fast flying target in the ballistic measurement system. The multichannel anisotropic image processing and display control of the ballistic trajectory measurement system are realized through a single FPGA architecture and an embedded MicroBlaze soft core design, and the parameters such as brightness, contrast and the like of a high-speed video channel can be adjusted on a screen through OSD. The multichannel video is fused for analysis, so that related personnel can accurately analyze trajectory monitoring information more intuitively and conveniently at the first time.
The multi-format high-speed digital video fusion system is realized by using an FPGA (field programmable gate array) architecture. The system preprocessing unit is responsible for decoding multi-format videos and chrominance space conversion of video data, the video processing unit is used for reducing noise, zooming, overlapping and caching the videos, the video coding unit is used for coding the fused videos, a MicroBlaze soft core is built by FPGA (field programmable gate array) internal resources to realize control over each unit, OSD (on screen display) man-machine interaction is supported for overlapping an OSD video memory image of one channel, adjustment of video parameters of each channel of the system is realized, and the video parameters are finally output to a high-definition liquid crystal display screen for display.
As shown in fig. 1, the multi-format high-speed digital video fusion system framework adopts a single FPGA architecture, and compared with the design of the FPGA + ARM architecture, video encoding and decoding are all implemented by using logic inside the FPGA, so that the system integration level is higher, and the system design is simpler. The hardware design periphery of the system is mainly divided into five parts: the device comprises a video input module, a video output module, a video cache module, a communication interface module and a clock power supply module. The video input module supports two HDMI interfaces and two SDI interfaces; the video output module supports one path of LVDS interface output and one path of HDMI interface output; the video cache module adopts DDR3 for storage; the communication interface module supports GPIO, UART and other communication interfaces; the power management module supports a 12V input.
As shown in fig. 2, a MicroBlaze soft core is built in an FPGA to realize flow control of each unit of the system, four-channel high-definition videos (2-channel HDMI format and 1-channel SDI format) are input into the FPGA and then are respectively decoded, and are uniformly converted into digital RGB video signals to be preprocessed, then video frames of each channel are cached in DDR3, the MicroBlaze soft core controls operation logic of each unit, when each channel realizes one-frame caching, four channels of videos can be read out through synchronous control logic to execute parallel video algorithm processing, including video noise reduction, video scaling, video superposition and the like, and after output selection control logic, the processed videos are synchronously encoded into HDMI format and LVDS format video signals in the FPGA and are output to a high-definition display screen to be displayed.
The system integrates the OSD on-screen control function and realizes more friendly human-computer interaction. The software system framework of the OSD unit is shown in the following figure 3, the application layer is designed for an OSD menu GUI interface, the middle layer relates to an interface key message response mechanism, the middle layer provides a corresponding interface to package a driving layer, the equipment driving layer interacts with a hardware platform, and when a key is pressed, the dynamic refreshing of the OSD menu can be correspondingly realized.
The method comprises the steps that a PS end software control program of the multi-format high-speed digital video fusion system is realized by using a C language, a video processing algorithm logic is designed by using a Verilog language and is packaged and integrated in a Vivado, and a PL end of an FPGA and a MicroBlaze soft core (PS end) carry out information interaction of data and commands through an AXI bus. As shown in fig. 4, the system control logic flow includes, first, performing initialization configuration of the system according to predetermined parameters, then, determining key operation, directly displaying and outputting the content of the current system configuration when no key is pressed, logically responding to key information when a parameter of a certain channel is adjusted by a key, refreshing an OSD memory image, and simultaneously transmitting corresponding parameters to IP registers of the PL side through an AXI bus for real-time configuration update. And after the system re-configures the parameters of the video processing modules of each channel, dynamically adjusting the multi-channel video.
The system can realize multi-channel differential image processing and display control in real time and can support four paths of 1920 x 1080@60Hz high-definition video signal input and output. The video coding and decoding are realized by using logic in the FPGA, so that an imported coding and decoding chip is avoided, a large amount of peripheral circuits are saved, and the research and development cost is reduced to a certain extent. The OSD on-screen display control function solves the problem that the upper computer software in the existing multi-video fusion system depends on the computer control, and the system integration level is improved compared with the video fusion system scheme of the mainstream FPGA + ARM framework.
Drawings
Fig. 1 is a block diagram of a hardware design of a multi-format high-speed digital video fusion system.
Fig. 2 is a block diagram of a multi-format high-speed digital video fusion system software design.
FIG. 3 is a software architecture of the OSD unit.
Fig. 4 is a flow chart of the control logic of the multi-format high-speed digital video fusion system.
Fig. 5 is a system OSD menu interface layout.
Fig. 6 is the system initialization output.
Fig. 7 is a system LVDS interface output display.
Fig. 8 is a system HDMI interface output presentation.
Fig. 9 is a two-channel SDI format video overlay output presentation.
Fig. 10 is a two-channel HDMI format video stitching output presentation.
Detailed Description
Firstly, video sources are respectively connected into four input interfaces (2 HDMI input interfaces and two SDI input interfaces) of a system board, two output interfaces (HDMI and LVDS) of the system board are respectively connected to a high-definition liquid crystal screen of a corresponding interface by connecting wires, and a JTAG downloader is connected to a JTAG interface of the system board and a computer. And after the signal wire is connected, the system board is powered on, the FPGA logic is downloaded through the Vivado SDK tool, and after the downloading is finished, the program is started and initialized and configured.
When the system is initialized, video signals with the resolution of 1920 × 1080 video signals in the two-channel HDMI format and the two-channel SDI format are respectively scaled to 960 × 540 resolution and are spliced into a picture with 1920 × 1080 size. The system initialization output is as shown in fig. 6 below, and at this time, the display screen at the output end is formed by splicing four parts, namely an upper left HDMI1 video source input, an upper right HDMI2 video source input, a lower left SDI1 video source input, and a lower right SDI2 video source input. And the video signals are simultaneously output to the high-definition liquid crystal display screen with the corresponding interface through the HDMI and LVDS interfaces for displaying.
After the output display is initialized, the OSD MENU is opened through a 'MENU' key of the key board. As shown in fig. 5, there are five secondary submenus on the left side of the OSD menu, which are respectively "channel selection", "brightness adjustment", "contrast adjustment", "display position" and "display size", and there are several three levels of submenus under each secondary submenu, and the upper right of the OSD interface prompts the currently set channel number.
The functions of the five secondary submenus are selected and cyclically switched by the "up" and "down" keys of the keypad. When the 'MENU' key is pressed to enter a certain secondary submenu, the interface displays the currently selected tertiary submenu of the secondary submenu, the 'MENU' key is pressed again to enter the tertiary submenu, and at the moment, the functions of the tertiary submenu can be selected and switched circularly through the 'decrease' key and the 'increase' key of the key board. Here, as an example of the display size setting, when the "MENU" key is pressed to enter the display size of the three-level submenu, the resolution to be changed may be cycled and switched by pressing the "decrease" and "increase" keys of the keypad, the "decrease" key is pressed, the option is moved downward, the "increase" key is pressed, the option is moved upward, when the corresponding parameter is selected, the "MENU" key is pressed again to confirm the current change, then the "return" key is pressed to exit the current-level MENU and return to the previous-level MENU, and the "return" key is pressed again to exit the OSD MENU closing after returning to the main MENU.
The system supports the random adjustment of the scaling size and the display position of each channel video, and can scale the input 1920 x 1080 high-definition video into a plurality of resolution sizes to be displayed at any position of the high-definition liquid crystal screen.
When the OSD menu is opened, the display interface of the output end is formed by splicing an upper left part, an upper right part, a lower left part and a lower right part, wherein the upper left part is an HDMI1 video source input, the upper right part is an HDMI2 video source input, the lower left part is an SDI1 video source input, and the lower right part is an OSD video memory image channel. When the OSD menu pops up for the first time after initialization, the output of SDI2 at the lower right is closed by default control, and the OSD video memory image is covered in the lower right area. Fig. 7 shows that the video processed by the system is output through the LVDS interface, and fig. 8 shows that the video processed by the system is output through the LVDS interface.
The output display switch and the display position of each channel can be adjusted by a user. The two-channel HDMI video source image output can be turned off through OSD setting, the two-channel SDI video source image output is reserved, the 1920 × 1080 resolution high-definition video input of one channel is scaled to 1280 × 720 resolution and then overlaid on the video source image of 1920 × 1080 resolution of the other channel which is not scaled, and the video source image is output to the high-definition display screen for display, as shown in fig. 9.
The output of the SDI channel video source image can be closed through OSD setting, the output of the two-channel HDMI video source image is reserved, and the two-channel 1920 × 1080 resolution high-definition video is respectively zoomed into 960 × 540 resolution and then is superposed, spliced and output to the high-definition display screen for display, as shown in FIG. 10.
Claims (7)
1. A multi-format high-speed digital video fusion system based on FPGA is characterized in that: the system comprises a video input module, a video cache module, an image processing module, a video output module, a communication interface module and a clock power management module.
The Video input module inputs the two-channel HDMI format Video data and the two-channel SDI format Video data into the FPGA, the RGB Video data is obtained after preprocessing such as corresponding format decoding and chrominance space conversion, and four paths of Video data are respectively converted into AXI Stream Video streams through a Video in toaAXI Stream IP core. The video cache module adopts DDR3 for storage, the module carries out frame cache processing on four-channel AXI Stream video Stream data in the input module through VDMA, the VDMA provides high-bandwidth direct storage access between an external memory DDR3 and the image processing module, and four paths of images subjected to frame cache can be synchronously read. The image processing module realizes image scaling of each channel video subjected to cache processing, and realizes fusion of an OSD video memory image and a multi-channel image through a data selection control logic. The Video output module converts AXI Stream Video streams fused and output in the image processing module into RGB digital signals through AXI Stream to Video out IP, time sequence signals are generated through Video timing control IP, the Video is synchronously encoded and converted into an HDMI format and an LVDS format, and the system realizes the functions of the HDMI interface and the LVDS interface in an IO simulation mode. The communication interface module supports GPIO and UART communication interfaces, wherein GPIO hardware is connected with four control keys. The UART interface is used for debugging information printing. The clock management module provides working clock control for the system.
2. The FPGA-based multi-format high-speed digital video fusion system of claim 1, characterized in that: the multi-path anisotropic image processing and display control of the ballistic measurement system are realized through a single FPGA framework and an embedded MicroBlaze soft core design, and the brightness and contrast parameters of a high-speed video channel are adjusted on a screen through OSD. The multichannel video is fused for analysis, so that related personnel can accurately analyze trajectory monitoring information intuitively and conveniently at the first time.
3. The FPGA-based multi-format high-speed digital video fusion system of claim 1, characterized in that: the multi-format high-speed digital video fusion system is realized by using an FPGA (field programmable gate array) architecture. The system preprocessing unit is responsible for decoding multi-format videos and chrominance space conversion of video data, the video processing unit is used for reducing noise, zooming, overlapping and caching the videos, the video coding unit is used for coding the fused videos, a MicroBlaze soft core is built by FPGA (field programmable gate array) internal resources to realize control over each unit, OSD (on screen display) man-machine interaction is supported for overlapping an OSD video memory image of one channel, adjustment of video parameters of each channel of the system is realized, and the video parameters are finally output to a high-definition liquid crystal display screen for display.
4. The FPGA-based multi-format high-speed digital video fusion system of claim 1, characterized in that: the multi-format high-speed digital video fusion system framework adopts a single FPGA (field programmable gate array) framework, and the video input module supports two HDMI interfaces and two SDI interfaces; the video output module supports one path of LVDS interface output and one path of HDMI interface output; the video cache module adopts DDR3 for storage; the communication interface module supports GPIO and UART communication interfaces; the power management module supports a 12V input.
5. The FPGA-based multi-format high-speed digital video fusion system of claim 1, characterized in that: the method comprises the steps of building a MicroBlaze soft core in an FPGA to realize flow control of each unit of the system, firstly respectively decoding four-channel high-definition videos after being input into the FPGA, uniformly converting the four-channel high-definition videos into digital RGB video signals, preprocessing the videos, caching video frames of each channel into DDR3, controlling operation logic of each unit by the MicroBlaze soft core, reading four channels of videos to execute parallel video algorithm processing through synchronous control logic after each channel realizes one-frame caching, performing video noise reduction, video scaling and video superposition, synchronously encoding the processed videos into HDMI format video signals and LVDS format video signals in the FPGA after output selection control logic, and outputting the HDMI format video signals to a high-definition display screen for display.
6. The FPGA-based multi-format high-speed digital video fusion system of claim 1, characterized in that: the system integrates OSD on-screen control function, an application layer is designed for an OSD menu GUI interface in an OSD unit software system framework, an intermediate layer relates to an interface key message response mechanism, the intermediate layer provides a corresponding interface to package a driving layer, the equipment driving layer interacts with a hardware platform, and when a key is pressed, dynamic refreshing of the OSD menu is correspondingly realized.
7. The FPGA-based multi-format high-speed digital video fusion system of claim 1, characterized in that: the PS end software control program of the multi-format high-speed digital video fusion system is realized by using C language, the video processing algorithm logic is designed by using Verilog language and is packaged and integrated in Vivado, and the PL end of the FPGA and the MicroBlaze soft core carry out information interaction of data and commands through an AXI bus. The system control logic flow comprises the steps of firstly, carrying out initialization configuration on a system according to preset parameters, then judging key operation, directly displaying and outputting the content of current system configuration when no key is pressed down, logically responding to key messages when the adjustment of a certain parameter of a certain channel is carried out through keys, refreshing an OSD video memory image, and simultaneously transmitting the corresponding parameter to each IP register of a PL (programmable logic) end through an AXI (advanced extensible interface) bus for carrying out real-time configuration updating. And after the system re-configures the parameters of the video processing modules of each channel, dynamically adjusting the multi-channel video.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113672310A (en) * | 2021-08-23 | 2021-11-19 | 高创(苏州)电子有限公司 | Wireless system, intelligent display equipment and information interaction method |
| CN113727161A (en) * | 2021-09-03 | 2021-11-30 | 南京大学 | Microblaze-based real-time video seam clipping method and system |
| CN114071031A (en) * | 2021-11-12 | 2022-02-18 | 天津市英贝特航天科技有限公司 | Multi-channel video overlapping and switching method and device |
| CN114286106A (en) * | 2021-12-29 | 2022-04-05 | 苏州长风航空电子有限公司 | Multi-path SDI video extremely-low-delay coding system and method based on MPSoC |
| CN115103190A (en) * | 2022-06-14 | 2022-09-23 | 晶晨芯半导体(成都)有限公司 | Encoder code rate control method and module, chip, electronic equipment and storage medium |
| CN116320218A (en) * | 2023-05-24 | 2023-06-23 | 深圳金智凌轩视讯技术有限公司 | Multipath video synthesis analysis processing management system based on embedded computer platform |
| WO2023184161A1 (en) * | 2022-03-29 | 2023-10-05 | 京东方科技集团股份有限公司 | Human-computer interaction method and system for display device |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103618869A (en) * | 2013-11-25 | 2014-03-05 | 广东威创视讯科技股份有限公司 | Multi-image video stitching method and device |
| CN103813107A (en) * | 2014-03-05 | 2014-05-21 | 湖南兴天电子科技有限公司 | Multichannel high-definition video overlapping method based on FPGA (field programmable gata array) |
| CN105187745A (en) * | 2015-08-30 | 2015-12-23 | 深圳市特力科信息技术有限公司 | High definition video OSD menu superposition module based on FPGA and method |
| WO2016201892A1 (en) * | 2015-06-16 | 2016-12-22 | 邦彦技术股份有限公司 | Fpga-based synchronous video switching system and method |
| CN106934758A (en) * | 2017-03-01 | 2017-07-07 | 南京大学 | A kind of three-dimensional image video real time integrating method and system based on FPGA |
| CN109743515A (en) * | 2018-11-27 | 2019-05-10 | 中国船舶重工集团公司第七0九研究所 | A kind of asynchronous video fusion overlapping system and method based on soft core platform |
| CN112040201A (en) * | 2020-09-28 | 2020-12-04 | 深圳市康维讯视频科技有限公司 | Asynchronous four-division monitor for broadcast stage based on FPGA |
| CN112235518A (en) * | 2020-10-14 | 2021-01-15 | 天津津航计算技术研究所 | Digital video image fusion and superposition method |
-
2021
- 2021-03-03 CN CN202110235165.7A patent/CN113014838B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103618869A (en) * | 2013-11-25 | 2014-03-05 | 广东威创视讯科技股份有限公司 | Multi-image video stitching method and device |
| CN103813107A (en) * | 2014-03-05 | 2014-05-21 | 湖南兴天电子科技有限公司 | Multichannel high-definition video overlapping method based on FPGA (field programmable gata array) |
| WO2016201892A1 (en) * | 2015-06-16 | 2016-12-22 | 邦彦技术股份有限公司 | Fpga-based synchronous video switching system and method |
| CN105187745A (en) * | 2015-08-30 | 2015-12-23 | 深圳市特力科信息技术有限公司 | High definition video OSD menu superposition module based on FPGA and method |
| CN106934758A (en) * | 2017-03-01 | 2017-07-07 | 南京大学 | A kind of three-dimensional image video real time integrating method and system based on FPGA |
| CN109743515A (en) * | 2018-11-27 | 2019-05-10 | 中国船舶重工集团公司第七0九研究所 | A kind of asynchronous video fusion overlapping system and method based on soft core platform |
| CN112040201A (en) * | 2020-09-28 | 2020-12-04 | 深圳市康维讯视频科技有限公司 | Asynchronous four-division monitor for broadcast stage based on FPGA |
| CN112235518A (en) * | 2020-10-14 | 2021-01-15 | 天津津航计算技术研究所 | Digital video image fusion and superposition method |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113672310A (en) * | 2021-08-23 | 2021-11-19 | 高创(苏州)电子有限公司 | Wireless system, intelligent display equipment and information interaction method |
| CN113727161A (en) * | 2021-09-03 | 2021-11-30 | 南京大学 | Microblaze-based real-time video seam clipping method and system |
| CN113727161B (en) * | 2021-09-03 | 2022-07-29 | 南京大学 | Microblaze-based real-time video seam clipping method and system |
| CN114071031A (en) * | 2021-11-12 | 2022-02-18 | 天津市英贝特航天科技有限公司 | Multi-channel video overlapping and switching method and device |
| CN114286106A (en) * | 2021-12-29 | 2022-04-05 | 苏州长风航空电子有限公司 | Multi-path SDI video extremely-low-delay coding system and method based on MPSoC |
| CN114286106B (en) * | 2021-12-29 | 2024-02-13 | 苏州长风航空电子有限公司 | MPSoC-based multipath SDI video extremely-low-delay coding system |
| WO2023184161A1 (en) * | 2022-03-29 | 2023-10-05 | 京东方科技集团股份有限公司 | Human-computer interaction method and system for display device |
| CN115103190A (en) * | 2022-06-14 | 2022-09-23 | 晶晨芯半导体(成都)有限公司 | Encoder code rate control method and module, chip, electronic equipment and storage medium |
| CN116320218A (en) * | 2023-05-24 | 2023-06-23 | 深圳金智凌轩视讯技术有限公司 | Multipath video synthesis analysis processing management system based on embedded computer platform |
| CN116320218B (en) * | 2023-05-24 | 2023-08-29 | 深圳金智凌轩视讯技术有限公司 | Multipath video synthesis analysis processing management system based on embedded computer platform |
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