CN108632547A - A kind of multi-channel video preprocess method - Google Patents
A kind of multi-channel video preprocess method Download PDFInfo
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- CN108632547A CN108632547A CN201711295801.5A CN201711295801A CN108632547A CN 108632547 A CN108632547 A CN 108632547A CN 201711295801 A CN201711295801 A CN 201711295801A CN 108632547 A CN108632547 A CN 108632547A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/47—End-user applications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/431—Generation of visual interfaces for content selection or interaction; Content or additional data rendering
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/47—End-user applications
- H04N21/485—End-user interface for client configuration
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0117—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving conversion of the spatial resolution of the incoming video signal
- H04N7/012—Conversion between an interlaced and a progressive signal
Abstract
The present invention relates to image/video process field more particularly to a kind of multi-channel video preprocess methods, the difference is that：Its step includes：A：The selection of video source；B：The extraction and judgement of video parameter；C：Video source scales；D：Video source cache and multi-channel video overlap-add procedure；E：Video source format conversion.Flexibility of the present invention is good, real-time.
Description
Technical field
The present invention relates to image/video process field more particularly to a kind of multi-channel video preprocess methods.
Background technology
With the rapid development of computer technology, the communication technology, network technology and multimedia technology, the appearance of digital technology
Far-reaching influence is brought for the life of modern humans with application, nowadays the mankind live in a digitized world,
It is special since digital signal has remote transmission, be easy storage and the information of storage is reliable and high quality reduction and cumulative distortion are small etc.
Point has been applied in many aspects of people's daily life；
The mankind receive information and mainly realize that 70% is to come from inside the information received by vision and sense of hearing two ways
Vision, so general more much larger than the audio-frequency information amount obtained by the sense of hearing by the video image information that vision obtains；Usually
The most effective and most important information acquiring pattern of the mankind is the image by retina to surrounding scenes, so video image has
Intuitively, specifically, vividly, it is true, efficient and many advantages, such as be widely used；
Multi-channel video superimposing technique is an application direction of video image processing technology, it by multichannel Multi-standard video signal into
Row processing forms vision signal all the way with additive fusion and exports, this technology is in television system, video monitoring system, advertisement recreational
It is significant thus be widely used in system, military field；It, can be real using multi-channel video superimposing technique in television system
Existing double vision window, more forms show that is, a screen can show the video of multiple channels, can also realize picture-in-picture effect, i.e., one
A main view frequency takes screen, and a secondary video is superimposed upon in a manner of wicket on main view frequency, and can be with shift position；In machine
Carry electronic system integrated display system in, using video superimposing technique can by airborne computer export comprising virtual instrument,
Map, various sensor parameters characters video shown together with externally input video additive fusion, enable pilot
Abundant information is obtained easily and fast；
But the extensive use with multi-channel video superimposing technique in each field, flexibility that technical staff is superimposed multi-channel video and
More stringent requirements are proposed for real-time, in consideration of it, provide a kind of flexibility is good, real-time multi-channel video preprocess method at
For this field urgent problem to be solved.
Invention content
It is an object of the invention to overcome the prior art, a kind of multi-channel video preprocess method, flexibility are provided
It is good, it is real-time.
In order to solve the above technical problems, the technical scheme is that：A kind of multi-channel video preprocess method, feature exist
In step includes：
A：The selection of video source；
A1：It inputs multipath video source and using being decoded to it with the matched video decoding chip of video source, obtains video
Source data；
A2：Select video source：It may be selected wherein arbitrarily all the way, to use as encoder；Also wherein arbitrary multichannel may be selected, as
Video superimposer uses, and carries out multi-channel video superposition；
B：The extraction and judgement of video parameter：
B1：Row field blanking instruction is obtained from the timing base code of video source data, is then somebody's turn to do according to row field blanking instruction
The resolution ratio and frame frequency size of video source；
B2：Judge whether resolution ratio and frame frequency match with the parameter that system processor is arranged, if matching, by video source export to
In next step, otherwise, blue screen is exported；
C：Video source scales：The resolution ratio being arranged according to system processor zooms in and out video source；If the video source of input is
Interlaced mode then needs video source being converted to pattern line by line from interlaced mode；
D：Video source cache and multi-channel video overlap-add procedure：
If only having selected video all the way in step A, this step is skipped；If having selected multi-channel video in step A, by this step
Suddenly；This step is specially：Plug-in DDR3 is arranged to store every road video source, data are read simultaneously from DDR3 after having stored
Video superposition is carried out using the OSD cores in FPGA；
E：Video source format conversion：Video source is encoded and is sent to system processor and carries out subsequent processing；
F：Initial configuration flow：Initial configuration flow is carried out, whole flow process is completed in system processor, and system processor is phase
Related parameter is allocated to FPGA, is communicated by SPI interface between system processor and FPGA；
G：Re-match flow：It is right according to configuration parameter and last difference when program sets different parameters in the process of running
Module is targetedly configured.
By above scheme, the video source inputted in the step A1 is 3 tunnels, and the wherein first via is DVI or VGA, with its phase
The video decoding chip of cooperation is ADV7441, and the second road and third road are SDI, and the video decoding chip being matched therewith is
GS2971；When selecting video source in step A2, any of which can be selected all the way, used as DVI, VGA or SDI encoder,
Wherein two-way or three tunnels can also be selected, multi-channel video superposition is carried out, is used as video superimposer.
By above scheme, the video source data in the step B1 is BT1120 formats, and the video source data specifically wraps
It includes：Image data, timing base code, ancillary data.
By above scheme, the step C is specifically included：
C1：Video source is zoomed in and out according to the resolution ratio of system processor HI3516A settings, the specific steps are：
C11：Simultaneously relevant parameter is arranged in the Video Scaler IP kernels of exampleization FPGA, and the parameter includes filter parameter, video
Source inputs size and Output Size range, video input format, core handle clock and can support maximum frame rate；
C12：Size is inputted according to video source in system processor HI3516A and Output Size calculates horizontal scaling factor
HSF and vertically scale factor Ⅴ SF, HSF=[round (input_h_size/output_h_size) * 2^20], VSF=
[round (input_v_size/output_v_size) * 2^20], input_h_size is horizontal input size in formula,
Input_v_size is vertical input size, and output_h_size is vertical output size, and output_v_size is vertical defeated
Go out size；
C13：Horizontal scaling factor HSF and vertically scale factor Ⅴ SF are allocated to Video Scaler IP kernels, to video source
Zoom in and out processing；
C2：If the video source of input is pattern line by line, without carrying out pattern conversion, if the video source of input is interlaced mode,
It then needs video source being converted to pattern line by line from interlaced mode.
By above scheme, the pattern in the video scaling and step C2 in the step C1 is converted in the Video of FPGA
It is completed in Scaler IP kernels.
By above scheme, the step D is specifically included：
D1：Plug-in DDR3 is arranged to store every road video source：When storing video source, to every road video source respectively according to
One frame is stored, and data are read from DDR3 for video superposition after having stored a frame；Wherein, the DDR3 is by FPGA
Included MIG cores control it；
D2：Video superposition is carried out using the OSD cores in FPGA, the specific steps are：
D21：The OSD IP kernels of exampleization FPGA simultaneously configure relevant parameter, and the relevant parameter includes that video format, video data are wide
Degree, the number of plies and layer configuration；
D22：Every layer of background colour, Alpha-blending (transparent mixing), size are calculated in system processor HI3516A
And the calculating of location parameter；
D23：By every layer calculated of background colour, Alpha-blending (transparent mixing), size and location parameter configuration
OSD IP kernels are given, video is overlapped.
By above scheme, the number of plies in the step D21 is 3 layers, when three road video superpositions, provides a main window,
The position of two wickets, wicket can drag and change, and wicket and main window can be interchanged, and form multi-channel video
It is superimposed picture-in-picture function.
By above scheme, in the step E, when being encoded to video source, encoded according to BT1120 formats.
By above scheme, in the step F, initial configuration flow includes mainly：Close fpga logic figure layer, configuration
Clock needed for BT1120 formats, each road video input size of configuration, each road SCALER of configuration, each road OSD of configuration, configuration BT1120
Total size and effective size open fpga logic figure layer.
By above scheme, the system processor is HI3516A processors.
By said program it is found that this method can support multipath video source while input, and it can support different video source classes
Type, video source parameter are also adapted dynamically；Further, the present invention is configurable to single channel encoder, can be configured as multichannel
Video superimposer supports picture-in-picture function, and main window size is adjustable, and wicket size and position are adjustable, wicket
It is interchangeable etc. with main window, various modes can be configured to, very flexibly；Meanwhile the present invention completes entire pretreatment using FPGA
Process, each operation is parallel, real-time, fast response time.
Description of the drawings
Fig. 1 is multi-channel video preprocess method the general frame of the present invention；
Fig. 2 is BT1120 data format block diagrams；
Fig. 3 is Scaler top layer interfaces；
Fig. 4 is Scaler parameter configuration block diagrams；
Fig. 5 is OSD top layer interfaces；
Fig. 6 is OSD parameter configuration block diagrams；
Fig. 7 is initialization flow diagram；
Fig. 8 attaches most importance to flow diagram.
Specific implementation mode
Below by specific implementation mode combination attached drawing, invention is further described in detail.
Referring to FIG. 1, Fig. 1 is multi-channel video preprocess method the general frame of the present invention, mainly by following components structure
At：The selection of video source, the extraction of video parameter and judgement, video source scaling, video source cache and multi-channel video overlap-add procedure,
Video source format conversion；The step of multi-channel video preprocess method of the present invention is：
A：The selection of video source；
A1：It inputs multipath video source and using being decoded to it with the matched video decoding chip of video source, obtains video
Source data；The video source that the present invention inputs is 3 tunnels, and wherein the first via is DVI or VGA, supports resolution ratio 1920*1200,1920*
1080,1080*720 etc., the video decoding chip being matched therewith is ADV7441, and the second road and third road are SDI, support to divide
Resolution is 1920*1080,1080*720 etc., and the video decoding chip being matched therewith is GS2971；
A2：Select video source：It may be selected wherein arbitrarily all the way, to use as encoder；Also wherein arbitrary multichannel may be selected, as
Video superimposer uses, and carries out multi-channel video superposition；In the embodiment of the present invention, when selecting video source all the way, as DVI, VGA
Or SDI encoders use, and when selection wherein two-way or three tunnels, carry out multi-channel video superposition, are used as video superimposer.
B：The extraction and judgement of video parameter：
B1：Row field blanking instruction is obtained from the timing base code of video source data, is then somebody's turn to do according to row field blanking instruction
The resolution ratio and frame frequency size of video source；The data to come from video decoding chip ADV7441 and GS2971 support BT1120 lattice
Formula, ITU-R BT.1120 digital interfaces are the unidirectional connections of offer between individual signals source and single destination, referring to Fig. 2,
In Fig. 2, BT1120 formatted datas include mainly three parts：Image data, timing base code, ancillary data, wherein image data
It is actually active data；Timing base code mainly has a SAV and EAV, the leading FF, FF, 00 of 3 byte of SAV and EAV signals, and last 1
Byte XY indicates the line position in the position of entire data frame and how to distinguish that bit7 fixed datas are that 1, bit6 indicates parity field,
Bit5 indicates whether the row is effective video data, and bit4 expressions are SAV or EAV, and bit3 ~ bit0 indicates protection signal；It is attached
It is that the fixation of row field blanking data is filled with 16 binary datas 8010 to belong to data；We can obtain capable field from timing base code and disappear
Then hidden instruction indicates the resolution ratio and frame frequency size that obtain the video source according to row field blanking；
B2：Judge whether the resolution ratio calculated in real time and frame frequency match with the parameter that system processor HI3516A is arranged, if
Match, then video source is exported in next step, otherwise, export blue screen；
C：Video source scales：Video source is zoomed in and out according to the resolution ratio of system processor HI3516A settings；If input regards
Frequency source is interlaced mode, then needs video source being converted to pattern line by line from interlaced mode；Video scaling and interlacing turn line by line
Pattern conversion is completed in the Video Scaler IP kernels of FPGA；
C1：Single channel export as video encoder and multiple-channel output as video superimposer when, be required for video according to
The resolution ratio of system processor HI3516A settings zooms in and out processing, the specific steps are：
C11：Simultaneously relevant parameter is arranged in the Video Scaler IP kernels of exampleization FPGA, and the parameter includes filter parameter, video
Source inputs size and Output Size range, video input format, core processing clock and can support maximum frame rate etc.；In the present invention
In embodiment, video input format uses YUV422；
C12：Size is inputted according to video source in system processor HI3516A and Output Size is completed to horizontal scaling factor
The calculating of HSF and vertically scale factor Ⅴ SF, HSF=[round (input_h_size/output_h_size) * 2^20], VSF
=[round (input_v_size/output_v_size) * 2^20], input_h_size is horizontal input size in formula,
Input_v_size is vertical input size, and output_h_size is vertical output size, and output_v_size is vertical defeated
Go out size；
C13：Horizontal scaling factor HSF and vertically scale factor Ⅴ SF are allocated to Video Scaler IP kernels, to video source
Zoom in and out processing；
C2：If the video source of input is pattern line by line, without carrying out pattern conversion, if the video source of input is interlaced mode,
It then needs video source being converted to pattern line by line from interlaced mode and gives system processor HI3516A processing, mitigate at system
Manage the pressure of device HI3516A processing；
D：Video source cache and multi-channel video overlap-add procedure：If only having selected video all the way in step A, this step is skipped；If
Multi-channel video has been selected in step A, then passes through this step；This step is specially：Be arranged plug-in DDR3 to every road video source into
Row storage carries out video superposition from reading data in DDR3 after having stored and using the OSD cores in FPGA；
The step D is specifically included：
D1：Plug-in DDR3 is arranged to store every road video source：When storing video source, to every road video source respectively according to
One frame is stored, and is read data from DDR3 after having stored a frame and is given video laminating module for video superposition；Its
In, complete the control to DDR3 using the MIG cores carried in FPGA；
D2：Video superposition is carried out using the OSD IP kernels in FPGA, OSD IP kernels could support up the α mixing of 8 layer videos or image,
It is capable of providing programmable background colour and programmable layer position；In embodiments of the present invention, 3 layers have been used, when three tunnels regard
When frequency is superimposed, a main window is provided, the position of two wickets, wicket can drag and change, and wicket and master
Window can be interchanged, and forms multi-channel video and is superimposed picture-in-picture function；The superposition of video and the variation of the window's position be all
It is completed in FPGA OSD IP kernels；When using OSD, the specific steps are：
D21：The OSD IP kernels of exampleization FPGA simultaneously configure relevant parameter, and the relevant parameter includes that video format, video data are wide
Degree, the number of plies and layer configuration；In the embodiment of the present invention, video format YUV422, video data 8bit, the number of plies 3, layer are matched
It is set to external AXI；
D22：Every layer of background colour, Alpha-blending (transparent mixing), size are calculated in system processor HI3516A
And the calculating of location parameter；
D23：By every layer calculated of background colour, Alpha-blending (transparent mixing), size and location parameter configuration
OSD IP kernels are given, video is overlapped；
E：Video source format conversion：The data of video source previous step are encoded according to format described in BT1120 formats, that is, Fig. 2
And it is sent to system processor HI3516A and carries out subsequent processing；In the embodiment of the present invention, the data of this step are defeated from OSD
The video data gone out；
F：Initial configuration flow：Fig. 7 shows initial configuration flow, and entire initial configuration is completed in HI3516A, at system
Relevant parameter is allocated to FPGA by reason device HI3516A, is communicated by SPI interface between HI3516A and FPGA；It is described initial
The detailed process of configuration is：It is big to close clock, each road video input of configuration needed for fpga logic figure layer, configuration BT1120 formats
Small, each road SCALER of configuration, each road OSD of configuration, configuration BT1120 total sizes and effective size open fpga logic figure layer；
It refers to that each module output is allowed not enable to close fpga logic figure layer, due to the processes pixel clock needed for different output resolution ratios
It is different, so pixel clock needed for output resolution ratio to be handled as requested in video frequency source coding, different pictures
Element processing clock is obtained by carries out what DRP (dynamic re-matches) was obtained to FPGA PLL, configures each road video size and Ge Lu
SCALER, configuration OSD complete the superposition to multi-channel video, configure BT1120 coding modules, finally open fpga logic figure layer, complete
The configuration of entire initialization flow in pairs；
G：Re-match flow：Fig. 8 shows re-matching flow diagram, and different parameters can be set in the process of running in program, at this point,
Reconfigured, in order to reduce setup time, improve response speed, thus when being re-matched be according to configuration parameter with
Last difference, set is identified to the module to be configured, then according to corresponding set mark to corresponding module into
Row re-matches and resets each re-matching mark, is targetedly to configure.
Above-mentioned steps are multi-channel video preprocess methods, can be zoomed in and out to single channel video and multi-channel video, superposition, lattice
Special-purpose imageprocessor is given to carry out subsequent operation after formula conversion, the advantages of embodiment of the present invention is：
1）Flexibility is good
The present invention can support multipath video source while input, and can support different video Source Types, resolution ratio, frame frequency, output
Resolution ratio also can be adjusted dynamically, and can be configured to single channel encoder can also be configured to multi-channel video superimposer, support picture-in-picture
Function, main window size is adjustable, and wicket size and position are adjustable, and wicket and main window are interchangeable etc., can configure
It is very flexible for various modes；
2）It is real-time
The present invention completes entire preprocessing process using FPGA, and it is parallel processing respectively to be operated in FPGA, therefore has very strong reality
When property and the small fast response time of system delay
3）Stability is strong
The present invention after fixed mode and pattern switching, stablize by code stream.
The above content is combining, specific embodiment is made for the present invention to be further described, and it cannot be said that this hair
Bright specific implementation is confined to these explanations.For those of ordinary skill in the art to which the present invention belongs, it is not taking off
Under the premise of from present inventive concept, a number of simple deductions or replacements can also be made, all shall be regarded as belonging to the protection of the present invention
Range.
Claims (10)
1. a kind of multi-channel video preprocess method, which is characterized in that its step includes：
A：The selection of video source；
A1：It inputs multipath video source and using being decoded to it with the matched video decoding chip of video source, obtains video
Source data；
A2：Select video source：It may be selected wherein arbitrarily all the way, to use as encoder；Also wherein arbitrary multichannel may be selected, as
Video superimposer uses, and carries out multi-channel video superposition；
B：The extraction and judgement of video parameter：
B1：Row field blanking instruction is obtained from the timing base code of video source data, is then somebody's turn to do according to row field blanking instruction
The resolution ratio and frame frequency size of video source；
B2：Judge whether resolution ratio and frame frequency match with the parameter that system processor is arranged, if matching, by video source export to
In next step, otherwise, blue screen is exported；
C：Video source scales：The resolution ratio being arranged according to system processor zooms in and out video source；If the video source of input is
Interlaced mode then needs video source being converted to pattern line by line from interlaced mode；
D：Video source cache and multi-channel video overlap-add procedure：
If only having selected video all the way in step A, this step is skipped；If having selected multi-channel video in step A, by this step
Suddenly；This step is specially：Plug-in DDR3 is arranged to store every road video source, data are read simultaneously from DDR3 after having stored
Video superposition is carried out using the OSD cores in FPGA；
E：Video source format conversion：Video source is encoded and is sent to system processor and carries out subsequent processing；
F：Initial configuration flow：Initial configuration flow is carried out, whole flow process is completed in system processor, and system processor is phase
Related parameter is allocated to FPGA, is communicated by SPI interface between system processor and FPGA；
G：Re-match flow：It is right according to configuration parameter and last difference when program sets different parameters in the process of running
Module is targetedly configured.
2. multi-channel video preprocess method according to claim 1, it is characterised in that：The video inputted in the step A1
Source is 3 tunnels, and wherein the first via is DVI or VGA, and the second road and third road are SDI；When selecting video source in step A2, Ke Yixuan
It selects any of which all the way, is used as DVI, VGA or SDI encoder, wherein two-way or three tunnels can also be selected, carry out multichannel and regard
Frequency is superimposed, and is used as video superimposer.
3. multi-channel video preprocess method according to claim 1, it is characterised in that：Video source number in the step B1
According to for BT1120 formats, the video source data specifically includes：Image data, timing base code, ancillary data.
4. multi-channel video preprocess method according to claim 1, it is characterised in that：The step C is specifically included：
C1：The resolution ratio being arranged according to system processor zooms in and out video source, the specific steps are：
C11：Simultaneously relevant parameter is arranged in the Video Scaler IP kernels of exampleization FPGA, and the parameter includes filter parameter, video
Source inputs size and Output Size range, video input format, core handle clock and can support maximum frame rate；
C12：Horizontal scaling factor HSF is calculated according to video source input size and Output Size in system processor and is hung down
Straight zoom factor VSF, HSF=[round (input_h_size/output_h_size) * 2^20], VSF=[round (input_
V_size/output_v_size) * 2^20], input_h_size is horizontal input size in formula, and input_v_size is vertical
Size is inputted, output_h_size is vertical output size, and output_v_size is vertical output size；
C13：Horizontal scaling factor HSF and vertically scale factor Ⅴ SF are allocated to Video Scaler IP kernels, to video source
Zoom in and out processing；
C2：If the video source of input is pattern line by line, without carrying out pattern conversion, if the video source of input is interlaced mode,
It then needs video source being converted to pattern line by line from interlaced mode.
5. multi-channel video preprocess method according to claim 4, it is characterised in that：Video scaling in the step C1
It is completed in the Video Scaler IP kernels of FPGA with the pattern conversion in step C2.
6. multi-channel video preprocess method according to claim 1, it is characterised in that：The step D is specifically included：
D1：Plug-in DDR3 is arranged to store every road video source：When storing video source, to every road video source respectively according to
One frame is stored, and data are read from DDR3 for video superposition after having stored a frame；Wherein, the DDR3 is by FPGA
Included MIG cores control it；
D2：Video superposition is carried out using the OSD cores in FPGA, the specific steps are：
D21：The OSD IP kernels of exampleization FPGA simultaneously configure relevant parameter, and the relevant parameter includes that video format, video data are wide
Degree, the number of plies and layer configuration；
D22：Every layer of background colour, transparent mixing, the calculating of size and location parameter are calculated in system processor；
D23：By every layer calculated of background colour, transparent mixing, size and location parameter are allocated to OSD IP kernels, to video
It is overlapped.
7. multi-channel video preprocess method according to claim 6, it is characterised in that：The number of plies in the step D21 is 3
Layer provides a main window when three road video superpositions, and the position of two wickets, wicket can drag and change, and
Wicket and main window can be interchanged, and form multi-channel video and are superimposed picture-in-picture function.
8. multi-channel video preprocess method according to claim 1, it is characterised in that：In the step E, to video source
When being encoded, encoded according to BT1120 formats.
9. multi-channel video preprocess method according to claim 1, it is characterised in that：In the step F, initial configuration stream
Journey includes mainly：Close clock, each road video input size of configuration, configuration needed for fpga logic figure layer, configuration BT1120 formats
Each road SCALER, each road OSD of configuration, configuration BT1120 total sizes and effective size open fpga logic figure layer.
10. multi-channel video preprocess method according to claim 1, it is characterised in that：The system processor is
HI3516A processors.
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| CN109819272A (en) * | 2018-12-26 | 2019-05-28 | 平安科技（深圳）有限公司 | Video transmission method, device, computer readable storage medium and electronic equipment |
| CN110753194A (en) * | 2019-10-23 | 2020-02-04 | 京东方科技集团股份有限公司 | Dual-screen different display method, storage medium and electronic equipment |
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