CN103686307A - Digital signal processor based multi-screen splicing display device - Google Patents
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Abstract
The invention discloses a digital signal processor based multi-screen splicing display device. The digital signal processor based multi-screen splicing display device comprises a network interface data transmission module, a video decoding module, digital signal processors and a video coding module, wherein the network interface data transmission module sends multiple de-multiplexed single-path video data to the video decoding module; the single-path video data correspond to a video source and include one or more single-frame video data; the video decoding module decodes the single-frame video data; each digital signal processor reads and compresses single-frame video data indicated in a scheduling message and stores the data in a corresponding storage block; the storage block is in one-to-one correspondence with the video source; each digital signal processor respectively reads the compressed single-frame video data in each storage block, and the video coding module codes and outputs the single-frame video data. The digital signal processor based multi-screen splicing display device efficiently solves the problems of poor real-time capability, insufficient storage capacity and poor processing capability of a multi-screen splicing technology, improves the real-time capability of the multi-screen splicing technology, improves storage capacity and a capability of performing parallel treatment on a large number of paths of videos.
Description
Technical field
The present invention relates to image/video processing technology field, particularly relate to a kind of multi-picture splicing display device based on digital signal processor.
Background technology
Along with the arrival of digital times, the depth & wideth of human cognitive things further increases, and to obtaining rapidly the demand of large information capacity, also strengthens thereupon.The continuous maturation of signal processing technology, network technology, the communication technology, makes video processing technique obtain broad development, also makes the use of video become the mankind and obtains rapidly in time the effective means of bulk information.Universal and the popularization gradually of IPTV (IPTV, Interactive Personality TV) technology, makes user can obtain high-quality digital media service and obtains the degree of freedom very widely to select all kinds of video frequency programs.
Video processing technique comprises collection, processing and the output of vision signal.Wherein, most crucial part is processing section.Particularly, being similar to the optical fiber of network video image of all kinds of video frequency programs of IPTV multiplexed is fast and effective video acquisition mode.The video data that processing section receiving front-end gathers, completes set Processing Algorithm for video data, and the video data of organizing is sent to next step.Output, according to the video signal standard setting, by the video data output of handling.The destination of output can be TV signal, computer video signal, can be also various video interfaces, display and control desk.
Further, in video processing technique, real-time is very important performance index.Early stage processing system for video, performance limitations due to core processing device, often can not process too large video image, and for VGA(Video Graphics Array that nowadays decomposing force and frame frequency are larger, Video Graphics Array) or DVI(Digital Visual Interface, digital visual interface) the RGB image of standard, deal with difficulty very large, particularly for the processing of a large amount of multi-channel video signals, processing speed and difficulty increase greatly, therefore the Capability Requirement of Video processing are also increased greatly.
More directly perceived in order to make to be similar to all kinds of video frequency programs of IPTV, and then produced multi-picture splicing technology, realize many picture displies of a plurality of video frequency programs.Multi-picture splicing technology be the video signal of the different resolution of a plurality of video source is dwindled to processing after, on same display terminal for user presents many picture effects, thereby provide maximum amount of information for user.Wherein, video source can comprise video camera, computer, television set, network etc.
But, due to the existing problem of video processing technique, cause multi-picture splicing technology to there is the limitation of the following aspects: 1, processing capability in real time is poor, because multi-picture splicing will gather a plurality of videos simultaneously, requirement of real-time when therefore, existing equipment is difficult to meet the demands output.2, restricted to the video quality of input, because traditional multi-picture splicing device storage capacity is limited, to high definition large-capacity video, cannot process.3, restricted to the way of multi-channel video, only can process splicing to several signals, to too much video way, cannot process.
Summary of the invention
Multi-picture splicing technology real-time for prior art is poor, lack of memory capacity and the problem that can not process too much video way, the present invention proposes a kind of multi-picture splicing display device based on digital signal processor, to promote the real-time of multi-picture splicing technology, the ability that improves memory capacity and the video of a large amount of ways is processed.
For solving the problems of the technologies described above, a kind of multi-picture splicing display device based on digital signal processor provided by the invention comprises: network interface data transmission module, video decode module, local management module, one or more pieces digital signal processors, video encoding module, display; Wherein: network interface data transmission module will receive a plurality of single channel video datas of multi-path video data demultiplexing, and described a plurality of single channel video data transmittings of the one or more single channel video datas that receive and demultiplexing are delivered to video decode module; Wherein, the corresponding video source of single channel video data described in each, described single channel video data comprises one or more single frames video datas; Video decode module is decoded to each single frames video data; Local management module generates schedule information according to every digital signal processor when single frames the video data volume of pre-treatment, to control every digital signal processor, reads single frames video data indicated in described schedule information; Every described digital signal processor compresses the described single frames video data reading, and by compression after single frames Video Data Storage in corresponding memory block; Wherein, there is one-to-one relationship in described memory block and video source, and a viewing area in the corresponding display of each memory block; Every described digital signal processor reads respectively the single frames video data after compression in each memory block, and exports to video encoding module; Described video encoding module is encoded respectively, and each stores the single frames video data after fast middle compression, and exports to display, with multi-path video data described in Concurrent Display in one or more viewing areas of correspondence.
Wherein, can also comprise: in advance the shared memory cell of described one or more pieces digital signal processors is divided into one or more memory blocks; For each memory block distribution network address; Between the network address of described each memory block and the network address of a video source, corresponding relation is set, to realize the corresponding one by one of memory block and video source.
Wherein, can also comprise: every digital signal processor is connected with external memory modules.
Wherein, described every digital signal processor comprises single frames video data input port and First Input First Output data buffer zone; Described input port receives single frames video data, and according to first-in first-out rule by the single frames Video Data Storage receiving in First Input First Output data buffer zone.
Wherein, described every digital signal processor also comprises Ethernet medium access controller, wherein: Ethernet medium access controller is sent to each the single frames video data in First Input First Output data buffer zone in corresponding external memory modules, so as digital signal processor to the single frames video data in described external memory modules compress, concatenation.
Beneficial effect of the present invention is as follows:
The present invention utilizes DSP to have the advantages that processing capability in real time is strong, processes the multi-channel video of collection, makes equipment provided by the invention have good real-time in video output, has improved disposal ability and the real-time of multi-picture splicing.And the present invention utilizes the advantage that DSP can extension storage unit, and then promoted the memory capacity of multi-picture splicing, can splice processing to the video of multichannel different resolution different capabilities, made multi-picture splicing have more reliability.
Accompanying drawing explanation
Fig. 1 is the structural representation of the multi-picture splicing display device based on digital signal processor according to an embodiment of the invention;
Fig. 2 is the workflow diagram of the multi-picture splicing display device based on digital signal processor according to an embodiment of the invention;
Fig. 3 is the structural representation of network interface data transmission module according to an embodiment of the invention;
Fig. 4 is the structural representation of DSP according to an embodiment of the invention;
Fig. 5 is the structural representation of Ethernet medium access controller according to an embodiment of the invention;
Fig. 6 is that multi-path video data splices schematic diagram according to an embodiment of the invention.
Embodiment
In order to solve the problem that prior art multi-picture splicing technology real-time is poor, can not process too much video way, solved further the problem of lack of memory capacity.The invention provides a kind of multi-picture splicing display device based on digital signal processor.
Digital signal processor (Digital Signal Processor, DSP) is a kind of processor calculating towards density data that is specifically designed to image processing, Video processing.DSP has real-time processing and capacity the feature such as can expand, and utilizes the advantage of DSP in image/video is processed, and by multi-DSP, is realized the processing of multi-path video data and splicing are had to high performance advantage.
Below in conjunction with accompanying drawing and embodiment, the present invention is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, does not limit the present invention.
As shown in Figure 1, Fig. 1 is the structural representation of the multi-picture splicing display device based on digital signal processor according to an embodiment of the invention.
This equipment can comprise network interface data transmission module 101, video decode module 102, DSP core processing module 103, video encoding module 104, power module 105, external memory modules 106, local management module (Local Management Processor, LMP) 107, clock module 108, memory cell 109, display (not shown) etc.
Network interface data transmission module 101 can be for receiving single channel video data and the multi-path video data of the transmission of optical fiber multiplex networks by network interface, and by multi-path video data demultiplexing, and for the video data transmitting that 103 splicings are processed through DSP core processing module is delivered to network.Wherein, multi-path video data demultiplexing is referred to by multi-path video data demultiplexing be a plurality of single channel video datas, and the single channel video data transmitting after the single channel video data of reception and demultiplexing is delivered to video decode module 102.Concrete, the ethernet transceiver part that can comprise by network interface changes into ethernet frame data the bit stream of the networked physics layer receiving on network, so, the corresponding video source of each single channel video data, each single channel video data comprises one or more single frames video datas, and each single frames video data comprises the video source information under it.This video source can comprise: video camera, computer, television set, network etc.
DSP core processing module 103 can comprise one or more pieces DSP, the processing such as every DSP can be for compressing the frame video data in the single channel video data by 102 decodings of video decode module, splicing, and compression, spliced video data transmitting are delivered to video encoding module 104 processing of encoding.
Display can be for showing multi-path video data.
In conjunction with Fig. 2-Fig. 6, the function of the modules in Fig. 1 and the present invention are elaborated.
As shown in Figure 2, Fig. 2 is the workflow diagram of the multi-picture splicing display device based on digital signal processor according to an embodiment of the invention.
Step S201, receives the video data that multiplex fibre optic network transmits, and is a plurality of single channel video datas by multi-path video data.Wherein, the corresponding video source of each single channel video data, and each single channel video data comprises one or more single frames video datas.
Particularly, each video source can be by multiplex fibre optic networking to the one or more video data streams of network interface data transmission module 101 transmission, network interface data transmission module 101 can be resolved one or more video data streams by resolving procotol, and each video data stream after parsing can comprise single channel video data and/or multi-path video data.Resolving procotol is for example transmission control protocol/Internet Interconnection agreement (Transmission Control Protocol/Internet Protocol, TCTIP), User Datagram Protocol (User Datagram Protocol, UDP) etc.By network interface data transmission module 101, will receive multi-path video data demultiplexing is a plurality of single channel video datas, and single channel video data is changed into one or more single frames video datas.Wherein, the video source of multi-path video data is identical, and before demultiplexing not, this multi-path video data is by Same Physical medium transmission.For example cable television line only has one, but can transmit multi-channel TV signals simultaneously, and source is all to broadcast node.Network interface data transmission module 101 by the one or more single frames structured video data transmittings (output) in single channel video data to video decode module 102.
For example: as shown in Figure 3, Fig. 3 is the structural representation of network interface data transmission module according to an embodiment of the invention.Video source 1 by its transmitting terminal 1 by video data 1(single channel video data) encoding forms video data data flow 1, and video data stream 1 is sent to network interface data transmission module 101.Video source 2 is by its transmitting terminal 2, by video data 2 to video data m(m > 2) encoding after being combined with each other forms video data stream 2(multi-path video data), and this video data stream 2 is sent to network interface data transmission module 101.Network interface data transmission module 101 receiving video data stream 1 and video data streams 2, by resolving procotol, video data stream 1 and video data stream 2 are resolved, obtain the valid data in video data stream 1, it is video data 1, obtain the valid data in video data stream 2, be video data 2 to video data m, this video data 2 is the video data mixing to video data m.Video data multichannel being mixed by demultiplexing is separated into a plurality of single channel video datas, that is to say the video data mixing 2 is carried out to separation to video data m.Video data 1 can directly be done output without demultiplexing and process, and video data 2 can be done output processing after video data m needs demultiplexing.
Step S202, decodes to single channel video data, that is to say each the single frames video data in single channel video data is decoded.
Particularly, video decode module 102 can be decoded each single channel video data.Decoded video data can be the digital video frequency flow with reference format, for example, be the standard digital video flowing of BT.656YUV4:2:2.The DSP that these decoding rear video data can offer in DSP core processing module 103 processes.
Step S203, according to schedule information, every DSP compresses and splices decoded video data.
As shown in Figure 4, be the structural representation of DSP according to an embodiment of the invention.
DSP inner integrated Ethernet medium access controller (EMAC) 402, video port 403, external memory storage expansion interface (EMIFA) 404.
Wherein, EMAC controller 402 is connected with network interface 407, can be for being responsible for transmitting-receiving and the control of Ethernet net frame, and EMAC controller 402 can receive the network data being packaged into according to network standard 802.3.This network interface 407 can be DSP external network interface, and the network data that EMAC controller 402 receives can be the schedule information that local management module 107 sends.
The structural representation of Ethernet medium access controller 402 as shown in Figure 5.EMAC controller 402 can comprise EMAC control unit, I/O management unit (MDIO) and EMAC unit.EMAC control unit can be for controlling MDIO unit and EMAC unit, such as the unlatching of unit, close etc.EMAC unit provides Media Independent Interface (MII bus), can be connected and transmit network data with the ethernet network transceiver (physical layer device) in network interface 407.MDIO unit provides MDIO bus interface (MDIO bus) can control the state of this ethernet transceiver part of configuration and monitoring of the ethernet transceiver part in network interface 407.
64 of the data-bus widths of external memory storage expansion interface (EMIFA) 404 can be divided into 4 memory cell, and the size in each space is 256MB.The expansion of EMIFA interface 404 of the present invention comprises external memory modules 106, in this external memory modules 106, comprises synchronous DRAM SDRAM expansion 406 and program storage FLASH expansion 405.Wherein, synchronous DRAM SDRAM expansion 406 is the expansions to DSP internal memory, for the storage to the jumbo vedio data of multichannel.Program storage FLASH expansion 405 is for stored program operation code, the program storage that data power down does not disappear, this program storage FLASH expansion 405 has that storage data are quick, capacity large, power down not obliterated data, online programmable, have the abundant advantages such as erasing times.
DSP based on having said structure can process concurrently multi-path video data in one or more pieces DSP.In order to reduce multi-DSP while processing video data, easily cause data collision problem, the present invention introduces local management module 107 as the task dispatcher between multi-DSP, to different DSP allocating tasks, to prevent the conflict between multi-DSP.For example, adopt load-balancing technique, make every DSP process corresponding one or more video data, and the processing quantity of every DSP is even.Local management module 107 can also be distributed reading with write operation of DSP by task, with the generation of avoiding a conflict.For example: can make one or more pieces DSP read-writes synchronous, the mistake screen phenomenon occurring to prevent multi-DSP from reading while write same memory headroom.The task generation that local management module 107 can be worked as pre-treatment according to one or more pieces DSP is for the schedule information of each DSP and to each DSP transmission.In addition, synchronous for what guarantee that multi-DSP and local management module 107 can be in time, therefore, on the clock of multi-DSP and local management module 107, introduce clock module 108, to guarantee the unification of clock signal, also guaranteed the succession that task is distributed and carried out.
According to foregoing, the step of decoded video data being processed and being spliced for every DSP, particularly, video decode module 102 offers each DSP by decoded one or more single frames video datas, the every schedule information that DSP sends according to local management module 107, reads the single frames video data in single channel video data indicated in this schedule information.Further, can in advance the VP0 mouth of video port 403 and VP2 mouth be configured to single frames video data input port, can realize monolithic DSP parallel processing multi-path video data.And the single frames video data reading is placed in to data fifo buffering area 401 by sub-video mouth VP0, VP2.Further, two single frames video data input ports can receive respectively 2 road single frames video datas, and according to first-in first-out rule by the single frames Video Data Storage receiving in FIFP data buffer zone 401.VP0 mouth can be responsible for receiving 2 road single frames video datas, and VP2 mouth can be responsible for receiving other 2 road single frames video datas.And according to the rule of first in first out, by the brightness signal Y of single frames video data, blue difference signal Cb and red color difference signal Cr, be automatically assigned to the buffering area separately in fifo buffer 401, to facilitate the further processing of DSP core.Wherein, the relation that brightness signal Y, blue difference signal Cb and red color difference signal Cr three's sampling ratio is 4:2:2.
According to first-in first-out rule, EDMA controller 402 is sent to each the single frames video data in data fifo buffering area 401 in corresponding external memory modules, so as DSP to the single frames video data in external memory modules compress, concatenation.Particularly, EDMA controller 402 is continuous by the brightness signal Y of each the single frames video data in fifo buffer 401, blue difference signal Cb and red color difference signal Cr, and is sent in synchronous DRAM SDRAM expansion 406.DSP compresses the single frames video data of synchronous DRAM SDRAM expansion 406, splice, to realize many picture displies multi-path video data.Compression method can comprise: run length encoding, entropy coding etc.
As shown in Figure 6, be that multi-path video data splices schematic diagram according to an embodiment of the invention.
Particularly, in advance the shared memory cell 109 of one or more pieces DSP is divided into one or more memory blocks, as, memory block 1, memory block 2, memory block 3 ..., memory block n(n > 0), and the memory space of each memory block can equate.For each memory block distribution network address, between the network address of each memory block and the network address of a video source, corresponding relation is set, make the corresponding video source in each network address, there is one-to-one relationship in memory block and video source.In addition, multi-picture splicing display device of the present invention, can also comprise a display, and display comprises one or more viewing areas, for the good multi-path video data of display splicing.Set in advance virtual video-splicing region, this video-splicing region can be corresponding with display.Video-splicing region is divided into several video source sub-blocks, sub-block 1, sub-block 2, sub-block 3 in Fig. 6 ..., sub-block n.A sub-block is corresponding with a memory block, that is to say, a viewing area in a corresponding display of memory block, to be used for showing the video data of a video source, like this video data of each sub-block is stitched together, shows the video data of a plurality of video source.
DSP determines the video source under the single frames video data in synchronous DRAM SDRAM expansion 406.For example, single frames video data has the identical network address with affiliated video source, searches the video source with single frames video data with same network address, and then determines the video source under this single frames video data.DSP adopts the mode of single frames video data being carried out to convergent-divergent, by the single frames video data compression of different resolution, is target image.Target image in each memory block has identical resolution.For target image, DSP writes each target image in the affiliated corresponding memory block of video source of this target image (single frames video data).Thereby completed the compression of multi-path video data and splicing.
Step S204: will compress, spliced coding video data, and export to display and carry out many picture displies.
Video encoding module is encoded respectively, and each stores the single frames video data after fast middle compression, and exports to display, with multi-path video data described in Concurrent Display in one or more viewing areas of correspondence.
Particularly, DSP reads respectively target image from each memory block of memory cell 109, and the single frames video data after compression, exports to video encoding module 104, target image is encoded to the video data can multi-path video data together showing.More specifically, particularly, can, using the VP1 mouth in video port 403 as video output, by VP1 mouth, export target image to video encoding module 104 and encode.This coding is for example: by the video data recompile of BT.656 form, be extended formatting.In cataloged procedure, the target image from same memory block is encoded to video data, and in the video data after this coding, can comprises its position in video-splicing region, i.e. residing sub-block.Video encoding module 104 is exported to display by the network interface of network interface data transmission module 101 by the video data after coding, to show in real time multi-path video data in display.
The above, be only a kind of conceptual design of the present invention, is not intended to limit protection scope of the present invention, all any modifications of making within the spirit and principles in the present invention, is equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Although be example object, the preferred embodiments of the present invention are disclosed, it is also possible those skilled in the art will recognize various improvement, increase and replacement, therefore, scope of the present invention should be not limited to above-described embodiment.
Claims (5)
1. the multi-picture splicing display device based on digital signal processor, it is characterized in that, described equipment comprises: network interface data transmission module, video decode module, local management module, one or more pieces digital signal processors, video encoding module, display; Wherein:
Network interface data transmission module will receive a plurality of single channel video datas of multi-path video data demultiplexing, and described a plurality of single channel video data transmittings of the one or more single channel video datas that receive and demultiplexing are delivered to video decode module; Wherein, the corresponding video source of single channel video data described in each, described single channel video data comprises one or more single frames video datas;
Video decode module is decoded to each single frames video data;
Local management module generates schedule information according to every digital signal processor when single frames the video data volume of pre-treatment, to control every digital signal processor, reads single frames video data indicated in described schedule information;
Every described digital signal processor compresses the described single frames video data reading, and by compression after single frames Video Data Storage in corresponding memory block; Wherein, there is one-to-one relationship in described memory block and video source, and a viewing area in the corresponding display of each memory block;
Every described digital signal processor reads respectively the single frames video data after compression in each memory block, and exports to video encoding module;
Described video encoding module is encoded respectively, and each stores the single frames video data after fast middle compression, and exports to display, with multi-path video data described in Concurrent Display in one or more viewing areas of correspondence.
2. equipment as claimed in claim 1, is characterized in that, also comprises:
In advance the shared memory cell of described one or more pieces digital signal processors is divided into one or more memory blocks;
For each memory block distribution network address;
Between the network address of described each memory block and the network address of a video source, corresponding relation is set, to realize the corresponding one by one of memory block and video source.
3. equipment as claimed in claim 1 or 2, is characterized in that, also comprises: every digital signal processor is connected with external memory modules.
4. equipment as claimed in claim 3, is characterized in that:
Described every digital signal processor comprises single frames video data input port and First Input First Output data buffer zone;
Described input port receives single frames video data, and according to first-in first-out rule by the single frames Video Data Storage receiving in First Input First Output data buffer zone.
5. equipment as claimed in claim 4, is characterized in that: described every digital signal processor also comprises Ethernet medium access controller, wherein:
Ethernet medium access controller is sent to each the single frames video data in First Input First Output data buffer zone in corresponding external memory modules, so as digital signal processor to the single frames video data in described external memory modules compress, concatenation.
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