CN101282477A

CN101282477A - Method and system for processing multicore DSP array medium based on RapidIO interconnection

Info

Publication number: CN101282477A
Application number: CN 200810025491
Authority: CN
Inventors: 虞水中; 吴涛
Original assignee: AVONACO COMMUNICATION SYSTEMS (SUZHOU) Co Ltd
Current assignee: AVONACO COMMUNICATION SYSTEMS (SUZHOU) Co Ltd
Priority date: 2008-05-06
Filing date: 2008-05-06
Publication date: 2008-10-08

Abstract

The invention relates to a multi-core DSP array media processing system based on RapidIO interconnection and method thereof. Three more multi-core DSP are serially interconnected by RapidIO and are packaged inside a chip, communications between the cores are realized by employing high-speed bus and shared memory; the media processing method is: transmitting high-definition media processing streams respectively to multiple DSP high-definition decoders for decoding; transmitting the result to another multi-core DSP image synthesizer through RapidIO, and inputting the processed signal to the multi-core DSP high-definition encoders for encoding. RapidIO switching technology is employed by the invention, which can respectively provide a low-delay data switching path with maximum transmission speed of 10Gbps between each DSP chip, which ensures feasibility of pipeline processing and greatly improves processing density for a signal DSP, which can real-time distribute processing task effectively according to processing load of each DSP kernel.

Description

Based on RapidIO interconnected system for processing multicore DSP array medium and method thereof

Technical field

The present invention relates to the method for scheduling task in a kind of multi-nuclear DSP system, particularly a kind of based on RapidIO interconnected system for processing multicore DSP array medium and method thereof.

Background technology

Multimedia is handled (as H.263, MPEG-4, H.264 encoding and decoding transcoding) all relate to all very complex mathematical computings, need expend a large amount of processing resources, for example: H.264 the coding computing of real-time per second 30 frames of CIF (352x288 pixel) form need expend the above universal cpu calculation resources of 1000Mhz, the CPU of at present the fastest Intel P4 4GHz also can only support 4～5 the tunnel, and the fastest monokaryon DSP also can only support 7～8 the tunnel.Traditional single monokaryon DSP can't handle the video of high definition (HD Full HD).Handle in order to satisfy a large amount of parallel datas, DSP can realize many dsp bus interconnection by pci bus interface by the PCI bridge, shares resource each other, makes between the DSP and can directly carry out exchanges data.The subject matter that universal bus structure exists is: when there was a plurality of equipment in system bus, each equipment shared bus bandwidth need take bus by the arbitration timesharing, causes the spendable bus bandwidth deficiency of each equipment.Because development of semiconductor has suffered from technical bottleneck, the dominant frequency that improves chip merely is no longer feasible, all moves at the framework to polycaryon processor from the universal cpu to DSP.Some complex calculations needs many multi-core DSPs to handle, RapidIO is a kind of high speed, packet switch formula point-to-point protocol, have predictable low delay character, be very suitable in video code conversion, industrial imaging, media gateway, wireless base station and other have the application of strict demand to bandwidth and low time delay, being connected extendible a plurality of DSP.At present, RapidIO is in the application of the high-definition multimedia process field further development and application that awaits.

Summary of the invention

In order to overcome the deficiency that prior art exists, the invention provides a kind of dynamic task distribution of multi-core DSP and the medium processing system and the method thereof of scheduling.

In order to reach the foregoing invention purpose, the technical scheme that the present invention takes provides a kind of based on the interconnected multicore DSP array multimedia processing system of RapidIO, its characteristics are: it is interconnected with the multi-core DSP serial more than 3 by RapidIO, be encapsulated in a chip internal, the communication between its nuclear adopts high-speed bus and shared drive to realize; Described serial interlinkage form is a kind of in stelliform connection topology configuration, Mesh topological structure, ring topology or the point-to-point topological structure or their combination; Described multi-core DSP, wherein, 1 is the high definition encoder, and 1 is the picture fusion device, and all the other are the high definition decoder.

It is a kind of based on the interconnected multicore DSP array multi-media processing method of RapidIO that technical solution of the present invention also provides, and its characteristics are that step is as follows:

(1) high definition media being handled flow point does not send to a plurality of multi-core DSP high definition decoders and carries out decoding processing;

(2) above-mentioned result is transferred in other 1 multi-core DSP picture fusion device by RapidIO carries out the picture fusion treatment;

(3) signal after will handling is again sent in the multi-core DSP high definition encoder and is carried out encoding process.

The present invention has used leading RapidIO switching technology, and the low delay exchanges data path of the highest 10Gbps can be provided respectively between each dsp chip, has guaranteed the feasibility that pipeline system is handled.Simultaneously, because only bearing, each dsp chip of the present invention handles a certain function, greatly improve the processing density of single dsp chip, the dynamic task of multi-core DSP distributes and dispatching method, can be efficiently according to the real-time allocation process task of the processing load of each DSP kernel.

Description of drawings

Fig. 1 is that the embodiment of the invention is based on the interconnected DSP stelliform connection topology configuration schematic diagram of RapidIO;

Fig. 2 is the workflow diagram of multi-media processing method;

Fig. 3 is that the embodiment of the invention is based on the interconnected DSP Mesh topological structure schematic diagram of RapidIO;

Fig. 4 is that the embodiment of the invention is based on the interconnected DSP ring topology schematic diagram of RapidIO;

Fig. 5 is that the embodiment of the invention is based on the interconnected DSP point-to-point topological structure schematic diagram of RapidIO.

Embodiment

Below in conjunction with drawings and Examples the present invention is further described:

Embodiment 1:

Referring to accompanying drawing 1, it is that present embodiment is based on the interconnected multi-core DSP stelliform connection topology configuration schematic diagram of RapidIO; 5 multi-core DSPs are star-like connection by RapidIO Switch, and in the multi-core DSP, 1 is the high definition encoder, and 1 is the picture fusion device, and 3 is the high definition decoder.Present embodiment is encapsulated in a chip internal with 5 DSP nuclears, communicates by letter with shared drive by high-speed bus between the nuclear.Each DSP nuclear independent operating greatly improves the processing density of single dsp chip on the frequency up to 1GHz, reduce power consumption and area simultaneously.

Handle for complex video, for example: the H.264 coding of 1280x720, single DSP nuclear can not be handled, adopt technical solution of the present invention, these complex video are used the mode that can follow streamline and are handled, each dsp chip is only born and is handled a certain function, for example: video decode or picture are synthetic, a video flowing is made video decode a DSP inside earlier, decoded then data are sent to another DSP, and to make picture synthetic, and the video data after synthetic exchanges to another DSP again and makes encoding process.The processing of pipeline system has reduced the complexity of task scheduling and resource management, but requires that exchanges data path is at a high speed arranged between the dsp chip.

Referring to accompanying drawing 2, it is the workflow diagram of present embodiment multi-media processing method; In the present embodiment, pending task is tripartite high definition conference video bridge, be transported to DSP1, DSP2 respectively and DSP3 high definition decoder carries out decoding processing from three parts's Media Stream, the signal that obtains is transported to DSP4 picture fusion device by RapidIO Switch and carries out the picture fusion treatment, data flow is transported to DSP0 high definition encoder by RapidIO Switch again and carries out encoding process, and the code stream that obtains directly sends to the participant three parts.

The present invention uses the RapidIO switching technology, and the low delay exchanges data path of the highest 10Gbps can be provided respectively between each dsp chip, and the processing that has guaranteed pipeline system is feasible.The RapidIO framework provides a predictable standard for the communication of being undertaken between a plurality of DSP by the point-to-point serial i of a high speed/O network, and it can be configured to multiple different topological form to satisfy the computing requirement.

Referring to accompanying drawing 3, it is to the present invention is based on the interconnected DSP Mesh topological structure schematic diagram of RapidIO; Referring to accompanying drawing 4, it is a DSP ring topology schematic diagram of the present invention; Referring to accompanying drawing 5, it is a DSP point-to-point topological structure schematic diagram of the present invention.In this system for processing multicore DSP array medium interconnected based on RapidIO, the present invention at operating system aspect framework one the cover pipeline system the multinuclear media processing method, dynamically allocation processing task between a plurality of nuclears has reached low delay and load balancing.The dynamic task of multi-core DSP distributes and dispatching method, can be efficiently according to the real-time allocation process task of the processing load of each DSP kernel, avoid occurring the resource " fragment " that the static resource allocation algorithm causes, support the multiple algorithm of single dsp operation, and greatly reduced system delay and shake.

Claims

1. one kind based on the interconnected system for processing multicore DSP array medium of RapidIO, its characteristics are: it is interconnected with the multi-core DSP serial more than 3 by RapidIO, be encapsulated in a chip internal, the communication between its nuclear adopts high-speed bus and shared drive to realize; Described serial interlinkage form is a kind of in stelliform connection topology configuration, Mesh topological structure, ring topology or the point-to-point topological structure or their combination; Described multi-core DSP, wherein, 1 is the high definition encoder, and 1 is the picture fusion device, and all the other are the high definition decoder.

2. one kind based on the interconnected multicore DSP array multi-media processing method of RapidIO, and its characteristics are that step is as follows: