CN209517357U - A kind of real-time video bidirectional transmission system - Google Patents

Abstract

The utility model discloses a kind of real-time video bidirectional transmission systems, comprising: high-definition camera, zynq chip, DDR3 memory chip, Ethernet card and ultra-high definition displays for network transmission；The high-definition camera is connect with the zynq chip, and the zynq chip is bi-directionally connected DDR3 memory chip and Ethernet card, and the ultra-high definition displays and the zynq chip are bi-directionally connected；Encapsulation H.264IP core encoder and H.264IP core decoder in the zynq chip, the H.264IP core encoder with the DDR3 memory chip is two-way is connected, the H.264IP core decoder is bi-directionally connected with the ultra-high definition displays.The utility model structure is simple, and system bulk is smaller, and significantly reduces the design difficulty of hardware, eliminate conventional architectures chip-scale interconnect brought by system bandwidth bottleneck, the design of User IP and it is integrated also simpler and more direct flexibly, it is versatile.

Description

A kind of real-time video bidirectional transmission system

Technical field

The utility model relates to real-time video transmission fields, and in particular to a kind of real-time video bidirectional transmission system.

Background technique

In field of video transmission, the huge video of data flow is treated as an outstanding problem.In image frame per second and resolution Rate requires relatively high occasion, and high performance digital signal processing chip (DSP), which is used only, can not obtain satisfactory effect. FPGA due to parallel data processing itself characteristic, it is very advantageous when handling mass data, in addition FPGA internal junction Structure is flexible, is suitable for modularized design, therefore do video using FPGA and be processed into for very universal scheme.

It when FPGA is handled for video, is not often used alone, general one central processing unit (CPU) of configuration carries out task Scheduling.Design for such dual chip, the area of pcb board, design difficulty, power consumption will improve, and cost also will increase, and Also bandwidth limitation is had between CPU and FPGA；The occasion more demanding for some pairs of power consumptions and size, this combination are simultaneously uncomfortable With.

Utility model content

Purpose of utility model: for overcome the deficiencies in the prior art, the utility model provides a kind of two-way biography of real-time video Defeated system, the system can solve that the high latency of Video transmission system, structure is complicated, bulky, conventional architectures chip-scale is mutual The problem of system bandwidth bottleneck brought by even and flexibility difference.

Technical solution: real-time video bidirectional transmission system described in the utility model, the system include: high-definition camera, Zynq chip, DDR3 memory chip, Ethernet card and ultra-high definition displays for network transmission；The high-definition camera with The zynq chip connection, the zynq chip are bi-directionally connected DDR3 memory chip and Ethernet card, the ultra-high definition displays It is bi-directionally connected with the zynq chip；H.264IP core encoder and H.264IP core decoder, institute are encapsulated in the zynq chip State H.264IP core encoder with the DDR3 memory chip is two-way is connected, the H.264IP core decoder input with it is described DDR3 memory chip is bi-directionally connected, and output end is bi-directionally connected with the ultra-high definition displays.

Preferably, the zynq chip further includes Video in AXI4-Stream IP kernel, is taken the photograph with the high definition Picture head is connected, and for the video flowing acquired from the high-definition camera to be converted to AXI4-Stream stream, and video stream data is logical It crosses VDMA and is transferred to the DDR3 memory chip.

Preferably, the zynq chip further includes OSD IP kernel and AXI4-Stream to Video Out IP kernel, described OSD IP kernel receives the video flowing extracted from the DDR3 memory chip, and video flowing is output to AXI4-Stream to Video Out IP kernel, the AXI4-Stream to Video Out IP kernel is by video stream into ultra-high definition displays.

Preferably, the H.264IP core encoder and the DDR3 memory chip use rtsp real-time streaming protocol to carry out net Network transmission.

Preferably, the ultra-high definition displays are connect using LVDS interface with the zynq chip.

Preferably, the also external FLASH chip of the zynq chip.

The utility model has the advantages that the utility model provides a kind of realization high-performance, the Video transmission system of low latency, structure letter Single, system bulk is smaller, and significantly reduces the design difficulty of hardware, eliminates brought by the interconnection of conventional architectures chip-scale System bandwidth bottleneck, the design of User IP and it is integrated also simpler and more direct flexibly, it is versatile.

Detailed description of the invention

Fig. 1 is the structural schematic diagram of system described in the utility model；

Fig. 2 is another structural schematic diagram of system described in the utility model；

Fig. 3 is the structural schematic diagram of zynq chip described in the utility model；

Fig. 4 be system described in the utility model as transmitting terminal when structural schematic diagram；

Fig. 5 be system described in the utility model as transmitting terminal when, the processing stream block diagram of display portion；

Fig. 6 be system described in the utility model as receiving end when, reception camera data processing block diagram.

Specific embodiment

H.264IP core intraframe coding allow H.264IP core encoder 11 realize frame frequency delay, macroblock pipelined architecture design Then further decrease about 0.3 millisecond of delay.The pipeline design supports each clock to handle eight pixels, realizes real-time 4K@60fps Video coding.

H.264IP core encoder supports that H.264 Hi422 format configures, unique in 5.1 standards (3840x2160p30) frame Coding.Support this expression of 10 digital video streams brings see to be not in gray scale and color degradation phenomenon from video item.Support YUV4:2: 2 video flowings are meant to realize that better color divides, particularly with red it is obvious that this is more clear image.

H.264 decoder supports that H.264 Hi422 format configures, unique encodings in 5.1 standards (3840x2160p30) frame. 10 digital video stream encryptions are equally supported with encoder, i.e., bring from video item and see to be not in gray scale or color degradation phenomenon. Decoder also supports YUV4:2:2 video format, supports intraframe decoder, realizes that the frame per second of decoder postpones using pipelined architecture.

As shown in Figure 1, the utility model provides real-time video bidirectional transmission system, which can work as video receiver, Transmitting terminal can also be worked as.When system is as receiving end, transmitting terminal can be PC machine, receive the view transmitted from Ethernet card Frequency evidence, is output on display screen by display, when system is as transmitting terminal, system acquisition camera data, by with Too net is sent to receiving end.

Specific as follows: system includes that high-definition camera 2, zynq chip 1, DDR3 memory chip 3, preferably capacity are all the way 1GB, Ethernet card 4 and ultra-high definition displays 5 for network transmission；Network transmission uses Ethernet card, compared with wifi, Ethernet network transmission is more stable, and high-definition camera 2 is connect with zynq chip 1, the external DDR3 memory chip 3 of zynq chip 1 With Ethernet card 4, and can two-way communication, the ultra-high definition displays 5 and the zynq chip 1 use the two-way company of LVDS interface It connects.

As shown in Fig. 2, in one of the embodiments, the also external FLASH chip 6 of zynq chip and USB interface 7 and SATA interface 8.

Wherein, zynq chip 1 is main control chip, and Zynq runs linux operating system, and Qt operation interface, inside is by two It is grouped as: PL (Program Logic) and PS (Program System).PS includes a double-core Cortex A9 processor, PL Side is FPGA resource, and the utility model encapsulates H.264IP core encoder 11 in the zynq chip 1 and H.264IP core decodes Device 12, the H.264IP core encoder 11 with the DDR3 memory chip 3 is two-way is connected, H.264IP 12 one end of core decoder with DDR3 memory chip 3 is two-way to be connected, and the other end is bi-directionally connected with the ultra-high definition displays 5.H.264IP core encoder 11 only makes It is that other must electricity with the programmable logic and DSP resource of Zynq Z-7045 SoC 78% and 55% available RAM Enough spaces are reserved in road.

In the utility model, received video data is transmitted using Ethernet and all uses H.264 encoding and decoding, to reduce transmission Data volume；H.264IP the core encoder 11 carries out network transmission using rtsp real-time streaming protocol with DDR3 memory chip 3. The network transmission protocol uses rtsp agreement.Video data is packaged into standard RTP data packet according to Real-time Transport Protocol rule, is then made It is interacted with RTSP agreement with receiving end, sends receiving end for RTP packet, receiving end plays the video data received.

H.264 it encodes and H.264 encodes IP kernel using dedicated, H.264 IP kernel can support 1080p@30fps video to compile Decoding.Cooperate rtsp real-time streaming protocol, end-to-end delay can be made to be reduced to 10ms.

As shown in figure 3, zynq chip 1 further includes Video in AXI4-Stream in one of the embodiments, IP kernel 13, high-definition camera 2 are linked into zynq chip 1 by rgb interface, and video flowing first accesses Video in AXI4- Stream IP kernel 13 is handled to be input to VDMA after AXI4-Stream stream, and AXI4-stream stream is input in DDR3 by VDMA Chip is deposited, and carries out the processing of next step.

Video flowing is input in DDR3 memory chip, and after H.264 IP kernel encoder 11 coding through rtsp agreement It is sent to receiving end, which is H.264 IP kernel decoder 12 and superb clear display 5.

As shown in figure 4, zynq chip 1 further includes OSD IP kernel 17 and AXI4-Stream to Video as transmitting terminal Out IP kernel 18, the OSD IP kernel 17 receives the video flowing for extracting by VDMA and being stored in memory, and video flowing is output to AXI4-Stream to Video Out IP kernel 18, the AXI4-Stream to Video Out IP kernel 18 send out video flowing It is sent in ultra-high definition displays 5.The display of superb clear display 5 realizes that the LVDS interface uses AXI4- using LVDS interface Stream to Video Out IP kernel 18 is realized.

As Fig. 5 be display portion processing stream block diagram, AXI-VDMA by AXI-Memory-to-Stream bus with it is interior Connection is deposited, VDMA reads data from memory, and converts AXI-stream stream for internal storage data and be then communicated to osd IP kernel, AXI-stream stream is input to AXI4-stream to video out and shown by OSD IP kernel.Vdma, osd IP kernel, It between axi4-stream to video out is connected by axi-stream bus.

Axi_dynclkIP core is dynamic clock IP kernel, provides clock for video timing Controler IP kernel, Video timing Controler IP kernel generates the video timing that display needs.

When as receiving end, the data sent by Ethernet are received, by inputting after the parsing of H.264IP core decoder To superb clear display.If Fig. 6 is the processing block diagram for receiving camera data.Video in AXI-stream is by input Camera data are converted to axi-stream and are input to vdma, and axi-stream circulation is changed to internal storage data and transmitted by vdma To memory, vdma here passes through axi-stream-to-memory bus and Memory linkage.

The utility model can not only meet the performance of video processing using heterogeneous chip piece, but also be able to satisfy demand for control.Structure Simply, system bulk is smaller, and flexible design is convenient, and versatility is good.High-performance, the transmission of video effect of low latency.

Claims (6)

1. a kind of real-time video bidirectional transmission system, which is characterized in that the system includes: high-definition camera, zynq chip, DDR3 Memory chip, Ethernet card and ultra-high definition displays for network transmission；The high-definition camera and the zynq chip Connection, the zynq chip are bi-directionally connected DDR3 memory chip and Ethernet card, the ultra-high definition displays and the zynq core Piece connection；H.264IP core encoder and H.264IP core decoder, the H.264IP core encoder are encapsulated in the zynq chip With the DDR3 memory chip is two-way is connected, the H.264IP core decoder input and the two-way company of DDR3 memory chip It connects, output end is bi-directionally connected with the ultra-high definition displays.

2. real-time video bidirectional transmission system according to claim 1, which is characterized in that the zynq chip further includes Video in AXI4-Stream IP kernel, is connected with the high-definition camera, for that will adopt from the high-definition camera The video flowing of collection is converted to AXI4-Stream stream, and video stream data is transferred to the DDR3 memory chip by VDMA.

3. real-time video bidirectional transmission system according to claim 1, which is characterized in that the zynq chip further includes OSD IP kernel and AXI4-Stream to Video Out IP kernel, the OSD IP kernel are received from the DDR3 memory chip The video flowing of extraction, and video flowing is output to AXI4-Stream to Video Out IP kernel, the AXI4-Stream to Video Out IP kernel is by video stream into ultra-high definition displays.

4. real-time video bidirectional transmission system according to claim 1, which is characterized in that the H.264IP core encoder Network transmission is carried out using rtsp real-time streaming protocol with the DDR3 memory chip.

5. real-time video bidirectional transmission system according to claim 1, which is characterized in that the ultra-high definition displays use LVDS interface is connect with the zynq chip.

6. real-time video bidirectional transmission system according to claim 1, which is characterized in that the zynq chip is also external FLASH chip.