CN107360380A - A kind of double Compression camera devices and its host computer decoding apparatus - Google Patents
A kind of double Compression camera devices and its host computer decoding apparatus Download PDFInfo
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- CN107360380A CN107360380A CN201710507730.4A CN201710507730A CN107360380A CN 107360380 A CN107360380 A CN 107360380A CN 201710507730 A CN201710507730 A CN 201710507730A CN 107360380 A CN107360380 A CN 107360380A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/18—Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/439—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using cascaded computational arrangements for performing a single operation, e.g. filtering
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/70—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/2628—Alteration of picture size, shape, position or orientation, e.g. zooming, rotation, rolling, perspective, translation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/268—Signal distribution or switching
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
- H04N5/77—Interface circuits between an apparatus for recording and another apparatus between a recording apparatus and a television camera
Abstract
The present invention proposes a kind of double Compression camera devices and its host computer decoding apparatus, working stability, on the premise of transmission bandwidth is not improved, can collect high definition pictorial information, greatly improves on aircraft load to the observation effect of common-denominator target.This pair of Compression camera device adds ARM serial structure using FPGA；Wherein the HD video received is divided into two-way by image conduit interface module IPIPEIF, is sent into image size adjustment module RZA all the way and is adjusted video size to SD form, then SD video is sent into compression core progress video data and H.264 compressed；Another way is sent into picture signal interface module ISIF, and is ultimately delivered to compression core and carries out image data JPEG compression；Image data after JPEG compression is divided into multiple data blocks, and a data block is embedded between adjacent two frames video data；The serial data for including image data and video data is sent to FPGA by SPI interface.
Description
Technical field：
The invention belongs to image information technical field, is related to a kind of double Compression camera devices and its host computer decoding dress
Put, more particularly to the improvement to IMAQ Compression Transmission Technology.
Background technology：
With the continuous development of China's Aero-Space cause, the demand of China's effective monitoring load on board the aircraft at present
Increasing simultaneously.Due to being limited by transmission bandwidth and compression algorithm, monitor camera device uses more on China's aircraft
720x576 resolution ratio, video data is compressed according to no more than 500kbps compression bit rates, to observe key position work
Make state；Due to limited in bandwidth, to transmit to earth station the image for carrying out decompressing display again after 500kbps Compressions
It is ineffective, it is difficult to meet that observation requires.Therefore how how to meet that observation requires to turn into the case where not improving bandwidth to fly
Row device monitor camera device solves the problems, such as emphatically.
By inquiring about the data of literatures of other field, patent document CN 102387348A " are applied to intelligent transportation
Dual code stream high definition camera " discloses a kind of dual code stream compression set, and the device adds DSP parallel processing structure using ARM, proposes
HD video and high definition picture are compressed simultaneously.But data volume is larger after program compression, can not meet in aerospace field
The smaller requirement of bandwidth, while the program can not be adjusted to compression video and the compression bit rate of picture, resolution ratio, flexibility
Not enough, actual requirement of engineering can not be met.Moreover, although parallel processing speeds are fast, structure is not sufficiently stable, and number easily occurs
According to the loss during collect and process, error code is caused to occur.
The content of the invention：
The present invention proposes a kind of double Compression camera devices and its host computer decoding apparatus, working stability, is not improving
On the premise of transmission bandwidth, high definition pictorial information can be collected, greatly improves sight of the load to common-denominator target on aircraft
Survey effect.
The solution of the present invention is as follows：
This pair of Compression camera device includes video acquisition module and video compressing module, using FPGA plus ARM string
Row structure；The video acquisition module is based on FPGA, gathers vision signal and is converted to HD video, is sent into video compress mould
Block；The video compressing module includes image conduit interface module IPIPEIF, image size adjustment module RZA and picture signal
Interface module ISIF；The HD video received is divided into two-way by image conduit interface module IPIPEIF, is sent into image tube all the way
Road IPIPE image size adjustment module RZA adjusts video size to SD form, then SD video feeding compression core is entered
H.264, row video data compresses；Another way is sent into picture signal interface module ISIF, and is ultimately delivered to compression core and carries out picture number
According to JPEG compression；Image data after JPEG compression is divided into multiple data blocks, and an institute is embedded between adjacent two frames video data
State data block；The serial data for including image data and video data is sent to FPGA, FPGA by SPI interface and presses 422
Interface rear end data integrator sends data, and is sent by antenna to ground data receiving device.
Based on above scheme, the present invention has also further made following optimization：
In the serial data, the image data after video data and compression after compression is end to end respectively added with mark
Position.
The video compressing module uses TI DM368 type products.
The FPGA is communicated by GPIO interface with video compressing module.
The video acquisition module is to change the video signal format of collection to BT.1120 HD video agreements, according to
1080P@25HZ videos are sent into video compressing module by BT.1120 HD videos agreement；Described image size adjustment module RZA is
Video size is adjusted to 720x576, then 720x576@25HZ videos are sent into compression core progress video data and H.264 compressed.
The each data block split out by the image data after the JPEG compression is 1KB sizes.
Corresponding to the host computer decoding apparatus of above-mentioned double Compression camera devices, including data reorganization module and decoding mould
Block, after data reorganization module receives the serial data of compression, according to zone bit information, image data is chosen from video data
Go out and recombinate, decoder module will choose and recombinate obtained video compression data and picture compression data, and to carry out decoding respectively aobvious
Show.
The present invention has advantages below：
1) ARM serial structure is added using FPGA, Stability Analysis of Structures, is not in asking of being lost in data acquisition compression process
Topic, can ensure system steady operation.
2) compressed while using SD video and high definition picture for input video, do not improving the premise of transmission bandwidth
Under, high definition pictorial information can be collected, the significant increase definition of observed object.
3) by by compressed picture deblocking, solving the problems, such as bandwidth deficiency, ensure that data uniform transmission, meeting
Transmission of video requirement.
4) HD video is gathered by DM368, and HD video can be cut randomly and be scaled using RZA modules；
5) FPGA can be communicated by GPIO interface with DM368, the resolution ratio of real time modifying video and picture compression,
Code check, frame frequency.
6) earth station of the present invention can be shown using soft decoding progress real-time decoding.
Brief description of the drawings
Fig. 1 is camera device outline structural diagram.
Fig. 2 is the overall structure diagram of the present invention.
Fig. 3 is operation principle (the i.e. DM368 video sampling and compressing transport stream in Fig. 2 of double Compressions in the present invention
Journey).
Fig. 4 is the flow chart of video acquisition thread in double Compressions.
Fig. 5 is video pictures compression process figure in double Compressions.
Fig. 6 is compressed data output flow chart in double Compressions.
Fig. 7 is video resolution, code check modification process figure.
Fig. 8 is thin-skinned decoding process figure.
Embodiment
By way of example and in conjunction with the accompanying drawings, the implementation of the present invention is described in detail.
Double Compression camera device contour structures as shown in Figure 1, its two pieces of circuit board of internal placement, including power panel
With video compress plate.
As shown in Fig. 2 this pair of Compression camera device device such as including CMOS, FPGA and DM368, for video
Collection and double Compressions, corresponding built-in function can be divided into video data receive capabilities, compression function and transfer function.
FPGA (video acquisition module) is as video acquisition and the video that will be collected with external interface communication chip, FPGA
Data conversion is sent to TI DM368 into BT.1120 forms；TI DM368 (video compressing module) as video input, compression,
The master chip of transmission, it disclosure satisfy that the requirement of the experimental situations such as temperature.
H.264, this pair of Compression camera device is scaled to high definition 1080P videos to be compressed to 720x576,
High definition picture compression is carried out by 1080P (1920x1080) resolution ratio simultaneously, compression algorithm uses JPEG, and picture presses every 125 frame pressure
Contract a frame.Because picture uses JPEG compression, compression efficiency is not high, and the data volume after data compression is larger, by video data and
Image data passes down successively can cause bandwidth to increase to more than 1Mbps suddenly, therefore the present invention is split into image data
Multiple small data blocks, add and transmitted after video data is per frame compressed data, can so ensure transmission bandwidth uniformly without
It can increase suddenly, by the image data of the video after compression by reaching ground installation under data integrator, and by video and figure
Sheet data distinguishes simultaneously decoding display respectively, SD video can observed object motion state, high definition picture can reduce more mesh
Details is marked, greatly improves observation effect.
The operation principle of this pair of Compression camera device is as follows：
1) FPGA gathers CMOS videos, and video format is changed to BT.1120 HD video agreements；
2) DM368 receives 1080P@25HZ videos according to BT.1120 HD videos agreement, and video is sent into image conduit
Interface IPIPEIF modules；
3) HD video received is divided into two-way by IPIPEIF modules, is sent into image conduit IPIPE RZA (figures all the way
As big minor adjustment) for module to video progress size adjusting to 720x576, another way is sent into picture signal interface ISIF modules, and
It is ultimately delivered to compression core and carries out JPEG compression；
4) H.264 RZA modules are compressed 720x576@25HZ videos feeding compression core；
5) image data after JPEG compression is divided into multiple 1KB data blocks, each data block is embedded in per frame video pressure
Contracting data are backmost；
6) picture after compression and video data are sent to FPGA, FPGA by 16MHZ speed by SPI interface and presses 422
Interface rear end data integrator sends data, and is sent by antenna to ground data receiving device；
7) after ground host computer receives video pictures compressed data, according to zone bit information, by image data from video
Choose in data and recombinate, while the video chosen and picture compression data are sent to decoding display respectively.
Mainly the work of each module in DM368 inside is described in detail below：
As shown in figure 3, the compression of dicode rate includes video acquisition thread, video pictures compression thread, compressed bit stream output
Thread.
Video acquisition thread includes video acquisition unit, and video acquisition function receives from FPGA to be transmitted with BT1120 forms
1080P 25HZ videos, video will be received and preserved into buffering area in case encoding thread dispatching.FPGA leads to video data
Cross the IPIPEIF (image conduit interface) that BT1120 interfaces are sent to DM368, be then distributed to ISIF (picture signal interface) and
IPIPE (image conduit) module carries out Data Stream Processing.
The collection of ISIF interfaces is completed to produce ISIF_INTO interrupt signals, the handle in interrupt response function after a two field picture
Video data passes to video compressing module and carries out high definition picture JPEG compression.IPIPE modules have RSZ (the big minor adjustment of image) mould
Block.The data received are carried out the big minor adjustment of image to 720x576 by the module, are then forwarded to compression module and are carried out H.264
Compression, video acquisition thread work flow refer to Fig. 4.
Wherein, the flow of video acquisition task is represented in dotted line, calls AVSERVER_bufGetEmpty first from video
The address that thread obtains storage screen buffer is encoded, DRV_captureStart functions is then recalled and performs video acquisition times
Business, AVSERVER_bufputFull functions are called afterwards, the sky that the video data collected deposit is obtained from coding thread
In not busy buffering area, coding thread can call the data in buffering area to be encoded.
Video compressing module is compressed to 720x576@25HZ SDs videos and high definition picture respectively, and wherein SD regards
Frequency is compressed by code check 500kbps, and high definition picture is compressed by every 100KB size, is opened every 125 frame video compress one
Picture, to ensure not increase transmission bandwidth, image data is carried out splitting into multiple 1KB data blocks, added in video by the present invention
After data are per frame compressed data, can so ensure transmission bandwidth uniformly without increase suddenly, by the video after compression and
Image data under data integrator by reaching ground installation.In the present invention, FPGA is led to DM368 by GPIO interface
Letter, FPGA sends low and high level by GPIO to send instruction to DM368, so as to compression video resolution, code check, frame
The key messages such as frequency are adjusted in real time, so as to meet different compression requirements.
Refering to Fig. 5, Video coding flow is as schemed, the flow of presentation code task, first AVSERVER_ in dotted line
BufGetFull functions obtain the address of storage screen buffer from video acquisition thread, then recall AVSERVER_
BufGetEmpty obtains an empty buffer zone address from coding thread, for depositing the compressed video data after coding, afterwards
Call ALG_vidEncRun functions to perform encoding tasks, AVSERVER_bufputFull functions are called, by the compression after coding
Code stream sends to compressed bit stream and exports thread, while calls AVSERVER_bufPutEmpty functions by an idle buffering area
Coding thread is returned in address, in case coding next time obtains freebuf when performing.
Decoded for convenience of rear end, video compression data video and image data are added into flag bit respectively end to end, and pass through
Data are sent to FPGA, FPGA and send data to data integrator, number by 422 interfaces by transport module by SPI interface
It is to video compression data addition frame head postamble and package according to synthesizer function, is ultimately routed to ground receiving equipment, Fig. 6 is
Compressed bit stream output module flow chart, the interior flow for representing compressed bit stream output task of dotted line, calls AVSERVER_ first
BufGetFull functions obtain the address of storage compressed video data buffering area from Video coding thread, then recall VIDEO_
StreamFileWrite functions send compressed bit stream to FPGA, call AVSERVER_bufPutEmpty functions afterwards by sky
Not busy buffer zone address returns coding thread.
Refering to Fig. 7, FPGA can be sent a command to by host computer, then carry out low and high level by three GPIO interfaces and match somebody with somebody
Put, can compile and be sent for various modes to DM368, according to the agreement set in advance, according to demand, code is carried out in real time to collection video
It is compressed after rate, resolution ratio, the resetting of frame frequency.
Refering to Fig. 8, compressed data choose by the decoding of rear end host computer first carries out group after the subpackage of road by image data
Bag, and deliver to decoder respectively and decoded.
Claims (7)
1. a kind of double Compression camera devices, including video acquisition module and video compressing module, it is characterised in that：Using
FPGA adds ARM serial structure；
The video acquisition module is based on FPGA, gathers vision signal and is converted to HD video, is sent into video compressing module；
The video compressing module includes image conduit interface module IPIPEIF, image size adjustment module RZA and picture signal
Interface module ISIF；The HD video received is divided into two-way by image conduit interface module IPIPEIF, is sent into image tube all the way
Road IPIPE image size adjustment module RZA adjusts video size to SD form, then SD video feeding compression core is entered
H.264, row video data compresses；Another way is sent into picture signal interface module ISIF, and is ultimately delivered to compression core and carries out picture number
According to JPEG compression；Image data after JPEG compression is divided into multiple data blocks, and an institute is embedded between adjacent two frames video data
State data block；The serial data for including image data and video data is sent to FPGA, FPGA by SPI interface and passed through
422 interface rear end data integrators send data, and are sent by antenna to ground data receiving device.
2. double Compression camera devices according to claim 1, it is characterised in that：In the serial data, after compression
Video data and compression after image data be added with flag bit respectively end to end.
3. double Compression camera devices according to claim 1, it is characterised in that：The video compressing module uses TI
DM368 type products.
4. double Compression camera devices according to claim 3, it is characterised in that：The FPGA by GPIO interface with
Video compressing module is communicated.
5. double Compression camera devices according to claim 1, it is characterised in that：The video acquisition module is to adopt
The video signal format of collection is changed to BT.1120 HD video agreements, according to BT.1120 HD videos agreement by 1080P@25HZ
HD video is sent into video compressing module；Described image size adjustment module RZA is to adjust video size to 720x576, then
720x576@25HZ SDs video is sent into compression core progress video data H.264 to compress.
6. double Compression camera devices according to claim 1, it is characterised in that：By the picture after the JPEG compression
Each data block that data are split out is 1KB sizes.
A kind of 7. host computer decoding apparatus corresponding to double Compression camera devices described in claim 1, it is characterised in that bag
Include：
Data reorganization module, after the serial data for receiving compression, according to zone bit information, by image data from video data
Choose and recombinate；
Decoder module, will choose and recombinate obtained video compression data and picture compression data and carry out decoding respectively and show.
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| CN201710507730.4A CN107360380B (en) | 2017-06-28 | 2017-06-28 | A kind of double Compression photographic devices and its host computer decoding apparatus |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109729361A (en) * | 2019-01-28 | 2019-05-07 | 北京晶品特装科技有限责任公司 | A kind of terminal hardware implementation method with audiovisual compression |
| CN111147902A (en) * | 2020-04-03 | 2020-05-12 | 北京数智鑫正科技有限公司 | Video playing system |
| CN113411492A (en) * | 2018-12-26 | 2021-09-17 | 深圳市道通智能航空技术股份有限公司 | Image processing method and device and unmanned aerial vehicle |
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