CN207339867U

CN207339867U - A kind of time information synchronization system

Info

Publication number: CN207339867U
Application number: CN201721482646.3U
Authority: CN
Inventors: 褚毅宏; 王�锋; 吴树奎; 李瑞峰; 魏磊; 朱志凯; 何广印; 刘锦
Original assignee: Wuhan Hua Rong Country Science And Technology Co Ltd
Current assignee: Shenzhen Huaxun Ark Photoelectric Technology Co ltd
Priority date: 2017-11-07
Filing date: 2017-11-07
Publication date: 2018-05-08
Anticipated expiration: 2027-11-07

Abstract

The utility model discloses a kind of time information synchronization system, system includes：Sequentially connected host computer, intermediate frequency card and multiple signal sources, intermediate frequency card include：The fpga chip being connected with host computer, multiple the ADC daughter boards and time source coding module being connected with fpga chip, each signal source connect an ADC daughter board；Fpga chip includes：The time decoder cache module being connected with time source coding module, the multiple data fusion modules being connected with time decoder cache module, multiple FIFO memories, and the PCI E controllers being connected with multiple FIFO memories and host computer, wherein, each data fusion module is all connected with a FIFO memory and an ADC daughter board.The beneficial effects of the utility model are：Temporal information transmission and management function are realized by fpga chip, and realize under the control of trigger signal merging for AD data and time stamp data, realizes the time synchronization of high-speed AD acquisition.

Description

A kind of time information synchronization system

Technical field

Field of signal processing is the utility model is related to, more particularly to a kind of time information synchronization system.

Background technology

High-speed AD data acquisition is widely used in all conglomeraties such as military affairs, space flight, aviation, railway, machinery.It is different from middling speed And low-speed DAQ system, include high speed circuit inside high-speed data acquistion system, it can be achieved that high frequency analog signals it is high-precision Degree sampling, is used widely in fields such as radar, sonar, software radio, transient signal tests.

In high-speed AD data collecting system, since sample frequency is high, and often by multipath high-speed AD and video, High Speed Serial Gathered at the same time etc. various other signals, therefore the synchronousness between various signals is most important for total system.At present The country there is no the Time Synchronizing for high-speed AD acquisition.

Utility model content

The utility model provides a kind of time information synchronization system, solves the technical problem of the prior art.

The technical solution that the utility model solves above-mentioned technical problem is as follows：

A kind of time information synchronization system, including：Sequentially connected host computer, intermediate frequency card and multiple signal sources, in described Frequency card includes：Fpga chip, multiple ADC daughter boards and time source coding module；The fpga chip includes：Time decoder caches mould Block, multiple data fusion modules, multiple FIFO memories and PCI-E controllers；

One output terminal of each signal source connects an ADC daughter board, which connects a data fusion module, Another output terminal connects the data fusion module；

The time source coding module, the time decoder cache module and the multiple data fusion module connect successively Connect, each data fusion module connects a FIFO memory, the multiple FIFO memory, the PCI-E controllers and institute Host computer is stated to be sequentially connected.

The beneficial effects of the utility model are：Temporal information transmission and management function are realized by fpga chip, and touched Merging for AD data and time stamp data is realized under the control of signalling, the time synchronization of high-speed AD acquisition is realized, also passes through PCI-E controllers are scheduled each circuit-switched data and are uploaded to host computer.

Based on the above technical solutions, the utility model can also do following improvement.

Preferably, the time source coding module includes：The GPS module and time encoding module of interconnection, when described Between coding module the time decoder cache module is connected by LVDS interface.

Preferably, the PCI-E controllers include：Sequentially connected data dispatch module, dma controller and transmission are drawn Hold up, the multiple FIFO memory connects the data dispatch module, and the transmission engine connects institute by PCI-E X8 buses State host computer.

Preferably, an output terminal of each signal source connects an ADC daughter board, ADC by the first SMA connectors Plate connects a data fusion module, another output terminal of the signal source connects the data fusion by the 2nd SMA connectors Module.

Preferably, each ADC daughter boards include：The ADC module and phase-locked loop circuit of interconnection, each ADC module pass through FMC interfaces connect a data fusion module.

Preferably, the intermediate frequency card further includes：Multiple DDR3 controllers, each DDR3 controllers connect a FIFO storage Device.

Preferably, the intermediate frequency card further includes：Power supervisor, the power supervisor connect the multiple DDR3 controls Device and the fpga chip.

Brief description of the drawings

Fig. 1 is a kind of structure diagram for time information synchronization system that the utility model embodiment provides；

Fig. 2 is a kind of structure diagram for time information synchronization system that another embodiment of the utility model provides；

Fig. 3 is a kind of structure diagram for time information synchronization system that another embodiment of the utility model provides.

Embodiment

The principle and feature of the utility model are described below in conjunction with attached drawing, example is served only for explaining this practicality It is new, it is not intended to limit the scope of the utility model.

As shown in Figure 1, a kind of time information synchronization system, including：Sequentially connected host computer 1, intermediate frequency card 2 and multiple letters Number source 3, the intermediate frequency card 2 include：Fpga chip 21, multiple ADC daughter boards 22 and time source coding module 23；The fpga chip 21 include：Time decoder cache module 211, multiple data fusion modules 212, multiple FIFO memories 213 and PCI-E controllers 214；

One output terminal of each signal source 3 connects an ADC daughter board 22, which connects a data fusion Module 212, another output terminal connect the data fusion module 212；

The time source coding module 23, the time decoder cache module 211 and the multiple data fusion module 212 It is sequentially connected, each data fusion module 212 connects a FIFO memory 213, the multiple FIFO memory 213, described PCI-E controllers 214 and the host computer 1 are sequentially connected.

Temporal information transmission and management function are realized using Xilinx fpga chips, and it is real under the control of trigger signal Existing AD data are merged with time stamp data, the time synchronization of high-speed AD acquisition are realized, also by PCI-E controllers to each way According to being scheduled and be uploaded to host computer.

Specifically, time source coding module includes：The GPS module and time encoding module of interconnection, time encoding mould Block decodes cache module by the LVDS interface Connection Time.

As shown in Fig. 2, PCI-E controllers include：Sequentially connected data dispatch module, dma controller and transmission engine, Multiple FIFO memories connect data dispatch module, send engine and connect host computer by PCI-E X8 buses.

Each signal source connects an ADC daughter board by the first SMA connectors, which connects a data fusion Module, the signal source connect the data fusion module by the 2nd SMA connectors.

As shown in figure 3, an output terminal of each signal source connects an ADC daughter board by the first SMA connectors, should ADC daughter boards connect a data fusion module, another output terminal of the signal source connects the data by the 2nd SMA connectors Fusion Module.

Intermediate frequency card further includes：Multiple DDR3 controllers, each DDR3 controllers connect a FIFO memory.

Intermediate frequency card further includes：Power supervisor, power supervisor connect multiple DDR3 controllers and fpga chip.

The advantages of the technical program, is as follows：

1) high-speed ADC control, collection are realized using FPGA；

2) interface communication with time stamp issuing unit is realized；

3) cumulative, the comparison scheduling algorithm of timestamp are realized；

4) timestamp, AD information are realized into data fusion under trigger signal control；

5) by data buffer storage in each road cache module；

6) PCIE is dispatched and each circuit-switched data is uploaded to host computer.

GPS module obtains temporal information in real time from gps satellite, and time encoding module is responsible for GP configuring S chip operation patterns, Receive the GPS module time and temporal information string is turned to LVDS signals and is issued to by the LVDS serial protocols according to predefined FPGA.FPGA is responsible for receiving the configuration information of host computer, and such as sample rate, sampling length, sampling start, and control AD data The work such as upload, encoding and decoding.The real-time continuous serial LVDS temporal informations for obtaining time source and issuing of FPGA, and unstring to be parallel Timestamp is cached.At the same time, multichannel analog signals enter system with trigger signal by SMA, and turn by high-speed ADC Digital signal is turned to, is transferred to FPGA.Data fusion module is issued under the driving of trigger signal according to host computer by PCIE Sampling length, the configuration information such as sampling delay, after a certain amount of AD data and timestamp information are sent to according to protocol packing Hold FIFO cachings.DDR3 controllers are defeated according to FIFO remaining datas amount and PCIE data pool data volume dynamic controls DDR inputs Go out.PCIE High-speed Interface Card is dispatched by multichannel, followed with dma mode according to the size of each road cache module data volume in front end Ring sends each circuit-switched data.

A kind of temporal information synchronous method, including：

S1, GPS module obtain temporal information in real time from gps satellite, and temporal information is sent to time encoding module, when Between coding module the temporal information string received turned to by LVDS signals according to default LVDS serial protocols send to FPGA cores Piece；

Multichannel analog signals are sent to multiple ADC daughter boards, each ADC daughter boards will receive respectively by S2, multiple signal sources Analog signal be converted to digital signal and send to fpga chip, each signal source is also by the corresponding trigger signal of the analog signal Send to fpga chip；

S3, fpga chip receive LVDS signals, the trigger signal corresponding with per railway digital signal per railway digital signal, will LVDS signals unstring as timestamp information, and timestamp information is cached；

S4, fpga chip match somebody with somebody confidence under the driving of every road trigger signal, according to host computer through what PCI-E controllers issued Breath, will transmit to a FIFO memory per the corresponding digital signal of road trigger signal and timestamp information and cache, through every A FIFO memory is sent to PCI-E controllers；

S5, PCI-E controller dock received data packet according to the remaining data amount of each FIFO memory and are scheduled And it is uploaded to host computer.

PCI-E in the remaining data amount and PCI-E controllers of the FIFO memory that DDR3 controllers are connected according to itself The input and output of the data volume dynamic control FIFO memory of data pool.

The above is only the preferred embodiment of the present invention, is not intended to limit the utility model, all in this practicality Within new spirit and principle, any modification, equivalent replacement, improvement and so on, should be included in the guarantor of the utility model Within the scope of shield.

Claims

A kind of 1. time information synchronization system, it is characterised in that including：Sequentially connected host computer, intermediate frequency card and multiple signals Source, the intermediate frequency card include：Fpga chip, multiple ADC daughter boards and time source coding module；The fpga chip includes：Time Decode cache module, multiple data fusion modules, multiple FIFO memories and PCI-E controllers；

One output terminal of each signal source connects an ADC daughter board, which connects a data fusion module, another A output terminal connects the data fusion module；

The time source coding module, the time decoder cache module and the multiple data fusion module are sequentially connected, often A data fusion module connects a FIFO memory, the multiple FIFO memory, PCI-E controllers and described upper Machine is sequentially connected.
A kind of 2. time information synchronization system according to claim 1, it is characterised in that the time source coding module bag Include：The GPS module and time encoding module of interconnection, the time encoding module connect the time solution by LVDS interface Code cache module.
3. a kind of time information synchronization system according to claim 1, it is characterised in that the PCI-E controllers include： Sequentially connected data dispatch module, dma controller and transmission engine, the multiple FIFO memory connect the data dispatch Module, the transmission engine connect the host computer by PCI-E X8 buses.
A kind of 4. time information synchronization system according to claim 3 a, it is characterised in that output of each signal source End by the first SMA connectors connect an ADC daughter board, the ADC daughter boards connect a data fusion module, the signal source it is another One output terminal connects the data fusion module by the 2nd SMA connectors.
5. a kind of time information synchronization system according to claim 4, it is characterised in that each ADC daughter boards include：Mutually The ADC module and phase-locked loop circuit of connection, each ADC module connect a data fusion module by FMC interfaces.
6. according to a kind of time information synchronization system of claim 1-5 any one of them, it is characterised in that the intermediate frequency card is also Including：Multiple DDR3 controllers, each DDR3 controllers connect a FIFO memory.
7. a kind of time information synchronization system according to claim 6, it is characterised in that the intermediate frequency card further includes：Electricity Source manager, the power supervisor connect the multiple DDR3 controllers and the fpga chip.