CN210515284U

CN210515284U - Dual-channel 1553B communication board card

Info

Publication number: CN210515284U
Application number: CN201921578031.XU
Authority: CN
Inventors: 李进军; 喻劲峰
Original assignee: Beijing Shenzhou Feihang Technology Co ltd
Current assignee: Beijing Shenzhou Feihang Technology Co ltd
Priority date: 2019-09-20
Filing date: 2019-09-20
Publication date: 2020-05-12
Anticipated expiration: 2029-09-20

Abstract

The utility model relates to a data transmission control field, concretely relates to bi-pass 1553B communication board card, which comprises a PCI bus interface, an FPGA for processing received and sent information, 2 groups of memories, a bi-pass 1553 transceiver and a bi-pass 1553 isolation transformer; the utility model discloses purchasing cost has greatly been saved. The 2 channels can receive and transmit data simultaneously, and the data transmission speed can be effectively improved. Meanwhile, the board card supports a large number of additional functions commonly used by domestic clients, helps the clients to process 1553B bus data in real time, and greatly simplifies inconvenience in software development.

Description

Dual-channel 1553B communication board card

Technical Field

The utility model relates to a data transmission control field, concretely relates to 1553b communication integrated circuit board.

Background

The 1553b bus is also called MILSTD1553B bus, and is an information transmission bus standard, namely a protocol for transmission among devices, which is specially established for equipment on an airplane by the American military. The MILSTD1553b data bus has bidirectional output characteristic and high real-time performance and reliability, is widely applied to current-generation transport planes and a considerable number of civil airliners and military aircrafts, and is also widely applied to aerospace systems. The 1553b bus system mainly comprises 3 parts: the bus controller BC, the remote terminal RT and optionally the bus guardian MT, have an operating frequency of 1 Mb/s. However, as the amount of transmitted data increases, the 1M rate cannot meet the application requirements under some special conditions, relevant departments and organizations in China release a 1553B specification of 4M upgrading version, the protocol layer of the 1553B specification is completely compatible with 1M1553B, the speed is only accelerated at home, and the speed is changed from 1Mb/s to 4 Mb/s.

The board card is developed based on 1M and 4M transmission rates compatible with a 1553b bus. The main working principle is that a 1553 protocol IP and a transceiver developed by our company are utilized to transmit and receive data signals. The transceiver is constructed by separating elements instead of a traditional 1M transceiver chip, and can simultaneously support the transmission of 1M and 4M 1553B signals. Therefore, the cost of outsourcing chips is saved, and the support of multi-rate is supported.

Most products of the currently known 1553b bus are designed by adopting foreign protocol chips and transceivers, and the problems of long supply period and high purchase cost exist. At present, only mature chips of 1M1553B products exist in the market, related chips of 4M products do not exist, and 4M rate product suppliers are single and monopolized by a certain company.

Disclosure of Invention

The utility model aims to provide a 1553B integrated circuit board of a pair of passageway realizes the 1553B agreement with FPGA, adopts from researching transceiver circuit simultaneously, can support 1M and 4M transmission rate simultaneously. The method is realized by the following steps:

a dual-channel 1553B communication board comprises a PCI bus interface, an FPGA for processing received and sent information, 2 groups of memories, a dual-channel 1553 transceiver and a dual-channel 1553 isolation transformer, wherein the FPGA is used for processing the received and sent information; the 1553 transceivers are provided with 4 groups, each channel is provided with 2 groups, and the transceivers are arranged on the board card in parallel; the memories are 2 groups and are arranged on the board card in parallel with the FPGA; a bus controller, a 1553 functional module and a storage management module are arranged in the FPGA; the internal modules are directly connected through a logic circuit; each channel 1553 transformer is in communication connection with a 1553 transceiver, and the 1553 transceiver is in communication connection with a 1553 functional module in the FPGA; the 2 groups of memories are in communication connection with an FPGA internal storage management module; and the PCI bus interface is in communication connection with the FPGA through a bus controller.

Further, in the above technical solution, an MT bus monitor is arranged inside the FPGA and used for monitoring system communication.

Further, in the above technical solution, the board card further provides dual-channel RS422 and TTL signal input/output, and the board card is provided with a dual-channel RS422 level digital input/output module and an isolated RS422 transceiver; the double-channel TTL digital quantity input/output module is provided with an isolation TTL driver; the FPGA is also internally provided with a trigger processing module; and the double-channel RS422 and TTL signal input/output module are in communication connection with the trigger processing module.

Further, in the above technical solution, the memory is a 16M × 16bit SDRAM.

Further, in the above technical solution, the FPGA is further provided with an encryption module.

The utility model discloses purchasing cost has greatly been saved. The 2 channels can receive and transmit data simultaneously, and the data transmission speed can be effectively improved. Meanwhile, the board card supports a large number of additional functions commonly used by domestic clients, helps the clients to process 1553B bus data in real time, and greatly simplifies inconvenience in software development.

Drawings

FIG. 1 is a schematic diagram of a board card structure;

FIG. 2 is a model diagram of an FPGA architecture.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings.

The board card of the utility model comprises a PCI bus interface, an FPGA for processing received and sent information, 2 groups of memories, a two-channel 1553 transceiver and a two-channel 1553 isolation transformer; the 1553 transceivers are provided with 4 groups, each channel is provided with 2 groups, and the transceivers are arranged on the board card in parallel; the storage comprises 2 groups, the storage is placed on the board card in parallel with the FPGA, and the storage is a 16M 16bit SDRAM; a bus controller, a 1553 functional module and a storage management module are arranged in the FPGA; the internal modules are directly connected through a logic circuit; each channel 1553 transformer is in communication connection with a 1553 transceiver, and the 1553 transceiver is in communication connection with a 1553 functional module in the FPGA; the 2 groups of memories are in communication connection with an FPGA internal storage management module; and the PCI bus interface is in communication connection with the FPGA through a bus controller.

Meanwhile, in order to realize the triggering input/output function of the 1553B message, the board card also provides dual-channel RS422 and TTL signal input/output, and is provided with a dual-channel RS422 level digital quantity input/output module and an isolation RS422 transceiver; the double-channel TTL digital quantity input/output module is provided with an isolation TTL driver; the FPGA is also internally provided with a trigger processing module; and the double-channel RS422 and TTL signal input/output module are in communication connection with the trigger processing module.

As shown in fig. 1, after entering the board card, the 1533B signal passes through the isolation transformer, is converted by the transceiver circuit, becomes a TTL level signal, and enters the FPGA to perform 1553B protocol analysis. The PCI bus interface realizes the PCI bus interface time sequence by the PCI IP in the FPGA chip and completes the reading and writing functions of the PCI bus.

As shown in fig. 2, the 1553B bus enters the FPGA through the transceiver via bus data, and is subjected to serial-to-parallel conversion via the manchester codec module. The analysis clock of the Manchester encoding and decoding module is controlled and selected by the PCI bus and can be set to be 1M or 4M. And then completes 1553B standard protocol analysis through a BC protocol module, an RT protocol module and an MT protocol module, and forms a 1553B message frame. The BC Service module, the RT Service module and the MT Service module store the message frames, then submit the message frames to the PCI bus for access, and simultaneously perform trigger correlation processing to realize the trigger input/output function of external TTL/RS422 signals.

The FPGA is also provided with an encryption module.

Claims

1. The utility model provides a 1553B communication integrated circuit board of binary channels which characterized in that: the board card comprises a PCI bus interface, an FPGA for processing received and sent information, 2 groups of memories, a dual-channel 1553 transceiver and a dual-channel 1553 isolation transformer;

the 1553 transceivers are provided with 4 groups, each channel is provided with 2 groups, and the transceivers are arranged on the board card in parallel;

the memories are 2 groups and are arranged on the board card in parallel with the FPGA;

a bus controller, a 1553 functional module and a storage management module are arranged in the FPGA; the internal modules are directly connected through a logic circuit;

each channel 1553 transformer is in communication connection with a 1553 transceiver, and the 1553 transceiver is in communication connection with a 1553 functional module in the FPGA; the 2 groups of memories are in communication connection with an FPGA internal storage management module;

and the PCI bus interface is in communication connection with the FPGA through a bus controller.

2. The dual-channel 1553B communication board of claim 1, wherein: and an MT bus monitor is arranged in the FPGA and used for monitoring system communication.

3. The dual-channel 1553B communication board of claim 1, wherein: the board card also provides dual-channel RS422 and TTL signal input/output, and is provided with a dual-channel RS422 level digital quantity input/output module and an isolation RS422 transceiver; the double-channel TTL digital quantity input/output module is provided with an isolation TTL driver;

the FPGA is also internally provided with a trigger processing module;

and the double-channel RS422 and TTL signal input/output module are in communication connection with the trigger processing module.

4. The dual-channel 1553B communication board of claim 1, wherein: the memory is a 16M by 16bit SDRAM.

5. The dual-channel 1553B communication board of claim 1, wherein: the FPGA is also provided with an encryption module.