CN107544328A - CAN controller chip interface serialization device - Google Patents
CAN controller chip interface serialization device Download PDFInfo
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- CN107544328A CN107544328A CN201710794173.9A CN201710794173A CN107544328A CN 107544328 A CN107544328 A CN 107544328A CN 201710794173 A CN201710794173 A CN 201710794173A CN 107544328 A CN107544328 A CN 107544328A
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Abstract
It is cost-effective by the design to CAN controller interface serial, to realize the far distance controlled to CAN controller, also can effectively reduce transmission line the present invention relates to communications protocol chip, reduce the interface requirement to master controller.The present invention, CAN controller chip interface serialization device, including interface management logic, information buffer, bit stream processor, acceptance fitration, bit timing logic, mistake manages logical sum serioparallel exchange unit；Wherein：Order of the interface management logical process from CPU, data, the addressing of internal register is controlled, and interruption and status information are provided to CPU；Information buffer is for storing the message sent and received；Acceptance fitration carries out an acceptance inspection filtering to the identifier of message to determine whether to receive the message；Bit stream processor controls generation, error detecting and handling, arbitration, the filling of CAN data flows.Present invention is mainly applied to the design and manufacture of communications protocol chip.
Description
Technical field
The present invention relates to communications protocol chip, a kind of serialization design more particularly to CAN controller chip interface and
Its control method.
Background technology
Controller Area Network (CAN) are controller LAN, i.e. controller LAN, are international most wide
One of general fieldbus.At first the communication that CAN is designed as in automotive environment is applied, and is carrying electronic control device
(ECU) information is exchanged between, forms electronic control network of automobile.CAN is as a kind of advanced technology, reliability is high, transmits
The network service control mode of the features such as distance, real-time height, perfect in shape and function, reasonable cost, has been widely applied to industry
The various fields such as automation, various control equipment, the vehicles, Medical Instruments and building, environmental Kuznets Curves.
After the content of CAN agreement determines substantially, Intel develops CAN controller chip I NTEL82526 first,
This is that first hardware of CAN protocol is realized.Subsequent Philips semiconductors are also proposed its CAN controller 82C200 and later
SJA1000 that is most widely used and supporting CAN2.0B.
At present, the CAN controller chip of in the market is mostly parallel interface, and data use parallel processing, but work as chip
With master controller it is distant when, typically using serial communication mode without using parallel communication fashion.It is because parallel logical
The line that the cost of letter system is higher, numerous is not only readily incorporated interference, and line fault also easily occurs.
Serial communication refer between main frame and peripheral hardware and between host computer system and host computer system data it is serial
Transmission.Using a data line, ground of data one is transmitted successively, each data occupies a regular time length
Degree.It needs several line cans to exchange information between system, especially suitable for computer and computer, computer with
Telecommunication between peripheral hardware.
Bibliography：
[1] Zhu Min, Zhang Chongwei, it is big to thank to application [J] Hefei industry of the shake .CAN buses in acquisition and control system
Learn journal：Natural science edition, 2002,25 (3):345-349.
[2] Liu Fu, Luo Huiqiong .CAN buses summary [J] Fujian computer, 2006 (4):26-27.
[3] in great waves, application [J] .Global Electronics Chinas of the Du Fudan .CAN in automotive electronics, 2006
(11):58-60.
[4]Marino A,Schmalzel J.Controller Area Network for In-Vehicle Law
Enforcement Applications[A].In:Sensors Applications Symposium[C].California,
USA:2007.1-5.
[5]Xing W,Chen H,Ding H.The application of controller area network on
vehicle[A].In:Vehicle Electronics Conference[C].Beijing,China:1999.455-458.
[6] research of the new vehicle-mounted CANs bus computer monitoring systems of Liu Zhen is with applying [J] urban construction theoretical researches:
Electronic edition, 2015 (9).
The content of the invention
For overcome the deficiencies in the prior art, it is contemplated that by the design to CAN controller interface serial, can
To realize the far distance controlled to CAN controller, transmission line also can be effectively reduced, it is cost-effective, reduce to master controller
Interface requirement.The technical solution adopted by the present invention is CAN controller chip interface serialization device, including interface management logic,
Information buffer, bit stream processor, acceptance fitration, bit timing logic, mistake manages logical sum serioparallel exchange unit；Wherein：
Order of the interface management logical process from CPU, data, the addressing of internal register is controlled, and provided to CPU
Interruption and status information；
Information buffer is for storing the message sent and received；
Acceptance fitration carries out an acceptance inspection filtering to the identifier of message to determine whether to receive the message；
Bit stream processor controls generation, error detecting and handling, arbitration, the filling of CAN data flows；
Bit timing, sampling and the synchronization of bus in bit timing logic control；
Mistake manages logic is used for receiving from information of the bit stream processor about mistake, then the error reporting of correlation
Reflect interface management logic；
Serioparallel exchange unit is to be converted into going here and there by the order from interface management logical sum information buffer, address and data
Row data are sent to CPU, and the serial order from CPU, address and data also are converted into parallel data is sent to interface management
Logical sum information buffer.
Serioparallel exchange unit externally selects CS, clock CLK, data receiving end Si, data origin So to be led to CPU by piece
Letter；Internally by ALE, RD, WR and interface management logic communication, pass through [7:0] port is handled in interface management logic and come from
CPU order and the addressing of internal register, while pass through [7:0] port carries out data exchange with information buffer；String is simultaneously
Converting unit inputs CS, CLK and Si signal by CPU, after chip selection signal is inputted, starts to pass to serioparallel exchange unit from Si pins
Data are sent, each clock transmission a data, one byte data of transmission need 24；When there is chip selection signal, preceding 8 clocks
What the cycle sent is command signal, so as to judge it is reading or write signal, provides reading or writes enabled, middle 8 clock cycle
What is sent is the address of register, in the 16th clock cycle, exports an ale signal to interface management logic, address is locked
Deposit, while send RD in 16 clock cycle trailing edges if above interpretation is reading instruction and give interface management logic, by interface
Management logic prepares to need the data read, is data bit corresponding to last 8 clock cycle, if it is then interface management to read
Logic is to CPU output datas, is CPU to CAN controller input data if writing.
The features of the present invention and beneficial effect are：
CAN has increasingly been widely deployed in industry, agricultural, military affairs, parallel CAN controlling transmission
Control closely is only applicable to, and the data wire taken and the space of master controller are big, when long-distance transmissions control, and
Row transmission cost is high, and easily introduces interference.Serial CAN controlling transmission is more applicable for long-distance transmissions control, section
About cost, reduce the interface requirement to master controller.
Brief description of the drawings：
Fig. 1 CAN controller interface serials realize block diagram.
Fig. 2 serioparallel exchange units and annexation.
Fig. 3 Serial Control timing diagrams.
Embodiment
As shown in figure 1, typical CAN controller structure includes interface management logic, information buffer, bit stream processing
Device, acceptance fitration, bit timing logical sum mistake manages logic.Improved CAN controller is believed in interface management logical sum
Interface serial is realized by a serioparallel exchange unit at breath buffer.
Order of the interface management logical process from CPU, data, the addressing of internal register is controlled, and provided to CPU
Interruption and status information.
Information buffer is for storing the message sent and received.
Acceptance fitration carries out an acceptance inspection filtering to the identifier of message to determine whether to receive the message.
Bit stream processor controls the generation of data flow in CAN controller, error detecting and handling, arbitration, filling
All performed in its inside.
Bit timing, sampling and the synchronization of bus in bit timing logic control.
Mistake manages logic is used for receiving from information of the bit stream processor about mistake, then the error reporting of correlation
Reflect interface management logic.
Serioparallel exchange unit is to be converted into going here and there by the order from interface management logical sum information buffer, address and data
Row data are sent to CPU, and the serial order from CPU, address and data also are converted into parallel data is sent to interface management
Logical sum information buffer.
As shown in Fig. 2 serioparallel exchange unit externally shares four signal wires, respectively CS (chip selection signal), So (output strings
Row signal), Si (incoming serial signal), CLK (clock), have ALE (address latch signal), RD to CAN controller inside
(read signal), WR (write signal), [7:0] port (8 bit address or data-signal).
As shown in figure 3, corresponding 24 clocks of piece choosing each time, corresponding byte transmission, 8 are before Si or So transmission
Command signal, it correspond to read or write, middle 8 correspond to address signal, and latter 8 correspond to data-signal, in transmitting procedure
Middle generation ALE (address latch signal), RD (read signal) and WR (write signal) are transferred to inside CAN controller.
Serioparallel exchange unit is designed with reference to Fig. 2 and Fig. 3 and control is described in detail.
This serioparallel exchange unit is designed and controlled according to Fig. 3 control sequential figures, and serioparallel exchange unit is by master controller
CS, CLK and Si are inputted, after chip selection signal is inputted, is started to transmit data, each clock to serioparallel exchange unit from Si pins
A data is transmitted, one byte data of transmission need 24.When there is chip selection signal, what preceding 8 clock cycle sent is instruction
Signal, so as to judge it is reading or write signal, provide reading or write enabled, what middle 8 clock cycle sent is CAN control
The address of device internal register processed, in the 16th clock cycle, an ale signal is exported to CAN controller inside, by ground
Location is latched, while is sent read signal in 16 clock cycle trailing edges if above interpretation is reading instruction and controlled to CAN
Inside device, prepare to need the data read by internal, be data bit corresponding to last 8 clock cycle, if it is then CAN to read
Bus control unit is to master controller output data, is main control to CAN controller input data if writing.If
Write command, then write signal is sent to CAN controller in the 23rd clock cycle, realize write operation.
Claims (2)
1. a kind of CAN controller chip interface serialization device, it is characterized in that, including interface management logic, information buffer, position
Stream handle, acceptance fitration, bit timing logic, mistake manages logical sum serioparallel exchange unit；Wherein：
Order of the interface management logical process from CPU, data, the addressing of internal register is controlled, and interruption is provided to CPU
And status information；
Information buffer is for storing the message sent and received；
Acceptance fitration carries out an acceptance inspection filtering to the identifier of message to determine whether to receive the message；
Bit stream processor controls generation, error detecting and handling, arbitration, the filling of CAN data flows；
Bit timing, sampling and the synchronization of bus in bit timing logic control；
Mistake manages logic is used for receiving from information of the bit stream processor about mistake, and then the error reporting of correlation is reflected
To interface management logic；
Serioparallel exchange unit is that the order from interface management logical sum information buffer, address and data are converted into serial number
According to CPU is sent to, the serial order from CPU, address and data are also converted into parallel data and are sent to interface management logic
And information buffer.
2. CAN controller chip interface serialization device as claimed in claim 1, it is characterized in that, serioparallel exchange unit is external
CS, clock CLK, data receiving end Si, data origin So is selected to be communicated by piece with CPU；Internally pass through ALE, RD, WR and interface
Logic communication is managed, passes through [7:0] port handles seeking for order from CPU and internal register in interface management logic
Location, while pass through [7:0] port carries out data exchange with information buffer；Serioparallel exchange unit inputs CS, CLK and Si by CPU
Signal, after chip selection signal is inputted, started to transmit data, each clock transmission one digit number to serioparallel exchange unit from Si pins
According to one byte data of transmission need 24；When there is chip selection signal, what preceding 8 clock cycle sent is command signal, so as to sentence
Disconnected is reading or write signal, provides reading or writes enabled, what middle 8 clock cycle sent is the address of register, the 16th
The individual clock cycle, an ale signal is exported to interface management logic, by address latch, while if above interpretation is reading instruction
Then RD is sent in 16 clock cycle trailing edges and gives interface management logic, prepared to need the data read by interface management logic,
Data bit corresponding to last 8 clock cycle, if read be then interface management logic to CPU output datas, if writing
It is then CPU to CAN controller input data.
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| CN201710794173.9A CN107544328A (en) | 2017-09-06 | 2017-09-06 | CAN controller chip interface serialization device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108919788A (en) * | 2018-09-10 | 2018-11-30 | 汽-大众汽车有限公司 | A kind of remote monitoring system and method for the automobile bench test based on vehicle-mounted CAN bus |
| CN113485954A (en) * | 2021-06-29 | 2021-10-08 | 中国科学院近代物理研究所 | CAN control unit and ion accelerator power supply controller |
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|---|---|---|---|---|
| CN108919788A (en) * | 2018-09-10 | 2018-11-30 | 汽-大众汽车有限公司 | A kind of remote monitoring system and method for the automobile bench test based on vehicle-mounted CAN bus |
| CN113485954A (en) * | 2021-06-29 | 2021-10-08 | 中国科学院近代物理研究所 | CAN control unit and ion accelerator power supply controller |
| CN113485954B (en) * | 2021-06-29 | 2023-04-11 | 中国科学院近代物理研究所 | CAN control unit and ion accelerator power supply controller |
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Application publication date: 20180105 |