CN103532686B - Serial data transmission circuit and control method thereof with line sequence self-adaptive - Google Patents
Serial data transmission circuit and control method thereof with line sequence self-adaptive Download PDFInfo
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Abstract
The invention discloses a kind of serial data transmission circuit with line sequence self-adaptive and control method thereof, this circuit includes serial data transmitting terminal signal processing module and Serial data receiving end signal processing module, wherein, the front end of this serial data transmitting terminal signal processing module is connected with serial data transmitting terminal signal generation module, and rear end is connected with serial signal transfer channel；The front end of this Serial data receiving end signal processing module is connected with serial signal transfer channel, and rear end is connected with Serial data receiving end signal receiver module.The serial data transmission circuit with line sequence self-adaptive of present invention offer and control method thereof, it is not only able to preferably detect the line sequence mistake due in serial signal transfer, and data transmit-receive two ends can be made correctly to be transmitted data with self-adaptative adjustment serial signal line sequence.The present invention has preferable versatility simultaneously, can apply to the various wired or wireless various standard serial data transmissions waited in transmission channel.
Description
Technical field
The application relates to Circuits System technical field, particularly relates to a kind of with line sequence self-adaptive
Serial data transmission circuit and control method thereof.
Background technology
Serial data communication transmission is less and obtain a wide range of applications, such as due to its line number signal
Universal Asynchronous Receive/dispensing device (Universal Asynchronous Receiver/Transmitter,
UART), Serial Peripheral Interface (SPI) (Serial Peripheral Interface, SPI) and other implementations
(such as I2C), wherein UART is asynchronous serial communication mode, generally uses data to send (TxD)
With data receiver (RxD) two paths of signals line；SPI is synchronous serial communication mode, generally uses three
Line (CLK, DATA and EN tri-road holding wire) or four line (CLK, MOSI, MISO and EN
Four road holding wires) pattern.
Owing to serial data signal line is less, its line sequence problem is just particularly important, the mistake of line sequence
The data that will result directly in transmission can not be correctly received.In the transmission of serial signal realizes, due to
The situations such as fly line mistake, design mistake and wireless channel frequency mistake, often occur that line sequence mistake is asked
Topic.
For detection and correction line sequence relevant issues, some patents have been had to propose solution.
The patent " a kind of line sequence method of testing " of Application No. 201010002667.7, it is proposed that a kind of
Ethernet line carries out the method for line sequence test.But ethernet line can only be tested by this method；
And only sniffing function, and there is no self adaptation error correction；The most this method based on electric resistance partial pressure,
Needing modulus conversion chip (hereinafter referred ADC), the degree of stability of resistance and ADC all can affect line
Sequence test result.Patent similar therewith also has the patent " network of Application No. 200820029252.7
Wiring fault simulation tester ", equally either with or without error correction, can only defect based on RJ-45.
The patent " a kind of multicore communication cable comprehensive tester " of Application No. 200910154166.8,
Propose a kind of multicore communication cable comprehensive tester, use encoding and decoding CPU to carry out line sequence information survey
Examination, but this method needs also exist for based on ADC, and need independent CPU, and can only carry
For test function, and do not have from error correction.Patent similar therewith also has Application No.
The patent " multiple conductor cable line sequence and fault locator " of 94223771.4, Application No.
200610146680.3 patent " detection method " and Application No. 200610166865.0 patent " use
In the detection method that at least one cable is detected ", there is a need to independent CPU, Zhi Nengti equally
Supply test function and not there is the defect from error correction.
The patent " network line sequence converter " of Application No. 200620036870.5, it is proposed that a kind of net
Line line sequence changer, can carry out line sequence conversion to netting twine based on RJ-45, but this network line
Netting twine based on RJ-45 can only be converted by sequence changer, and can only be fixed line sequence conversion,
And there is no error detection and self adaptation error correction.
Sum up above-mentioned patent, it can be seen that Current patents and implementation thereof all also exist can only be examined
Survey and maybe can only be fixed line sequence switching, and mostly can only based on special interface (RJ-45) lack
Point.
As it is shown in figure 1, Fig. 1 is existing serial data signal transmits schematic diagram.Existing serial signal
Transmitting-receiving mode is: by serial signal transmitting terminal, transmitting terminal being processed circuit needs the data sent by agreement
Being converted into serial data signal, serial data signal is transmitted at serial data signal transmission channel,
Serial data signal will be turned after receiving serial data signal by Serial data receiving end by agreement
Gaining the serial data of legacy data form, the serial data converting back legacy data form is transferred to
Receiving terminal processes circuit and is for further processing.Wherein, transmitting terminal processes circuit can be processor
(CPU or MCU), digital signal processor (DSP) or other process circuit (FPGA, CPLD
Deng), serial data signal transmission channel can be wired cable or PCB metal wire, also
It can be wireless signal channel.
As a example by the form of base band control signal is for SPI standard signal, SPI signal is a kind of to synchronize string
The interface bus of row peripheral hardware, it can make processor lead in a serial fashion with various peripheral apparatus
Letter, working method is master-slave mode.SPI transmission means is divided into three-wire system and two kinds of implementations of four-wire system,
Fig. 2 top half illustrates normal three-wire system SPI and realizes, and three-wire system SPI typically has following
Three road signals: clock signal (CLK), enable signal (EN) and data signal (DATA).Its
Middle CLK signal is sampled signal, samples signal when CLK signal is rising edge, when adopting
During sample, EN stabilizes to the currency of high level then DATA and will be read as valid data, such as DATA
Then read as data ' 0 ' for low level, do as data ' 1 ' reading if DATA is high level.As
Shown in Fig. 2, in order to ensure that CLK rising edge can be sampled accurately, EN signal and DATA all should
It was ready to before CLK rises, was referred to as in digital circuit during this period of time before CLK rises
" setting up the time (Setup Time) ", in the example shown in Fig. 2, EN more carries relative to DATA signal
More front time sets up.Example as shown in Fig. 2 top half, receiving terminal rising edge clock sample,
In the case of EN is high level, sample successively ' 0 ', ' 1 ', ' 0 ', ' 1 ', ' 1 ', ' 0 ', ' 1 ' and
‘0’.(Most Significant Bit, the highest have to use MSB transmission mechanism at first in instant example
Effect position), namely first ' 0 ' be MSB, 8 bit result of sampling are 0b01011010, enter with ten
Tabulation is shown as 90, and hexadecimal representation is 0x5A.
Fig. 2 the latter half illustrates three line SPI and exchanges due to EN signal and DATA signal mistake
Line sequence mistake and the data transmission fault that causes.Owing to the former data level of DATA that should be is by conduct
EN process, and the former data level of EN that should be is by as DATA process, makes rising edge clock only
Have and just can assert valid data former DATA signal (the existing EN signal for mistake) is for ' 1 ' when,
And DATA signal is ' 1 ' when, EN signal one is set to ' 1 ', this results in the letter that SPI adopts
Number all ' 1 ', adopting signal numerical value obtained when of 8 valid data is 8 bits
According to 0b11111111 (with hexadecimal representation as 0xFF, with decimal representation for 255).
Fig. 3 the latter half illustrates three line SPI due to CLK signal and the exchange of DATA signal mistake
Line sequence mistake and the data transmission fault that causes.Owing to the former data level of DATA that should be is by conduct
CLK process, and the former data level of CLK that should be is by as DATA process, makes clock (originally
DATA signal) rising edge time EN signal one be set to ' 1 ' (as it was previously stated, EN signal compares DATA
Signal (by as CLK signal) shifts to an earlier date the foundation of some time), and DATA signal is (originally
CLK signal) one it is set to ' 0 ' (due to the reason of the time of setting up, DATA signal carries than CLK signal
Front foundation, and when DATA signal is as clock signal (CLK), the when of the sampling of its rising edge
Before DATA signal (former CLK) is in rising edge, one is set to ' 0 '), this results in SPI and adopts
The signal all ' 0 ' arrived, adopting signal numerical value obtained when of 8 valid data is 8 two
Binary data 0b00000000 (with hexadecimal representation as 0x00, with decimal representation for 0).
Summary of the invention
(1) to solve the technical problem that
For said one or multiple problem present in prior art, present invention is primarily targeted at
There is provided a kind of serial data transmission circuit with line sequence self-adaptive and control method thereof, with to line
Sequence mistake detects, the line sequence of self-adaptative adjustment serial signal and relative time delay, makes data transmit-receive two
End is able to correct transmission data.
(2) technical scheme
According to an aspect of the present invention, the invention provides a kind of string with line sequence self-adaptive
Row data transmission circuit, this circuit includes serial data transmitting terminal signal processing module 100 and serial number
According to receiving end signal processing module 200, wherein, this serial data transmitting terminal signal processing module 100
Front end is connected with serial data transmitting terminal signal generation module 300, rear end and serial signal transfer channel
Connect；This Serial data receiving end signal processing module 200 front end is connected with serial signal transfer channel,
Rear end is connected with Serial data receiving end signal receiver module 400.
In such scheme, described serial data transmitting terminal signal processing module 100 includes serial signal mould
Formula signal generating unit 101, serial signal transmitting terminal control unit 104, feedback signal reception unit 105
With error model identifying unit 106, wherein, serial signal schema creation unit 101 respectively with serial
Data sending terminal signal generation module 300, serial signal transfer channel and serial signal transmitting terminal control
Unit 104 connects, serial signal transmitting terminal control unit 104 respectively with serial signal schema creation list
Unit 101, error model identifying unit 106 and feedback signal reception unit 105 connect.
In such scheme, described serial signal schema creation unit 101, including serial signal intersection square
A period of time unit 103, for receiving the original string that serial data transmitting terminal signal generation module 300 sends
Row data signal, receives the control signal of serial signal transmitting terminal control unit 104, and by original string
Row data signal is after its serial signal cross matrix subelement 103 processes, and serial has been revised in output
Data signal.Described serial signal cross matrix subelement 103 is for according to serial signal transmitting terminal control
The instruction of unit processed carries out signal cross.
In such scheme, described serial signal transmitting terminal control unit 104 is used for receiving feedback signal and connects
Receive the Serial data receiving feedback signal that unit 105 transmits, and it is single to be sent to error model judgement
Unit 106, receives the type of error that error model identifying unit 106 returns, according to this type of error control
The mode of operation of serial signal schema creation unit 101 processed, if type of error is unknown, then serial letter
Number transmitting terminal control unit 104 serially will send alarm signal by data sending terminal signal generation module 300
Breath.
In such scheme, described feedback signal reception unit 105 is for feeding back Serial data receiving end
Signal carries out pretreatment, and the signal after processing sends serial signal transmitting terminal control unit 104 to.
In such scheme, described error model identifying unit 106, comprise error model storing sub-units
107, for receiving wrong decision request and the serial that serial signal transmitting terminal control unit 104 sends
Data receiver feedback signal, by with the ratio of model of storage in error model storing sub-units 107
To and analyze, analyze current erroneous model, result is sent to serial signal transmitting terminal control unit
104。
In such scheme, described Serial data receiving end signal processing module 200 includes: serial signal
Receiving terminal control unit 201, it is believed that for the serial number of correction received on serial signal transfer channel
Number, and this signal is sent to Serial data receiving end signal receiver module 400 and feedback signal generation
Unit 202, and enable feedback signal generating unit 202 and produce Serial data receiving on the feedback channel
End feedback signal；Feedback signal generating unit 202, is used for receiving serial signal receiving terminal control unit
201 serial data signals transmitted and feedback signal instruction, generate Serial data receiving end feedback signal,
Output is to feedback signal reception unit 105.Described feedback signal generating unit 202 is in the feedback generated
Signal adds entry identification signal.
According to another aspect of the present invention, present invention also offers a kind of serial data transmitting-receiving controlling party
Method, is applied to the described serial data transmission circuit with line sequence self-adaptive, and the method includes:
Step A: serial signal transmitting terminal control unit 104 controls serial signal schema creation unit 101
Send test serial data signal；
Step B: serial signal transmitting terminal control unit 104 receives Serial data receiving end feedback signal
And send decision request and data to error model identifying unit 106；
Step C, when serial signal transmitting terminal control unit 104 receives error model identifying unit 106
" normally " signal after, control serial signal schema creation unit 101 by original serial data signal
It is conveyed directly to serial signal transfer channel；
Step D, when serial signal transmitting terminal control unit 104 receives error model identifying unit 106
" known error model " signal after, control serial signal schema creation unit 101 by AD HOC
Carrying out signal demonstration and signal cross, the signal after processing is sent to serial signal transfer channel；
Step E, when serial signal transmitting terminal control unit 104 receives error model identifying unit 106
" unknown error model " signal after, serially data sending terminal signal generation module 300 sends report
Alarming information wait process instruction further.
(3) beneficial effect
The serial data transmission circuit with line sequence self-adaptive of present invention offer and controlling party thereof
Method, is not only able to preferably detect the line sequence mistake due in serial signal transfer, and can be adaptive
Serial signal line sequence should be adjusted, make data transmit-receive two ends correctly be transmitted data.The present invention simultaneously
There is preferable versatility, can apply to the various wired or wireless various standard strings waited in transmission channel
Row data are transmitted.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of existing serial data signal transmission；
Fig. 2 is existing explanation as a example by three line SPI due to line sequence mistake (EN and DATA signal mistake
By mistake exchange) schematic diagram of data transmission fault that causes.
Fig. 3 is existing explanation as a example by three line SPI due to line sequence mistake (CLK and DATA signal mistake
By mistake exchange) schematic diagram of data transmission fault that causes.
The hardware frame of the serial data transmission circuit with line sequence self-adaptive that Fig. 4 present invention provides
Structure schematic diagram.
The serial data transmission circuit with line sequence self-adaptive that Fig. 5 provides for the present invention is unidirectional
Serial data transmission system realizes schematic diagram.
The serial data transmission circuit with line sequence self-adaptive that Fig. 6 provides for the present invention is two-way
Serial data transmission system realizes schematic diagram.
The mistake of the serial data transmission circuit with line sequence self-adaptive that Fig. 7 provides for the present invention
The flow chart that model judges.
Fig. 8 is the schematic diagram of serial signal cross matrix subelement work functions.
Fig. 9 is the flow chart that the test generation of signal, feedback and error model judge.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with concrete real
Execute example, and referring to the drawings, the present invention is described in more detail.
In the most described detailed description of the invention, it is assumed that the form of serial data signal is SPI standard
Signal, those skilled in the art is it is to be appreciated that for the signal of other standards, the present invention is same
It is suitable for.
In one exemplary embodiment of the present invention, it is proposed that a kind of with line sequence self-adaptive
Serial data signal transmission circuit.As shown in Figure 4, Fig. 4 present invention provide with line sequence self adaptation
The hardware structure schematic diagram of the serial data transmission circuit of function, this serial data signal transmission circuit bag
Include serial data transmitting terminal signal processing module 100 and Serial data receiving end signal processing module
200.Demand is realized according to system, if system is one-way data transfer demand, then can be by Fig. 5 institute
Show and implement transmitting terminal signal processing module and receiving end signal process mould respectively at transmitting terminal and receiving terminal
Block.If system is bidirectional data transfers requirement, all realize institute at side a and b the most as shown in Figure 6
State transmitting terminal signal processing module and receiving end signal processing module.Serial data transmitting terminal in Fig. 4
Signal generation module 300 and Serial data receiving end signal receiver module 400 are showing shown in Fig. 1
There is the ingredient of serial data transmission.
Wherein, serial data transmitting terminal signal processing module 100, its front end and serial data transmitting terminal
Signal generation module 300 connects, and its rear end is connected with serial signal transfer channel, and this module includes string
Row signal mode signal generating unit 101, serial signal transmitting terminal control unit 104, feedback signal reception
Unit 105 and error model identifying unit 106.Wherein:
Serial signal schema creation unit 101, including serial signal cross matrix subelement 103, point
Do not send out with serial data transmitting terminal signal generation module 300, serial signal transfer channel and serial signal
Sending end control unit 104 connects, and is used for receiving serial data transmitting terminal signal generation module 300 and sends
Original serial data signal, receive serial signal transmitting terminal control unit 104 control signal, and
By original serial data signal after its serial signal cross matrix subelement 103 processes, output is
Revise serial data signal.
Serial signal transmitting terminal control unit 104, respectively with serial signal schema creation unit 101,
Error model identifying unit 106 and feedback signal reception unit 105 connect, and are used for receiving feedback signal
Receive the Serial data receiving feedback signal that unit 105 transmits, and be sent to error model judgement
Unit 106, receives the type of error that error model identifying unit 106 returns, according to this type of error
Control the mode of operation of serial signal schema creation unit 101, if type of error is unknown, then serial
Signal sending end control unit 104 serially will send warning by data sending terminal signal generation module 300
Information.
Feedback signal reception unit 105, for Serial data receiving end feedback signal is carried out pretreatment,
And the signal after processing sends serial signal transmitting terminal control unit 104 to.
Error model identifying unit 106, comprises error model storing sub-units 107, with serial signal
Transmitting terminal control unit 104 connects, and receives the mistake that serial signal transmitting terminal control unit 104 sends
Decision request and Serial data receiving end feedback signal, by with in error model storing sub-units 107
The comparison of the model of storage and analysis, analyze current erroneous model, send result to serial signal and send out
Sending end control unit 104.
Serial data receiving end signal processing module 200, its front end is connected with serial signal transfer channel,
Its rear end is connected with Serial data receiving end signal receiver module 400, and this module includes that serial signal connects
Receiving end control unit 201 and feedback signal generating unit 202.Wherein:
Serial signal receiving terminal control unit 201, receives the string of correction on serial signal transfer channel
Row data signal, and this signal is sent to Serial data receiving end signal receiver module 400 and feedback
Signal signal generating unit 202.
Feedback signal generating unit 202, receives the string that serial signal receiving terminal control unit 201 transmits
Row data signal and feedback signal instruction, generate Serial data receiving end feedback signal, and feedback is given in output
Signal receiving unit 105.
The present invention will be described with example embodiments to divide 3 trifles below: " serial data sends
End signal processing module 100 part " and " Serial data receiving end end signal processing module 200 part "
Illustrate the hardware circuit of the present invention, i.e. " a kind of serial data transmitting-receiving described in foregoing summary
Circuit "；" the test generation of signal, feedback and error model determination flow " illustrates that the present invention is in mistake
Flow process in terms of model judgement by mistake, i.e. " a kind of serial data transmitting-receiving control described in foregoing summary
Method processed ".
Serial data transmitting terminal signal processing module 100 part
Serial signal schema creation unit 101, inside comprises serial signal cross matrix subelement 103,
Front end is connected with serial data transmitting terminal signal generation module 300, receives original serial data signal,
Rear end is connected with serial signal transfer channel, (revises for processing original serial data signal
Line sequence) and export revised serial data signal.
Serial signal cross matrix subelement 103, is included in serial signal schema creation unit 101,
Signal cross can be carried out according to the instruction of serial signal transmitting terminal control unit.In the present embodiment,
EN, CLK that port 0,1,2 is respectively defined as in normal transmission and DATA signal.Such as Fig. 8
Shown in, the present invention explains serial signal cross matrix subelement with the signal cross_placing problem in Fig. 3
The method of operation: for four road signals (in order to support three-wire type SPI and four-wire type SPI simultaneously, we
As a example by the more preferable four line cross matrixes of versatility), serial signal transmitting terminal control unit 104 is to string
Row signal mode signal generating unit 101 be given 4 to configuration data, form is as follows: (input port, output
Port), as (2,1) in Fig. 8 i.e. represent from port 2 input signal after matrix by port 1
Output.Serial signal cross matrix subelement 103 operationally reads these configuration data and revises signal
Line sequence, as shown in Figure 8, (DATA Yu CLK believes for the port 1 exchanged by mistake and port 2 signal
Number) revised by serial signal cross matrix subelement 103, revert to correct signal and connect.Serial
Signal cross matrix subelement 103 simultaneously can under the instruction of serial signal transmitting terminal control unit 104
With output serial data test signal, as it is shown in figure 9, the concrete handling process ginseng in present example
See below " the test generation of signal, feedback and error model determination flow " joint.
Serial signal transmitting terminal control unit 104, with feedback signal reception unit 105, serial signal
Schema creation unit 101 is connected with error model identifying unit 106, is used for receiving feedback signal and connects
Receive unit 105 and carry out pretreated feedback signal, and above-mentioned signal is sent to error model judgement
Unit 106, after receiving the return result of error model identifying unit 106, if result is " normally "
Or " known error model ", then press accordingly result configuration modifications serial signal cross matrix subelement 103
Configuration data；If result is " unknown error model ", then serial signal transmitting terminal control unit 104
By serially data sending terminal signal generation module 300 alert.Meanwhile, serial data is sent out
Sending end control unit 104 can also control serial signal schema creation unit 101 and generate serial data survey
Trial signal, as it is shown in figure 9, the concrete handling process in present example see below " test signal
Generation, feedback and error model determination flow " one joint.
Feedback signal reception unit 105, with feedback channel and serial signal transmitting terminal control unit 104
Connect, for receiving the signal on feedback channel, and be serial data transmitting terminal signal by its pretreatment
The manageable signal of each several part in processing module.Such as on feedback channel, signal is 5V Transistor-Transistor Logic level,
And serial data transmitting terminal signal processing module 100 uses 1.8V COMS level, then feedback letter
Number receive unit 105 need the signal sampling in feedback signal and be converted to 1.8V CMOS level
Signal.The most such as on feedback channel, signal and serial data transmitting terminal signal processing module 100 are
1.8V CMOS level, but due to the signal attenuation of feedback channel, it is actually reached feedback signal reception list
When the level of unit 105 only has about 1.2V, feedback signal reception unit 105 will be to channel signal
Sample and re-generate, reverting to the 1.8V CMOS level of standard.
Error model identifying unit 106, is connected with serial signal transmitting terminal control unit 104, receives
The feedback signal of serial signal transmitting terminal control unit 104 transmission and error model decision request, and will
This feedback signal contrasts with the signal in error model storing sub-units 107, draws error model
Result of determination (" normally ", " known error model " or " unknown error model ") and error model generation
Code (particular type of " known error model "), sends serial letter to by this error model result of determination
Number transmitting terminal control unit 104, and be further processed by serial signal transmitting terminal control unit 104.
Error model decision process in present example is as it is shown in figure 9, see below " the product of test signal
Life, feedback and error model determination flow " joint.
Serial data sends out receiving end signal processing module 200 part
Serial signal receiving terminal control unit 201, generates with serial signal transfer channel, feedback signal
Unit 202 and Serial data receiving end signal receiver module 400 connect, for receiving and pretreatment string
The serial data signal of correction on row signal channel is (to level pretreatment mode with described feedback
Signal receiving unit 105), meanwhile, the signal receiving also pretreatment is sent to feedback signal and generates single
Unit 202, and enable feedback signal generating unit 202 and produce Serial data receiving end on the feedback channel
Feedback signal.
Feedback signal generating unit 202, with serial signal receiving terminal control unit 201 and feedback channel
Connect, for receiving data signal and the enable instruction that serial signal receiving terminal control unit 201 transmits,
And generate Serial data receiving end feedback signal on the feedback channel.In order to make serial data transmitting terminal believe
The each unit of number processing module 100 can be with Recognition feedback signal, and feedback signal generating unit 202 needs
In feedback signal, add entry identification signal, be targeting signal in the present example, the life of feedback signal
Become as it is shown in figure 9, see below " the test generation of signal, feedback and error model determination flow "
One joint.
The test generation of signal, feedback and error model determination flow
As it is shown in fig. 7, the serial data transmission circuit with line sequence self-adaptive that the present invention proposes
When carrying out a data transfer, flow process is as follows: first, serial signal transmitting terminal control unit 104
Control serial signal schema creation unit 101 and send test serial data signal (step A)；Connecing
After receiving test signal, it is raw that serial signal receiving terminal control unit 201 transfers data to feedback signal
Become unit 202, and enable feedback signal generating unit 202 and generate serial data on the feedback channel and connect
Receiving end feedback signal, this feedback signal will add indications, identify for feedback signal reception unit 105
(present example uses leading character as indications).Serial signal transmitting terminal control unit 104 exists
Receive after the signal of feedback signal reception unit 105 pretreatment, signal data and request are passed
Giving error model identifying unit 106, error model identifying unit 106 is by this signal data and mistake
Condition code in model storing sub-units 107 is compared, and (" just draws error model result of determination
Often ", " known error model " or " unknown error model " and judge code) return to serial signal
Transmitting terminal control unit 104 (step B)；Serial signal transmitting terminal control unit 104 will be according to judgement
Output control serial signal schema creation unit 101 also sets serial signal cross matrix subelement 103
Configuration data (step C, step D or step E)；Step C, when serial signal transmitting terminal control
After unit 104 processed receives " normally " signal of error model identifying unit 106, control serial letter
Original serial data signal is conveyed directly to serial signal transfer channel by number schema creation unit 101；
Step D, when serial signal transmitting terminal control unit 104 receives error model identifying unit 106
After " known error model " signal, control serial signal schema creation unit 101 and enter by AD HOC
The demonstration of row signal and signal cross, the signal after processing is sent to serial signal transfer channel；Step
E, when serial signal transmitting terminal control unit 104 receive error model identifying unit 106 " not
Know error model " after signal, serially data sending terminal signal generation module 300 alert
And wait processes instruction further.
Fig. 9 illustrates to test the generation of signal, feedback and error model determination flow with concrete example.
As it is shown in figure 9, in a data transfer at first, serial signal transmitting terminal control unit 104
Control serial signal schema creation unit 101 on serial signal transfer channel, produce test signal, this
Test signal in embodiment is Binary Zero b01011010 (hexadecimal 0x5A), and serial signal connects
It is raw that signal and enable order are sent to feedback unit after receiving test signal by receiving end control unit 201
Become unit 202, feedback unit signal generating unit 202 feedback data the most front addition 2bit leading character (when
For 0b01 in front embodiment) as indications and using the front 8bit that receives as feedback signal leading
Once export after symbol.
If current line sequence is correct, then the 10bit data adding leading character are followed successively by: " 0 ", " 1 ", " 0 ",
" 1 ", " 0 ", " 1 ", " 1 ", " 0 ", " 1 ", " 0 ", (after removing 2bit leading character, numerical value is
0x5A)。
If current line sequence occurs in that EN as shown in Figure 2 and the mistake of DATA signal mistake exchange,
The 10bit data then adding leading character are followed successively by: " 0 ", " 1 ", " 1 ", " 1 ", " 1 ", " 1 ", " 1 ",
" 1 ", " 1 ", " 1 ", (after removing 2bit leading character, numerical value is 0xFF).
If current line sequence occurs in that CLK as shown in Figure 3 and the mistake of DATA signal mistake exchange,
The 10bit data then adding leading character are followed successively by: " 0 ", " 1 ", " 0 ", " 0 ", " 0 ", " 0 ", " 0 ",
" 0 ", " 0 ", " 0 ", (after removing 2bit leading character, numerical value is 0x00).
If first EN signal of test signal is not correctly sampled, first " 0 " is caused not have
Be sampled, the most then the 10bit data adding leading character are followed successively by: " 0 ", " 1 ", " 1 ", " 0 ", " 1 ",
" 1 ", " 0 ", " 1 ", " 0 ", " 0 ", such as " unknown error " that indicate in Fig. 9, (remove before 2bit
After leading symbol, numerical value is 0xB8).
Feedback signal reception unit 105 is receiving the feedback signal of feedback channel and is confirming leading character
After, remaining 8bit will be decoded and be sent to serial signal transmitting terminal control unit 104, string
Row signal sending end control unit 104 judges single by the data value of remaining 8bit is sent to error model
Unit 106, error model identifying unit 106 is by the spy in this data value and error model storing sub-units
Levy code compare and draw result of determination.If as it is shown in figure 9, fed back values is 0x5A, then sentencing
Being set to " normally ", serially signal sending end control unit 104 returns and judges code " 0 ", represents
" normally "；If fed back values is 0x00, being then judged to " known error model ", serially signal is sent out
Sending end control unit 104 returns and judges code " 1 ", represents " known error model, CLK/DATA
Signal error exchanges "；If fed back values is 0xFF, then it is judged to " known error model ", to string
Row signal sending end control unit 104 returns and judges code " 2 ", represents " known error model, EN
/ DATA signal mistake exchanges "；If fed back values is other values, then it is judged to " unknown error model ",
Serially signal sending end control unit 104 returns and judges code " 4 ", represents " unknown error model "；
According to the result of determination of error model identifying unit 106, serial signal transmitting terminal control unit
104 pairs of Different Results make different disposal:
If it is determined that result is " normally " (judging code " 0 "), then by serial signal cross matrix list
After the configuration numerical value of unit 103 is configured to ((0,0), (1,1), (2,2), (3,3)) and continues
Continuous data transmission；
If it is determined that result is " known error model, CLK/DATA signal error exchanges " (judges generation
Code " 1 "), then the configuration numerical value of serial signal cross matrix subelement 103 is configured to ((0,0),
(1,2), (2,1), (3,3)) and continue subsequent data transmission, as described in described Fig. 8；
With CLK/DATA signal error exchange similar, if it is determined that result be " known error model,
EN/DATA signal error exchanges " (judging code " 2 "), then by serial signal cross matrix list
After the configuration numerical value of unit 103 is configured to ((0,2), (1,1), (2,0), (3,3)) and continues
Continuous data transmission；
If it is determined that result is " unknown error model " (judging code " 4 "), then raw to transmitting terminal signal
Module 300 is become to report to the police.
In sum, the present invention provide the serial data transmission circuit with line sequence self-adaptive and
Its control method, is not only able to preferably detect the line sequence mistake due in serial signal transfer, and
Data transmit-receive two ends can be made correctly to be transmitted data with self-adaptative adjustment serial signal line sequence.With
Time the present invention have preferable versatility, can apply to various wired or wireless wait in transmission channel each
Plant standard serial data transmission.
Particular embodiments described above, is carried out the purpose of the present invention, technical scheme and beneficial effect
Further describe, be it should be understood that the foregoing is only the present invention specific embodiment and
, be not limited to the present invention, all within the spirit and principles in the present invention, that is done any repaiies
Change, equivalent, improvement etc., should be included within the scope of the present invention.
Claims (8)
1. the serial data transmission circuit with line sequence self-adaptive, it is characterised in that should
Circuit includes at serial data transmitting terminal signal processing module (100) and Serial data receiving end signal
Reason module (200), wherein, this serial data transmitting terminal signal processing module (100) front end and string
Row data sending terminal signal generation module (300) connects, and rear end is connected with serial signal transfer channel；
This Serial data receiving end signal processing module (200) front end is connected with serial signal transfer channel,
Rear end is connected with Serial data receiving end signal receiver module (400)；
Wherein, described serial data transmitting terminal signal processing module (100) includes serial signal pattern
Signal generating unit (101), serial signal transmitting terminal control unit (104), feedback signal reception unit (105)
With error model identifying unit (106), wherein, serial signal schema creation unit (101) is respectively
Send out with serial data transmitting terminal signal generation module (300), serial signal transfer channel and serial signal
Sending end control unit (104) connect, serial signal transmitting terminal control unit (104) respectively with serial
Signal mode signal generating unit (101), error model identifying unit (106) and feedback signal reception list
Unit (105) connects；
Described serial signal transmitting terminal control unit (104) is used for receiving feedback signal reception unit (105)
The Serial data receiving feedback signal transmitted, and it is sent to error model identifying unit (106),
Receive the type of error that error model identifying unit (106) returns, control string according to this type of error
The mode of operation of row signal mode signal generating unit (101), if type of error is unknown, then serial letter
Number transmitting terminal control unit (104) will serially send by data sending terminal signal generation module (300)
Warning message.
Serial data transmission circuit with line sequence self-adaptive the most according to claim 1,
It is characterized in that, described serial signal schema creation unit (101), including serial signal cross matrix
Subelement (103), is used for receiving that serial data transmitting terminal signal generation module (300) sends is former
Beginning serial data signal, receives the control signal of serial signal transmitting terminal control unit (104), and
By original serial data signal after its serial signal cross matrix subelement (103) processes, defeated
Go out and revise serial data signal.
Serial data transmission circuit with line sequence self-adaptive the most according to claim 2,
It is characterized in that, described serial signal cross matrix subelement (103) is for sending out according to serial signal
The instruction of sending end control unit carries out signal cross.
Serial data transmission circuit with line sequence self-adaptive the most according to claim 1,
It is characterized in that, described feedback signal reception unit (105) is for feeding back Serial data receiving end
Signal carries out pretreatment, and the signal after processing sends serial signal transmitting terminal control unit to
(104)。
Serial data transmission circuit with line sequence self-adaptive the most according to claim 1,
It is characterized in that described error model identifying unit (106) comprises error model storing sub-units
(107), it is used for receiving the wrong decision request that serial signal transmitting terminal control unit (104) sends
And Serial data receiving end feedback signal, by storing in error model storing sub-units (107)
The comparison of model and analysis, analyze current erroneous model, result sent to serial signal transmitting terminal
Control unit (104).
Serial data transmission circuit with line sequence self-adaptive the most according to claim 1,
It is characterized in that, described Serial data receiving end signal processing module (200) including:
Serial signal receiving terminal control unit (201), has been used for receiving on serial signal transfer channel
Revise serial data signal, and this signal is sent to Serial data receiving end signal receiver module (400)
With feedback signal generating unit (202), and enable feedback signal generating unit (202) in feedback letter
Serial data receiving end feedback signal is produced on road；
Feedback signal generating unit (202), is used for receiving serial signal receiving terminal control unit (201)
The serial data signal transmitted and feedback signal instruction, generate Serial data receiving end feedback signal, defeated
Go out to feedback signal reception unit (105).
Serial data transmission circuit with line sequence self-adaptive the most according to claim 6,
It is characterized in that, described feedback signal generating unit (202) adds in the feedback signal generated to be known
Level signal.
8. a serial data receiving and sending control method, is applied to institute any one of claim 1 to 7
The serial data transmission circuit with line sequence self-adaptive stated, it is characterised in that the method includes:
Step A: serial signal transmitting terminal control unit (104) controls serial signal schema creation list
Unit (101) sends test serial data signal；
Step B: serial signal transmitting terminal control unit (104) receives Serial data receiving end feedback
Signal also sends decision request and data to error model identifying unit (106)；
Step C, judges single when serial signal transmitting terminal control unit (104) receives error model
After " normally " signal of unit (106), control serial signal schema creation unit (101) by original
Serial data signal is conveyed directly to serial signal transfer channel；
Step D, judges single when serial signal transmitting terminal control unit (104) receives error model
After " known error model " signal of unit (106), control serial signal schema creation unit (101)
Carrying out signal demonstration and signal cross by AD HOC, the signal after processing is sent to serial signal and passes
Defeated channel；
Step E, judges single when serial signal transmitting terminal control unit (104) receives error model
After " unknown error model " signal of unit (106), serially data sending terminal signal generation module
(300) alert wait process instruction further.
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| CN201210229095.5A CN103532686B (en) | 2012-07-03 | 2012-07-03 | Serial data transmission circuit and control method thereof with line sequence self-adaptive |
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| CN103532686B true CN103532686B (en) | 2016-09-28 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104199795B (en) * | 2014-09-15 | 2017-02-08 | 活点信息技术有限公司 | Data transferring and receiving method of bus framework |
| CN108347393B (en) * | 2017-01-22 | 2020-11-06 | 华为技术有限公司 | Method, equipment and system for processing crossed line sequence |
| CN110166082B (en) * | 2019-04-01 | 2021-07-02 | 深圳市速腾聚创科技有限公司 | Magnetic ring line sequence self-adaption method, device, equipment and storage medium |
| CN111158335B (en) * | 2019-11-19 | 2021-08-20 | 潍柴动力股份有限公司 | Stitch function matching method of multi-ECU system and storage medium |
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|---|---|---|---|---|
| US6275526B1 (en) * | 1997-08-28 | 2001-08-14 | Samsung Electronics Ltd. | Serial data communication between integrated circuits |
| CN2634731Y (en) * | 2003-07-15 | 2004-08-18 | 上海长达信息科技有限公司 | Digital signal transmission device |
| CN1967513A (en) * | 2005-11-18 | 2007-05-23 | 群康科技(深圳)有限公司 | Data signal transmission system and method |
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2012
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6275526B1 (en) * | 1997-08-28 | 2001-08-14 | Samsung Electronics Ltd. | Serial data communication between integrated circuits |
| CN2634731Y (en) * | 2003-07-15 | 2004-08-18 | 上海长达信息科技有限公司 | Digital signal transmission device |
| CN1967513A (en) * | 2005-11-18 | 2007-05-23 | 群康科技(深圳)有限公司 | Data signal transmission system and method |
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