CN108347393B

CN108347393B - Method, equipment and system for processing crossed line sequence

Info

Publication number: CN108347393B
Application number: CN201710054156.1A
Authority: CN
Inventors: 刘建华; 陈仕才
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2017-01-22
Filing date: 2017-01-22
Publication date: 2020-11-06
Anticipated expiration: 2037-01-22
Also published as: CN108347393A

Abstract

The application provides a method, a device and a system for processing a cross line sequence, when a first device and a second device adopt a plurality of twisted-pair connections with the cross line sequence, the first device may adjust a position of a subsequence in the first signal sequence to be transmitted according to a line sequence relationship of a plurality of twisted wire pairs connected to a plurality of logical ports of the second device to obtain a second signal sequence, so that the first device and the second device can transmit training signal sequences based on the mode, so that the first signal sequence transmitted by the device as the transmitting side in the first device and the second device is the same as the signal sequence received by the device as the receiving side, and further, the determined channel transmission matrixes H are the same on the basis of the same signal sequence, so that the technical problem that the MIMO technology cannot be applied to the first equipment and the second equipment which are connected by adopting a cross line sequence is solved.

Description

Method, equipment and system for processing crossed line sequence

Technical Field

The present application relates to communications technologies, and in particular, to a method, a device, and a system for processing a cross line sequence.

Background

A Digital Subscriber Line (DSL) system is a broadband access system that uses a telephone twisted pair (twisted pair for short) to transmit data. Common DSL systems are: asymmetric Digital Subscriber Line (ADSL), Very-High-bit-rate Digital Subscriber Line (VDSL), Very-High-speed Digital Subscriber Line 2 (VDSL 2), integrated services Digital Network Digital Subscriber Line (ISDN IDSL), Single-wire-to-High-speed Digital Subscriber Line (SHDSL), and so on.

The above xDSL system includes: a plurality of Remote Transmission units (xTU-Rs), an Office Transmission Unit (xTU-Office) corresponding to each xTU-Rs, a core switch, etc. Wherein the core switch is connected to the xTU-Rs through the xTU-Os. Currently, when multiple xTU-Rs are all located on the same user side, the multiple xTU-Rs may be located on the same user side device (CPE). Accordingly, a plurality of xTU-Os corresponding to the plurality of xTU-Rs may be disposed on the same Digital Subscriber Line Access Multiplexer (DSLAM). The DSLAM may be located in a Central Office (CO) or a Distributed Processing Unit (DPU) of the xDSL system.

In the prior art, the DSLAM and the CPE may be connected by a network cable including a plurality of twisted wire pairs, so that one xTU-Os on the DSLAM may be connected with one xTU-Rs on the CPE by one twisted wire pair. When the DSLAM transmits signals with the CPE, in order to avoid far-end crosstalk caused by the signals transmitted by each twisted pair in the network cable to the signals transmitted by other twisted pairs, the DSLAM and the CPE may eliminate the far-end crosstalk through a Multiple-Input Multiple-Output (MIMO) technology. Taking the sender as a DSLAM and the receiver as a CPE as an example, the DSLAM may perform precoding processing on the sent signal through a channel transmission matrix, and accordingly, the CPE may perform post-coding processing on the received signal through the channel transmission matrix to eliminate far-end crosstalk and ensure the quality of the transmitted signal. The channel transmission matrix used by the DSLAM may be determined by the DSLAM according to a line sequence of a plurality of twisted pairs in a network line connected to the DSLAM, and the channel transmission matrix used by the CPE may be determined by the CPE according to a line sequence of a plurality of twisted pairs in a network line connected to the CPE. If the twisted pair wires in the network cable are connected to the DSLAM and the CPE in different wire orders, the channel transmission matrices determined by the DSLAM and the CPE are different, so that the DSLAM and the CPE use the MIMO technology and cannot correctly transmit signals.

Disclosure of Invention

The application provides a method, equipment and a system for processing a cross line sequence, which are used for solving the technical problem that the MIMO technology cannot be applied to DSLAM and CPE which adopt cross line sequence connection.

A first aspect provides a method for processing a cross-line order, the method is applied to a first device and a second device in a MIMO system, a physical port of the first device is connected to a physical port of the second device through a plurality of twisted wire pairs, each of the physical port of the first device and the physical port of the second device includes a plurality of logical ports, the plurality of twisted wire pairs connect a plurality of logical ports of the first device in a first line order, and the plurality of twisted wire pairs connect a plurality of logical ports of the second device in a second line order; the method comprises the following steps: the first equipment acquires the mapping relation between a plurality of logical ports of the first equipment and a plurality of logical ports of the second equipment; the first equipment determines whether the first line sequence and the second line sequence are crossed or not according to the mapping relation; and when the first equipment crosses the second line sequence, adjusting the position of a subsequence in a first signal sequence to be transmitted by the first equipment according to the second line sequence to obtain a second signal sequence.

By the processing method of the cross line sequence, when the first device and the second device adopt a plurality of twisted pairs with the cross line sequence for connection, the first device may adjust a position of a subsequence in the first signal sequence to be transmitted according to a line sequence relationship of a plurality of twisted wire pairs connected to a plurality of logical ports of the second device to obtain a second signal sequence, so that the first device and the second device can transmit training signal sequences based on the mode, so that the first signal sequence transmitted by the device as the transmitting side in the first device and the second device is the same as the signal sequence received by the device as the receiving side, and further, the determined channel transmission matrixes H are the same on the basis of the same signal sequence, so that the technical problem that the MIMO technology cannot be applied to the first equipment and the second equipment which are connected by adopting a cross line sequence is solved.

Optionally, the obtaining, by the first device, a mapping relationship between a plurality of logical ports of the first device and a plurality of logical ports of the second device includes: the first device obtains a third signal sequence according to signals, received from the plurality of logical ports of the first device, sent by the second device through the plurality of logical ports of the second device; and the first device determines the mapping relation between the plurality of logical ports of the first device and the plurality of logical ports of the second device according to the third signal sequence.

By the processing method for the cross line sequence provided by this possible embodiment, when the first device and the second device are connected by using a plurality of twisted pairs with the cross line sequence, the first device may obtain a third signal sequence according to signals received at a plurality of logic ports of the first device and sent by the second device through a plurality of logic ports of the second device, so that the first device determines a mapping relationship between the plurality of logic ports of the first device and the plurality of logic ports of the second device according to the third signal sequence, and further, the first device may determine whether a first line sequence connected to the first device and a second line connected to the second device cross each other by using the plurality of twisted pairs based on the mapping relationship, so that the first device may adjust the first signal sequence to be transmitted according to the second line sequence when the first line sequence and the second line sequence cross each other, therefore, the first signal sequence sent by the equipment serving as the sender in the first equipment and the second equipment is the same as the signal sequence received by the equipment serving as the receiver, and the technical problem that the MIMO technology cannot be applied to the first equipment and the second equipment which are connected by adopting the cross line sequence is solved.

Optionally, the signals sent by the second device through the plurality of logical ports of the second device are signals in a preset signal sequence, and the signals sent by the logical ports are different; the determining, by the first device, a mapping relationship between a plurality of logical ports of the first device and a plurality of logical ports of the second device according to the third signal sequence includes: and the first device determines the mapping relationship between the plurality of logical ports of the first device and the plurality of logical ports of the second device according to the third signal sequence and the preset signal sequence.

For example, the determining, by the first device, a mapping relationship between a plurality of logical ports of the first device and a plurality of logical ports of the second device according to the third signal sequence and the preset signal sequence includes: the first device performs correlation operation on each signal in the third signal sequence and each signal in the preset signal sequence, and determines a signal in the preset signal sequence which has the highest correlation with each signal in the third signal sequence; and the first device determines the mapping relationship between the plurality of logical ports of the first device and the plurality of logical ports of the second device according to the logical port of the second device corresponding to the signal with the highest correlation with each signal in the third signal sequence in the preset signal sequence and the logical port of the first device corresponding to each signal in the third signal sequence.

Optionally, the signal sent by the second device through each logical port of the second device is an identifier of each logical port; the determining, by the first device, a mapping relationship between a plurality of logical ports of the first device and a plurality of logical ports of the second device according to the third signal sequence includes: the first device analyzes the third signal sequence to obtain the identifier of the logical port of the second device, which is received by each logical port of the first device; the first device determines a mapping relationship between a plurality of logical ports of the first device and a plurality of logical ports of the second device according to the identifiers of the logical ports of the second device, which are received by the logical ports of the first device.

Optionally, the obtaining, by the first device, a mapping relationship between a plurality of logical ports of the first device and a plurality of logical ports of the second device includes:

and the first equipment receives the mapping relation sent by the second equipment.

With the processing method of the cross line order provided by this possible embodiment, when the first device and the second device use a plurality of twisted pair connections with the cross line order, the first device may obtain the mapping relationship by receiving the mapping relationship sent by the second device, and further enabling the first device to determine whether a first wire sequence connecting the first device and a second wire sequence connecting the second device are crossed by a plurality of twisted wire pairs based on the mapping relation, so that when the first wire sequence and the second wire sequence are crossed, adjusting the first signal sequence to be transmitted according to the second wire sequence, so that the first signal sequence sent by the device serving as the sender in the first device and the second device, and the signal sequence received by the equipment as the receiving party is the same, so that the technical problem that the MIMO technology cannot be applied to the first equipment and the second equipment which are connected by adopting the cross line sequence is solved.

Further, when the first device is a receiver, the second device is a sender, and the first signal sequence is a training signal sequence, and when the first line sequence crosses the second line sequence, the first device adjusts, according to the second line sequence, a position of a subsequence in the first signal sequence to be transmitted by the first device, so as to obtain a second signal sequence, and the method further includes: and the first equipment determines a channel transmission matrix according to the second signal sequence.

By the method for processing the cross line sequence provided by the possible embodiment, when the first device and the second device are connected by using a plurality of twisted pairs with the cross line sequence, the first device may adjust the position of the subsequence in the training signal sequence to be transmitted according to the line sequence relationship of the plurality of twisted pairs connected to the plurality of logic ports of the second device to obtain the second signal sequence, so that the second signal sequence obtained by the first device is the same as the training signal sequence sent by the second device to the first device, and further, based on the training signal sequence, the first device determines the channel transmission matrix H to be the same as the channel transmission matrix H determined by the second device, thereby solving the technical problem that the MIMO technology cannot be applied to the first device and the second device connected by using the cross line sequence.

A second aspect provides a cross-line order processing device, where the device is a first device in a multiple-input multiple-output MIMO system, and the MIMO system further includes a second device, and a physical port of the first device is connected to a physical port of the second device through a plurality of twisted wire pairs, where the physical port of the first device and the physical port of the second device each include a plurality of logical ports, the plurality of twisted wire pairs connect a plurality of logical ports of the first device in a first line order, and the plurality of twisted wire pairs connect a plurality of logical ports of the second device in a second line order; the first device further comprises: an obtaining module, configured to obtain mapping relationships between multiple logical ports of the first device and multiple logical ports of the second device; a first determining module, configured to determine whether the first thread sequence and the second thread sequence cross according to the mapping relationship; and the adjusting module is used for adjusting the position of a subsequence in a first signal sequence to be transmitted by the first equipment according to the second line sequence when the first line sequence and the second line sequence are crossed to obtain a second signal sequence.

Optionally, the obtaining module includes: the processing unit is configured to obtain a third signal sequence according to signals, which are received at the multiple logical ports of the first device and sent by the second device through the multiple logical ports of the second device; a determining unit, configured to determine, according to the third signal sequence, a mapping relationship between the multiple logical ports of the first device and the multiple logical ports of the second device.

Optionally, the signals sent by the second device through the plurality of logical ports of the second device are signals in a preset signal sequence, and the signals sent by the logical ports are different; the determining unit is specifically configured to determine, according to the third signal sequence and the preset signal sequence, a mapping relationship between the plurality of logical ports of the first device and the plurality of logical ports of the second device.

For example, the determining unit is specifically configured to perform a correlation operation on each signal in the third signal sequence and each signal in the preset signal sequence, and determine a signal in the preset signal sequence that has the highest correlation with each signal in the third signal sequence; and determining mapping relationships between the plurality of logic ports of the first device and the plurality of logic ports of the second device according to the logic port of the second device corresponding to the signal with the highest correlation with each signal in the third signal sequence in the preset signal sequence and the logic port of the first device corresponding to each signal in the third signal sequence.

Optionally, the signal sent by the second device through each logical port of the second device is an identifier of each logical port; the determining unit is specifically configured to analyze the third signal sequence to obtain an identifier of a logical port of the second device, where the identifier is received by each logical port of the first device; and determining the mapping relationship between the plurality of logical ports of the first device and the plurality of logical ports of the second device according to the received identifiers of the logical ports of the second device from the logical ports of the first device.

Optionally, the obtaining module is specifically configured to receive the mapping relationship sent by the second device.

Further, the first device is a receiver, the second device is a sender, and the first signal sequence is a training signal sequence; the first device further comprises: and the second determining module is used for determining a channel transmission matrix according to the second signal sequence after the adjusting module adjusts the position of the subsequence in the first signal sequence to be transmitted by the first device according to the second sequence.

The beneficial effects of the processing device for the cross line sequence provided by the second aspect and each possible implementation manner of the second aspect may refer to the beneficial effects brought by each possible implementation manner of the first aspect and the first aspect, and are not described herein again.

A third aspect provides a cross-line order processing device, where the device is a first device in a multiple-input multiple-output MIMO system, and the MIMO system further includes a second device, and a physical port of the first device is connected to a physical port of the second device through a plurality of twisted wire pairs, where the physical port of the first device and the physical port of the second device each include a plurality of logical ports, the plurality of twisted wire pairs connect a plurality of logical ports of the first device in a first line order, and the plurality of twisted wire pairs connect a plurality of logical ports of the second device in a second line order; the first device further comprises: a processor and a memory, the processor and the memory being connected by a bus; wherein the memory is to store computer-executable program code, the program code comprising instructions; when executed by the processor, the instructions cause the first device to perform the method provided by the first aspect of the present application.

The beneficial effects of the processing apparatus for the cross line sequence provided by the third aspect and each possible implementation manner of the third aspect may refer to the beneficial effects brought by each possible implementation manner of the first aspect and the first aspect, and are not described herein again.

A fourth aspect provides a cross-line order processing system, where the cross-line order processing system is a multiple-input multiple-output MIMO system, and the MIMO system includes: the physical port of the first device and the physical port of the second device are connected through a plurality of twisted wire pairs, wherein the physical port of the first device and the physical port of the second device both comprise a plurality of logical ports, the plurality of twisted wire pairs are connected with the plurality of logical ports of the first device in a first line order, and the plurality of twisted wire pairs are connected with the plurality of logical ports of the second device in a second line order; the first device is configured to obtain mapping relationships between a plurality of logical ports of the first device and a plurality of logical ports of the second device; determining whether the first line sequence and the second line sequence are crossed or not according to the mapping relation; and when the first line sequence and the second line sequence are crossed, adjusting the position of a subsequence in a first signal sequence to be transmitted by the first equipment according to the second line sequence to obtain a second signal sequence.

Further, when the first device is a receiver, the second device is a sender, and the first signal sequence is a training signal sequence, the first device is further configured to adjust, according to the second line sequence, a position of a subsequence in the first signal sequence to be transmitted by the first device when the first line sequence crosses the second line sequence, to obtain a second signal sequence, and then determine a channel transmission matrix according to the second signal sequence.

The beneficial effects of the processing system for the cross line sequence provided by the fourth aspect and each possible implementation manner of the fourth aspect may refer to the beneficial effects brought by each possible implementation manner of the first aspect and the first aspect, and are not described herein again.

A fifth aspect provides a cross-line sequential processing apparatus comprising at least one processing element (or chip) for performing the method of the first aspect above.

In a sixth aspect, the present application further provides a computer-readable storage medium comprising: instructions which, when run on a computer, cause the computer to perform the method of cross-line order processing provided in the first aspect above.

In a seventh aspect, the present application also provides a computer program product including instructions, which when run on a computer, causes the computer to execute the method for processing the cross-line order provided in the first aspect.

According to the processing method, the device and the system for the cross line sequence provided by the application, when the first device and the second device adopt a plurality of twisted-pair connections with the cross line sequence, the first device may adjust a position of a subsequence in the first signal sequence to be transmitted according to a line sequence relationship of a plurality of twisted wire pairs connected to a plurality of logical ports of the second device to obtain a second signal sequence, so that the first device and the second device can transmit training signal sequences based on the mode, so that the first signal sequence transmitted by the device as the transmitting side in the first device and the second device is the same as the signal sequence received by the device as the receiving side, and further, the determined channel transmission matrixes H are the same on the basis of the same signal sequence, so that the technical problem that the MIMO technology cannot be applied to the first equipment and the second equipment which are connected by adopting a cross line sequence is solved.

Drawings

Fig. 1 is a schematic diagram of a direct network cable provided in the present application;

fig. 2 is a schematic diagram of a cross-grid provided in the present application;

fig. 3 is a schematic flow chart of a cross line sequence processing method provided in the present application;

FIG. 4 is a schematic flow chart of another cross line order processing method provided in the present application;

FIG. 5 is a schematic structural diagram of a cross-line sequence processing apparatus provided in the present application;

FIG. 6 is a schematic diagram of another cross-line order processing apparatus provided herein;

FIG. 7 is a schematic structural diagram of another cross-line sequence processing apparatus provided in the present application;

FIG. 8 is a schematic structural diagram of another cross-line order processing apparatus provided in the present application;

fig. 9 is a schematic structural diagram of a cross-line processing system according to the present application.

Detailed Description

In the prior art, a physical port of a DSLAM and a physical port of a CPE in an xDSL system are connected by a plurality of twisted pairs, where the plurality of twisted pairs may be a plurality of twisted pairs arranged in the same network cable or a plurality of twisted pairs bound together. The following document describes an example in which a physical port of a DSLAM is connected to a physical port of a CPE via a network cable including 4 twisted wire pairs.

The physical ports of the DSLAM include 4 logical ports, which are assumed to be TXP1, TXP2, TXP3, TXP4, respectively. For the interior of the DSLAM, each logical port corresponds to one xTU-Os in the DSLAM, and for a network wire connected with the DSLAM, each logical port corresponds to one twisted wire pair of the network wire. Accordingly, the physical ports of the CPE include 4 logical ports, which are assumed to be RXP1, RXP2, RXP3, RXP4, respectively. For the interior of the CPE, each logical port corresponds to one xTU-Rs in the CPE, and for the network cable connected to the CPE, each logical port corresponds to one twisted pair of the network cable. In this way, each xTU-Rs located on the CPE can be connected to one xTU-Os on the DSLAM via one twisted pair.

The channel transmission matrix H corresponding to the DSLAM and the channel transmission matrix H corresponding to the CPE may be shown in the following formula (1), for example:

wherein h is_ijThe transmission equation for twisted pair j to twisted pair i is shown. i. j is a positive integer of 4 or less. When h is generated_ijWhen j and i are different, h is_ijIndicating far-end crosstalk caused by twisted pair j to twisted pair i.

According to the H-channel transmission matrix, when the DSLAM and the CPE transmit signals through the network cable, the signal transmitted by each twisted pair in the network cable may cause far-end crosstalk to the signals transmitted by other twisted pairs. Therefore, to ensure the quality of the transmitted signal, the DSLAM and CPE can eliminate the far-end crosstalk by a Multiple-Input Multiple-Output (MIMO) technique, so that j and i in the H matrix are different from H_ijIs 0. The DSL system that employs the MIMO technique to eliminate far-end crosstalk may be referred to as the MIMO system.

Taking the sender and the receiver as an example, how the DSLAM and the CPE eliminate the far-end crosstalk by the MIMO technology will be described. The sender may be a DSLAM and the receiver may be a CPE, or the sender may be a CPE and the receiver may be a DSLAM.

The transmit signal sequence x is represented as a 4 x1 channel input vector. That is, the transmission signal sequence includes 4 sub-sequences, wherein each sub-sequence may be a signal transmitted from one logical port of the transmitting side to the receiving side. The permutation sequence of the 4 subsequences in the transmission signal sequence is the same as the permutation sequence of the logical ports of the subsequence transmitted by the transmitting side. The received signal sequence y is represented as a 4 x1 channel output vector. That is, the received signal sequence includes 4 sub-sequences, where each sub-sequence may be a signal received by one logical port of the receiving side, and an arrangement order of the 4 sub-sequences in the received signal sequence is the same as an arrangement order of the logical ports of the receiving side receiving the sub-sequences. n is a 4 x1 noise vector. The channel transmission equation between the sender and the receiver can be expressed as the following equation (2):

y＝Hx+n (2)

the sender may introduce a precoding matrix P, so that when the sender sends a signal sequence, the sender may perform precoding processing on a transmission signal sequence x to transmit a precoded transmission signal sequence

And sending the data to a channel. The

Can be expressed by the following formula (3):

the receiving party can introduce a crosstalk cancellation matrix W, so that the receiving party can perform post-coding processing on the received signal sequence y when receiving the signal sequence to obtain a post-coded received signal sequence

The

Can be expressed by the following formula (4):

when the above formula (3) is substituted into the above formula (2), and the above formula (2) is substituted into the above formula (4), the above formula (4) can be further represented by the following formula (5):

to enable H in the matrix H to be other than the diagonal_ijAre all 0, i.e. in order to make j and i different H in the H matrix_ijIs 0. The above-mentioned matrices W and P may be some form of decomposition of the channel transmission matrix H (e.g. of the typeSingular value decomposition, etc.) so that after WHP is multiplied, j and i are different by h_ijAll are 0, thereby eliminating far-end crosstalk caused by the twisted pair j to the twisted pair i and ensuring the transmission quality of signals.

The matrix P used by the sender is a matrix obtained by decomposing the sender according to the channel transmission matrix H, and the matrices W and P used by the receiver are matrices obtained by decomposing the receiver according to the channel transmission matrix H. Therefore, in order to correctly receive the signal, the same channel transmission matrix H needs to be used when the transmitting side and the receiving side process the signal.

Currently, the transmitting side may determine the channel transmission matrix H according to the line order of the twisted wire pairs connected to the 4 logical ports thereof, and accordingly, the receiving side may determine the channel transmission matrix H according to the line order of the twisted wire pairs connected to the 4 logical ports thereof. When the network cable connecting the physical port of the sender and the physical port of the receiver is a direct network cable, that is, the line sequence of the 4 twisted wire pairs at the two ends of the network cable is the same, that is, the 4 twisted wire pairs do not cross inside the network cable. At this time, the line order used when the 4 twisted pairs are connected to the 4 logical ports of the sender is the same as the line order used when the 4 twisted pairs are connected to the 4 logical ports of the receiver.

Fig. 1 is a schematic diagram of a direct connection network cable provided in the present application. As shown in fig. 1, taking a 568B standard crystal head as an example for both ends of a direct connection network line, the twisted pair in the direct connection network line has the sequence of orange white, orange, green white, blue white, green, brown white, and brown. Taking the sender as a DSLAM and the receiver as a CPE as an example, an orange twisted pair (i.e., orange white and orange) at one end of the direct connection network line corresponds to the logical port TXP1 of the sender, a blue twisted pair (i.e., green white and blue) corresponds to the logical port TXP2 of the sender, a green twisted pair (i.e., blue white and green) corresponds to the logical port TXP3 of the sender, and a brown twisted pair (i.e., brown white and brown) corresponds to the logical port TXP4 of the sender. The orange twisted pair (orange white and orange) at the other end of the direct connection network wire corresponds to a logic port RXP1 of a receiver, the blue twisted pair (green white and blue) corresponds to a logic port RXP2 of a receiver, the green twisted pair (blue white and green) corresponds to a logic port RXP3 of a receiver, and the brown twisted pair (brown white and brown) corresponds to a logic port RXP4 of a receiver.

When the network cable connects the sender and the receiver by using the same wire sequence, a signal sent by the logical port TXP1 of the sender may be received by the logical port RXP1 of the receiver, a signal sent by the logical port TXP2 of the sender may be received by the logical port RXP2 of the receiver, a signal sent by the logical port TXP3 of the sender may be received by the logical port RXP3 of the receiver, and a signal sent by the logical port TXP4 of the sender may be received by the logical port RXP4 of the receiver. That is, the mapping relationship between the logical port of the sender and the logical port of the receiver is as follows: the sender TXP1 corresponds to the receiver RXP1, the sender TXP2 corresponds to the receiver RXP2, the sender TXP3 corresponds to the receiver RXP3, and the sender TXP4 corresponds to the receiver RXP 4.

At this time, the channel transmission matrix H determined by the transmitting side in the line order of the 4 twisted pairs of the network line connected to its physical port is the same as the channel transmission matrix H determined by the receiving side in the line order of the 4 twisted pairs of the network line connected to its physical port, and the channel transmission matrix may be expressed by the following equation (6):

when the network cable connecting the physical port of the transmitting side and the physical port of the receiving side is a cross network cable, that is, the line sequence of the 4 twisted wire pairs at both ends of the network cable is different, that is, the 4 twisted wire pairs are crossed inside the network cable. At this time, the 4 twisted pairs are connected to the 4 logical ports of the transmitting side in a different line order from the 4 twisted pairs connected to the 4 logical ports of the receiving side.

Fig. 2 is a schematic diagram of a cross-grid provided in the present application. As shown in fig. 2, taking an example that the 568B standard crystal head is used at one end of the cross mesh wire and the 568A standard crystal head is used at the other end, the sequence of the twisted pair at one end of the cross mesh wire is orange white, orange, green white, blue white, green, brown white, brown, and the sequence of the twisted pair at the other end of the cross mesh wire is green white, green, orange white, blue white, orange, brown white, and brown. Assuming that one end of the cross-net line is connected to the sender and the other end of the cross-net line is connected to the receiver, taking the sender as DSLAM and the receiver as CPE as examples, the orange twisted pair (i.e., orange white and orange) at one end of the cross-net line corresponds to the logical port TXP1 of the sender, the blue twisted pair (i.e., green white and blue) corresponds to the logical port TXP2 of the sender, the green twisted pair (i.e., blue white and green) corresponds to the logical port TXP3 of the sender, and the brown twisted pair (i.e., brown white and brown) corresponds to the logical port TXP4 of the sender. The other end of the cross network cable is provided with a green twisted pair (namely green white and green) corresponding to a logic port RXP1 of a receiver, a blue twisted pair (namely orange white and blue) corresponding to a logic port RXP2 of the receiver, an orange twisted pair (namely blue white and orange) corresponding to a logic port RXP3 of the receiver, and a brown twisted pair (namely brown white and brown) corresponding to a logic port RXP4 of the receiver.

When the network cable connects the sender and the receiver by adopting the two different wire orders, a signal sent by the logic port TXP1 of the sender can be received by the logic port RXP3 of the receiver, a signal sent by the logic port TXP2 of the sender can be received by the logic port RXP2 of the receiver, a signal sent by the logic port TXP3 of the sender can be received by the logic port RXP1 of the receiver, and a signal sent by the logic port TXP4 of the sender can be received by the logic port RXP4 of the receiver. That is, the mapping relationship between the logical port of the sender and the logical port of the receiver is as follows: the sender TXP1 corresponds to the receiver RXP3, the sender TXP2 corresponds to the receiver RXP2, the sender TXP3 corresponds to the receiver RXP1, and the sender TXP4 corresponds to the receiver RXP 4.

At this time, the channel transmission matrix H determined by the transmitting side in the line order of the 4 twisted wire pairs of the network line connected to its physical port is different from the channel transmission matrix H determined by the receiving side in the line order of the 4 twisted wire pairs of the network line connected to its physical port. The channel transmission matrix determined by the transmitting side may be represented by the above equation (6), and the channel transmission matrix H determined by the receiving side may be represented by the following equation (7):

as can be seen from the above equations (6) and (7), when the sender and the receiver are connected by using the cross network cable, the channel transmission matrices H determined by the sender and the receiver are different. Thus, after the sender precodes the sent signal according to P obtained by the channel transmission matrix H (i.e., the matrix shown in formula (6)) determined by the sender, P and W obtained by the receiver according to the channel transmission matrix H (i.e., the matrix shown in formula (7)) determined by the receiver cannot correctly postencode the received signal sequence, so that the receiver cannot correctly obtain the received signal sequence, and the MIMO technology cannot be applied to DSLAMs and CPEs using cross line sequence connection.

In view of the above situation, the method for processing a cross line sequence provided by the present application aims to solve the technical problem that the MIMO technology cannot be applied to DSLAMs and CPEs connected by a cross line sequence.

The technical solution of the present application will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.

Fig. 3 is a schematic flow chart of a cross line sequence processing method provided in the present application. As shown in fig. 3, the method may include:

s101, the first device obtains the mapping relation between a plurality of logic ports of the first device and a plurality of logic ports of the second device.

Specifically, in this embodiment, the first device and the second device may be devices in a MIMO system. The physical port of the first device is connected with the physical port of the second device through a network cable, the physical port of the first device and the physical port of the second device both comprise a plurality of logical ports, the network cable comprises a plurality of twisted pairs corresponding to the plurality of logical interfaces, the plurality of twisted pairs are connected with the plurality of logical ports of the first device in a first line sequence, and the plurality of twisted pairs are connected with the plurality of logical ports of the second device in a second line sequence. In a specific implementation, when the first device may be the DSLAM, the second device may be the CPE. Or, the first device may be the CPE, and in this case, the second device may be the DSLAM.

As can be seen from the foregoing description of the examples, when the network cable connecting the first device and the second device is a cross network cable, the mapping relationship between the plurality of logical ports of the first device and the plurality of logical ports of the second device is different from the mapping relationship between the plurality of logical ports of the first device and the plurality of logical ports of the second device when the network cable connecting the first device and the second device is a direct network cable. Therefore, in this embodiment, the first device may first obtain the mapping relationship, so that the first device may determine, through the mapping relationship, whether the network cable connecting the first device and the second device is a cross network cable, that is, whether a first line sequence of a plurality of twisted pairs of the network cable connecting the first device is different from a second line sequence of the network cable connecting the second device.

The embodiment does not limit the manner in which the first device obtains the mapping relationship. Optionally, the first device may determine, according to a signal sent by the second device at each logical port, a mapping relationship between the plurality of logical ports of the first device and the plurality of logical ports of the second device. The first device may also obtain the mapping relationship and the like by receiving the mapping relationship sent by the second device.

S102, the first device determines whether the first thread and the second thread are crossed or not according to the mapping relation.

Specifically, after the first device obtains the mapping relationship between the plurality of logical ports of the first device and the plurality of logical ports of the second device, the first device may obtain, through the mapping relationship, which logical port of the second device corresponds to each logical port of the first device through the twisted pair connected thereto, so that the first device may determine, according to the logical port of the second device corresponding to each logical port of the first device, whether a first line sequence of the plurality of twisted pairs of the network cable connected to the first device is different from a second line sequence of the plurality of twisted pairs connected to the second device.

Taking the first device as the DSLAM and the second device as the CPE as an example, if the mapping relationship obtained by the DSLAM is: the TXP1 of the DSLAM corresponds to RXP1 of the CPE, the TXP2 of the DSLAM corresponds to RXP2 of the CPE, the TXP3 of the DSLAM corresponds to RXP3 of the CPE, and the TXP4 of the DSLAM corresponds to RXP4 of the CPE. At this time, through the twisted pair in the network cable connecting the DSLAM and the CPE, the order of each logical port of the DSLAM in the DSLAM and the order of the logical port of the CPE corresponding to the logical port of the DSLAM in the CPE are the same. A first wire sequence connecting a first device and a second wire sequence connecting a second device are the same, namely, the first wire sequence and the second wire sequence are not crossed.

If the mapping relationship obtained by the DSLAM is: the TXP1 of the DSLAM corresponds to RXP3 of the CPE, the TXP2 of the DSLAM corresponds to RXP2 of the CPE, the TXP3 of the DSLAM corresponds to RXP1 of the CPE, and the TXP4 of the DSLAM corresponds to RXP4 of the CPE. At this time, the logic port TXP1 of the DSLAM and the logic port RXP3 of the CPE corresponding to the DSLAM logic port TXP1 are in different orders in the CPE through twisted pairs in the network cable connecting the DSLAM and the CPE. The logical port TXP3 of the DSLAM is in a different order in the DSLAM and the logical port RXP1 of the CPE corresponding to the DSLAM logical port TXP3 is in a different order in the CPE. A first wire sequence connecting a first device with a plurality of twisted wire pairs in a network wire is different from a second wire sequence connecting a second device, namely, the first wire sequence and the second wire sequence are crossed.

S103, when the first line sequence and the second line sequence are crossed, the first device adjusts the position of a subsequence in the first signal sequence to be transmitted by the first device according to the second line sequence to obtain a second signal sequence.

Specifically, as can be seen from the above description, if there is a cross between the first line sequence and the second line sequence, and at this time, if the first device and the second device synchronously transmit the training signal sequence through the cross line sequence, the first device differs according to the received training signal sequence and the training signal sequence received by the second device, so that the channel transmission matrices H acquired by the first device and the second device according to the different training signal sequences are different. Therefore, when the first device and the second device process the signal sequences to be transmitted based on different channel transmission matrices H, the device serving as a receiving side in the first device and the second device cannot correctly acquire the received signal sequences, so that the first device and the second device cannot normally communicate, and the MIMO technology cannot be applied to the first device and the second device connected in a cross line sequence.

Therefore, in this embodiment, when the first device determines that the first line sequence and the second line sequence intersect with each other according to the mapping relationship, the first device may adjust the position of the subsequence in the first signal sequence to be transmitted according to the second line sequence, so as to obtain the second signal sequence. The sequence of each subsequence in the second signal sequence is: and arranging the signals received by the plurality of logic ports of the device as the receiving party in the second line sequence. Wherein each subsequence of said first signal sequence may be: and each logic port of the device as a sender in the first device and the second device sends the signals.

Optionally, if the first device is a sender, the second device is a receiver. The first device may adjust the first signal sequence, which is sequentially arranged according to the plurality of logical ports of the first device, to the second signal sequence, which is sequentially arranged according to the plurality of logical ports of the second device, according to the second order. Optionally, if the first device is a receiver and the second device is a sender, the first device may adjust, according to the second line sequence, the first signal sequence to be transmitted, which is sequentially arranged according to the plurality of logical ports of the first device, to be the second signal sequence, which is sequentially arranged according to the plurality of logical ports of the second device. In this way, when the first and second devices transmit the second signal sequence, the second signal sequence is transmitted to the device serving as the receiving party through the network cable with the cross line sequence, so that the network cable with the cross line sequence can cross the second signal sequence again, and the signal sequence received by the device serving as the receiving party is the same as the first signal sequence to be transmitted. In a specific implementation, the second device may also adjust the first signal sequence according to the mapping relationship, and may specifically be determined according to a negotiation result of the first device and the second device, which is not described herein again.

At this time, if the first signal sequence to be transmitted is a training signal sequence, for example: the first device and the second device, by using the method of this embodiment, enable a device, which is a receiving side, of the first device and the second device to obtain a training signal sequence that is the same as the first signal sequence sent by the sending side, and further enable the first device and the second device to obtain the same channel transmission matrix H based on the same training signal sequence.

Optionally, if the first device is a sender and the second device is a receiver, the channel transmission matrix H obtained by the first device according to the first signal sequence is the same as the signal sequence obtained by the second device according to the second signal sequence sent by the first device and the first signal sequence, so that the channel transmission matrix H obtained by the second device based on the signal sequence is the same as the channel transmission matrix H obtained by the first device. Optionally, if the first device is a receiving side and the second device is a sending side, the channel transmission matrix H obtained by the first device according to the second signal sequence is the same as the signal sequence obtained by the first device according to the signal sequence sent to the first device and the second signal sequence, so that the channel transmission matrix H obtained by the second device based on the signal sequence is the same as the channel transmission matrix H obtained by the first device.

In this way, when the first device and the second device subsequently transmit the service signal sequence, they may negotiate with each other, so that one of them may adjust the signal sequence to be transmitted according to the mapping relationship, so that after the adjusted signal sequence is received by the receiving side of the first device and the second device, the obtained signal sequence is the same as the signal sequence sent by the sending side, and both the two signal sequences are matched with the channel transmission matrix H used by the first device and the second device. In this way, in the process of transmitting the service signal sequence, the first device and the second device may process the signal sequence to be transmitted based on the same channel transmission matrix H, so that the device serving as a receiving party in the first device and the second device may correctly obtain the received signal sequence, and the MIMO technology may be applied to the first device and the second device connected in a cross line sequence. How to obtain the channel transmission matrix H by the first device and the second device based on the training signal sequence may refer to the prior art, which is not described herein again.

Exemplarily, the first device is the DSLAM, and the second device is the CPE, where the DSLAM is a sender and the CPE is a receiver. The first signal sequence to be transmitted is { S1, S2, S3, S4}, and mapping relationships between the plurality of logical ports of the DSLAM and the plurality of logical ports of the CPE are: the TXP1 of the DSLAM corresponds to RXP3 of the CPE, the TXP2 of the DSLAM corresponds to RXP2 of the CPE, the TXP3 of the DSLAM corresponds to RXP1 of the CPE, and the TXP4 of the DSLAM corresponds to RXP4 of the CPE.

When determining that the first line sequence crosses the second line sequence, the DSLAM may adjust the order of the sub-sequences in the first signal sequence according to the second line sequence, and replace the positions of S1 originally transmitted by TXP1 and S3 transmitted by TXP3 to obtain a second signal sequence, i.e., { S3, S2, S1, S4 }. Thus, when the DSLAM transmits the second signal sequence to the CPE through 4 logical ports, that is, S3 is transmitted to RXP3 of the CPE through TXP1, S2 is transmitted to RXP2 of the CPE through TXP2, S1 is transmitted to RXP1 of the CPE through TXP3, and S4 is transmitted to RXP4 of the CPE through TXP4, that is, after the signals are crossed again by the crossed line sequence, the signal sequence received by the CPE is { S1, S2, S3, S4}, which is the same as the first signal sequence.

Through the adjustment, the first signal sequence sent by the DSLAM is the same as the signal sequence received by the CPE, and at this time, if the signal sequence is a training signal sequence, the channel transmission matrix H acquired by the DSLAM based on the first signal sequence is the same as the channel transmission matrix H acquired by the CPE based on the received signal sequence. Thus, when the DSLAM and the CPE process a signal sequence to be transmitted based on the same channel transmission matrix H, the CPE can correctly acquire a received signal sequence, and the MIMO technology can be applied to the DSLAM and the CPE which are connected in a cross line sequence. It should be noted that, although the example takes the DSLAM as the sender and the CPE as the receiver as an example, it can be understood by those skilled in the art that the same applies to the example when the DSLAM is the receiver and the CPE is the sender, and the achieved technical effects are the same.

According to the processing method for the cross line sequence, when the first device and the second device adopt a plurality of twisted pairs with the cross line sequence for connection, the first device may adjust a position of a subsequence in the first signal sequence to be transmitted according to a line sequence relationship of a plurality of twisted wire pairs connected to a plurality of logical ports of the second device to obtain a second signal sequence, so that the first device and the second device can transmit training signal sequences based on the mode, so that the first signal sequence transmitted by the device as the transmitting side in the first device and the second device is the same as the signal sequence received by the device as the receiving side, and further, the determined channel transmission matrixes H are the same on the basis of the same signal sequence, so that the technical problem that the MIMO technology cannot be applied to the first equipment and the second equipment which are connected by adopting a cross line sequence is solved.

Further, on the basis of the foregoing embodiment, the specific process of how the first device obtains the mapping relationship between the multiple logical ports of the first device and the multiple logical ports of the second device in the present embodiment may include the following two cases:

in the first case: the first device may determine a mapping relationship between the plurality of logical ports of the first device and the plurality of logical ports of the second device according to a signal sent by the second device at each logical port.

Fig. 4 is a schematic flow chart of another cross line order processing method provided in the present application. As shown in fig. 4, the method may include:

s201, the first device obtains a third signal sequence according to signals, which are received at the multiple logical ports of the first device and sent by the second device through the multiple logical ports of the second device.

Specifically, in this embodiment, the second device may send a signal to the first device through a plurality of logical ports of the second device, so that the first device may obtain a third signal sequence according to the signal received by each logical port. The order of each signal in the third signal sequence is the same as the order of the plurality of logic ports receiving each signal. The signals sent by the second device through the plurality of logic ports of the second device are signals in a preset signal sequence, and the signals sent by the logic ports are different. The signal sent by the second device through each logical port of the second device may also be an identification of each logical port, etc. The identifier of the logical port may be any identifier that uniquely indicates the logical port, such as a logical port number.

S202, the first device determines the mapping relation between the plurality of logic ports of the first device and the plurality of logic ports of the second device according to the third signal sequence.

Optionally, if the signals sent by the second device through the multiple logical ports of the second device are signals in a preset signal sequence, the first device may determine, according to the third signal sequence and the preset signal sequence, a mapping relationship between the multiple logical ports of the first device and the multiple logical ports of the second device. In a specific implementation, the first device may perform a correlation operation on each signal in the third signal sequence and each signal in the preset signal sequence, and determine a signal in the preset signal sequence that has the highest correlation with each signal in the third signal sequence. Then, the first device determines a mapping relationship between the plurality of logical ports of the first device and the plurality of logical ports of the second device according to the logical port of the second device corresponding to the signal with the highest correlation with each signal in the third signal sequence in the preset signal sequence and the logical port of the first device corresponding to each signal in the third signal sequence.

For example, taking the first device as the CPE and the second device as the DSLAM as an example, the preset signal sequence is { S1, S2, S3, S4}, and mapping relationships between the plurality of logical ports of the DSLAM and the plurality of logical ports of the CPE are: the TXP1 of the DSLAM corresponds to RXP3 of the CPE, the TXP2 of the DSLAM corresponds to RXP2 of the CPE, the TXP3 of the DSLAM corresponds to RXP1 of the CPE, and the TXP4 of the DSLAM corresponds to RXP4 of the CPE.

The DSLAM may send S1, S2, S3, S4 on its four logical ports for a preset period of time, that is, the DSLAM sends S1 signal on the first logical port TXP1, sends S2 signal on the second logical port TXP2, sends S3 signal on the third logical port TXP3, and sends S4 signal on the fourth logical port TXP 4. The logical port to signal relationship may be recorded as { (TxP1, S1), (TxP2, S2), (TxP3, S3), (TxP4, S4) }. Assume that the CPE receives a signal X1 at its own first logical port RXP1, a signal X2 at the second logical port RXP2, a signal X3 at the third logical port RXP3, and a signal X4 at the fourth logical port RXP 4. The relationship of the logical port to the signal may be recorded as { (RxP1, X1), (RxP2, X2), (RxP3, X3), (RxP4, X4) }.

At this time, the third signal sequence received by the CPE is { X1, X2, X3, X4 }. Then, the CPE may identify, based on the third signal sequence and the preset signal sequence { S1, S2, S3, S4}, which signal of X1, X2, X3, and X4 in the third signal sequence is respectively { S1, S2, S3, S4 }. The identification method can be various, for example, two signals can be correlated, specifically: performing correlation operation on the X1 and S1, S2, S3 and S4 respectively, and recording the maximum peak value of the correlation, wherein the maximum peak value is { V1, V2, V3 and V4 }; find the maximum values in { V1, V2, V3, V4 }. Assuming that V3 is the maximum value, the signal source of X1 is S3. Accordingly, continuing with the correlation, X2, X3, and X4 are processed in sequence to determine the signal sources of X1, X2, X3, and X4. In this example, the signal source of X1 is S3, the signal source of X2 is S2, the signal source of X3 is S1, and the signal source of X4 is S4.

Then according to the { (TxP1, S1), (TxP2, S2), (TxP3, S3), (TxP4, S4) } and { (RxP1, X1), (RxP2, X2), (RxP3, X3), (RxP4, X4) } relationships; a mapping relationship may be derived for determining a plurality of logical ports of the CPE and a plurality of logical ports of the DSLAM, which may be expressed as: { (TXP1, RXP3), (TXP2, RXP2), (TXP3, RXP1), (TXP4, RXP4) }.

Optionally, if the signal sent by the second device through each logical port of the second device is the identifier of each logical port, the first device may analyze the third signal sequence to obtain the identifier of the logical port of the second device received by each logical port of the first device, and then determine the mapping relationship between the plurality of logical ports of the first device and the plurality of logical ports of the second device according to the identifier of the logical port of the second device received by each logical port of the first device.

Exemplarily, taking the first device as the CPE and the second device as the DSLAM as an example, the mapping relationship between the plurality of logical ports of the DSLAM and the plurality of logical ports of the CPE is as follows: the TXP1 of the DSLAM corresponds to RXP3 of the CPE, the TXP2 of the DSLAM corresponds to RXP2 of the CPE, the TXP3 of the DSLAM corresponds to RXP1 of the CPE, and the TXP4 of the DSLAM corresponds to RXP4 of the CPE.

The DSLAM may send, at an initialization stage of the xDSL system, an identifier of the logical port to a logical port of the CPE through a Handshake message or an SOC message on each logical port. Specifically, the method comprises the following steps: the DSLAM may send the identity of TXP1 on a first logical port TXP1, the identity of TXP2 on a second logical port TXP2, the identity of TXP3 on a third logical port TXP3 and the identity of TXP4 on a fourth logical port TXP4, which the DSLAM considers to be. The CPE can then derive a third signal sequence from the signals received from each logical port, where the order of each signal in the third signal sequence is the order of the logical port that the CPE believes to be by itself. For example: the signal received by the CPE at the first logical port RXP1 considered by the CPE is identified as TXP3, the signal received at the second logical port RXP2 is identified as TXP2, the signal received at the third logical port RXP3 is identified as TXP1, and the signal received at the fourth logical port RXP4 is identified as TXP 4. The CPE may analyze the third signal sequence, that is, a mapping relationship between the plurality of logical ports of the CPE and the plurality of logical ports of the DSLAM, where the mapping relationship may be expressed as: { (TXP1, RXP3), (TXP2, RXP2), (TXP3, RXP1), (TXP4, RXP4) }.

In the second case: the first device may obtain the mapping relationship and the like by receiving the mapping relationship between the plurality of logical ports of the first device and the plurality of logical ports of the second device, which is sent by the second device.

Specifically, the first device may further send a preset signal sequence or an identifier of each logical port of the first device to the second device, so that the second device may determine the mapping relationship between the plurality of logical ports of the first device and the plurality of logical ports of the second device by using the two implementation manners in the first case. In this way, the second device may send the mapping relationship to the first device, so that the first device may obtain the mapping relationship by receiving the mapping relationship, sent by the second device, between the plurality of logical ports of the first device and the plurality of logical ports of the second device.

According to the method for processing the cross line sequence, when the first device and the second device are connected through a network cable with the cross line sequence, the first device can adjust the first signal sequence to be transmitted according to the mapping relation between the plurality of logic ports of the first device and the plurality of logic ports of the second device to obtain the second signal sequence, so that the first device and the second device can send the training signal sequence based on the mode, the first signal sequence sent by the device serving as a sender in the first device and the second device is identical to the signal sequence received by the device serving as a receiver, the sender and the receiver are identical based on the identical signal sequence, the determined channel transmission matrixes H are identical, and the technical problem that the MIMO technology cannot be applied to the first device and the second device which are connected through the cross line sequence is solved.

Fig. 5 is a schematic structural diagram of a cross-line sequence processing apparatus provided in the present application. The cross-line order processing device may be a first device in a MIMO system. The MIMO system further includes a second device. The physical port of the first device is connected with the physical port of the second device through a plurality of twisted wire pairs, wherein the physical port of the first device and the physical port of the second device both comprise a plurality of logical ports, the plurality of twisted wire pairs are connected with the plurality of logical ports of the first device through a first wire sequence, and the plurality of twisted wire pairs are connected with the plurality of logical ports of the second device through a second wire sequence.

Referring to fig. 5, the first apparatus further includes:

an obtaining module 11, configured to obtain mapping relationships between multiple logical ports of the first device and multiple logical ports of the second device;

a first determining module 12, configured to determine whether the first thread and the second thread cross according to the mapping relationship;

and an adjusting module 13, configured to adjust, when the first line sequence crosses the second line sequence, a position of a subsequence in the first signal sequence to be transmitted by the first device according to the second line sequence, so as to obtain a second signal sequence.

The processing device for the cross line sequence provided by the present application may be configured to execute the steps of the first device in the foregoing method embodiment, and specific implementation and technical effects are similar and will not be described here again.

Fig. 6 is a schematic structural diagram of another cross-line sequence processing apparatus provided in the present application. As shown in fig. 6, based on the block diagram shown in fig. 5, the obtaining module 11 of the first device may include:

a processing unit 111, configured to obtain a third signal sequence according to signals, which are received on the multiple logical ports of the first device and sent by the second device through the multiple logical ports of the second device;

a determining unit 112, configured to determine, according to the third signal sequence, a mapping relationship between the multiple logical ports of the first device and the multiple logical ports of the second device.

Optionally, in an implementation manner of the present application, if the signals sent by the second device through the plurality of logic ports of the second device are signals in a preset signal sequence, where the signals sent by the logic ports are different. The determining unit 112 may be specifically configured to determine a mapping relationship between the multiple logical ports of the first device and the multiple logical ports of the second device according to the third signal sequence and the preset signal sequence. In a specific implementation, the determining unit 112 may perform a correlation operation on each signal in the third signal sequence and each signal in the preset signal sequence, and determine a signal in the preset signal sequence that has the highest correlation with each signal in the third signal sequence; and determining mapping relationships between the plurality of logic ports of the first device and the plurality of logic ports of the second device according to the logic port of the second device corresponding to the signal with the highest correlation with each signal in the third signal sequence in the preset signal sequence and the logic port of the first device corresponding to each signal in the third signal sequence.

Optionally, in an implementation manner of the present application, if a signal sent by the second device through each logical port of the second device is an identifier of each logical port, the determining unit 112 may be specifically configured to analyze the third signal sequence to obtain the identifier of the logical port of the second device received by each logical port of the first device; and determining the mapping relationship between the plurality of logical ports of the first device and the plurality of logical ports of the second device according to the received identifiers of the logical ports of the second device from the logical ports of the first device.

Optionally, in another implementation manner of the present application, the obtaining module 11 may be specifically configured to receive the mapping relationship sent by the second device.

Fig. 7 is a schematic structural diagram of another cross-line sequence processing apparatus provided in the present application. When the first device is a receiving side, the second device is a transmitting side, and the first signal sequence is a training signal sequence, as shown in fig. 7, based on the block diagram shown in fig. 5, the first device may further include:

a second determining module 14, configured to determine a channel transmission matrix according to the second signal sequence after the adjusting module adjusts the position of the subsequence in the first signal sequence to be transmitted by the first device according to the second sequence.

It should be noted that the division of the modules of the above cross-line processing apparatus is only a logical division, and the actual implementation may be wholly or partially integrated into one physical entity, or may be physically separated. And these modules can be realized in the form of software called by processing element; or may be implemented entirely in hardware; and part of the modules can be realized in the form of calling software by the processing element, and part of the modules can be realized in the form of hardware. For example, the obtaining module may be a processing element separately set up, or may be implemented by being integrated in a chip of the processing device in the cross-line order, or may be stored in a memory of the processing device in the cross-line order in the form of program code, and the function of the obtaining module may be called and executed by a processing element of the processing device in the cross-line order. Other modules are implemented similarly. In addition, all or part of the modules can be integrated together or can be independently realized. The processing element described herein may be an integrated circuit having signal processing capabilities. In implementation, each step of the above method or each module above may be implemented by an integrated logic circuit of hardware in a processor element or an instruction in the form of software.

For example, the above modules may be one or more integrated circuits configured to implement the above methods, such as: one or more Application Specific Integrated Circuits (ASICs), or one or more microprocessors (DSPs), or one or more Field Programmable Gate Arrays (FPGAs), among others. For another example, when one of the above modules is implemented in the form of a processing element scheduler code, the processing element may be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).

Fig. 8 is a schematic structural diagram of another cross-line sequence processing apparatus provided in the present application. As shown in fig. 8, the cross-line sequential processing device may be a first device in a MIMO system. The MIMO system further includes a second device. The physical port of the first device is connected with the physical port of the second device through a plurality of twisted wire pairs, wherein the physical port of the first device and the physical port of the second device both comprise a plurality of logical ports, the plurality of twisted wire pairs are connected with the plurality of logical ports of the first device through a first wire sequence, and the plurality of twisted wire pairs are connected with the plurality of logical ports of the second device through a second wire sequence.

As shown in fig. 8, the first device may include: processor 21, memory 24, optionally, the radio access network device may further include: a transmitter 22, a receiver 23.

The memory 24, the transmitter 22 and the receiver 23 and the processor 21 may be connected by a bus. Of course, in practical applications, the memory 24, the transmitter 22, the receiver 23 and the processor 21 may be not in a bus structure, but may be in other structures, such as a star structure, and the present application is not limited in particular.

Alternatively, the processor 21 may be a general-purpose central processing unit or ASIC, may be one or more integrated circuits for controlling program execution, may be a hardware circuit developed by using an FPGA, and may be a baseband processor.

Alternatively, the processor 21 may include at least one processing core.

Alternatively, the memory 24 may include one or more of ROM, RAM, and disk memory. Memory 24 is used to store data and/or instructions required by processor 21 during operation. The number of the memory 24 may be one or more.

The processor 21 is configured to execute the instructions stored in the memory 24, and when the processor 21 executes the instructions stored in the memory 24, the processor 21 is enabled to execute the cross-line processing method executed by the first device, specifically:

the processor 21 is configured to obtain mapping relationships between a plurality of logical ports of the first device and a plurality of logical ports of the second device; determining whether the first line sequence and the second line sequence are crossed or not according to the mapping relation; and when the first line sequence and the second line sequence are crossed, adjusting the position of a subsequence in a first signal sequence to be transmitted by the first equipment according to the second line sequence to obtain a second signal sequence.

Optionally, the processor 21 is specifically configured to obtain a third signal sequence according to signals, which are received at the multiple logical ports of the first device and sent by the second device through the multiple logical ports of the second device; and determining the mapping relationship between the plurality of logical ports of the first device and the plurality of logical ports of the second device according to the third signal sequence.

In an implementation manner of the present application, if signals sent by the second device through the multiple logical ports of the second device are signals in a preset signal sequence, where the signals sent by the logical ports are different, the processor 21 is specifically configured to determine a mapping relationship between the multiple logical ports of the first device and the multiple logical ports of the second device according to the third signal sequence and the preset signal sequence. For example, the processor 21 may perform a correlation operation on each signal in the third signal sequence and each signal in the preset signal sequence, and determine a signal in the preset signal sequence that has the highest correlation with each signal in the third signal sequence; and determining mapping relationships between the plurality of logic ports of the first device and the plurality of logic ports of the second device according to the logic port of the second device corresponding to the signal with the highest correlation with each signal in the third signal sequence in the preset signal sequence and the logic port of the first device corresponding to each signal in the third signal sequence.

In an implementation manner of the present application, if a signal sent by a second device through each logical port of the second device is an identifier of each logical port, the processor 21 is specifically configured to analyze the third signal sequence to obtain the identifier of the logical port of the second device received by each logical port of the first device; and determining the mapping relationship between the plurality of logical ports of the first device and the plurality of logical ports of the second device according to the identifiers of the logical ports of the second device, which are received by the logical ports of the first device.

Optionally, the processor 21 is specifically configured to instruct the transmitter 22 to receive the mapping relationship sent by the second device.

Further, when the first device is a receiver, the second device is a sender, and the first signal sequence is a training signal sequence, the processor 21 may determine the channel transmission matrix according to the second signal sequence after adjusting the position of the subsequence in the first signal sequence to be transmitted by the first device according to the second sequence to obtain the second signal sequence.

Fig. 9 is a schematic structural diagram of a cross-line processing system according to the present application. The cross line order processing system may be a multiple-input multiple-output MIMO system, the MIMO system comprising: a first device 31 and a second device 32, a physical port of the first device 31 being connected to a physical port of the second device 32 through a plurality of twisted wire pairs, wherein the physical port of the first device 31 and the physical port of the second device 32 each include a plurality of logical ports, the plurality of twisted wire pairs are connected to the plurality of logical ports of the first device 31 using a first wire order, and the plurality of twisted wire pairs are connected to the plurality of logical ports of the second device 32 using a second wire order; wherein the content of the first and second substances,

the first device 31 is configured to obtain mapping relationships between a plurality of logical ports of the first device 31 and a plurality of logical ports of the second device 32; determining whether the first line sequence and the second line sequence are crossed or not according to the mapping relation; and when the first line sequence crosses the second line sequence, adjusting the position of a subsequence in the first signal sequence to be transmitted by the first device 31 according to the second line sequence to obtain a second signal sequence.

Optionally, the first device 31 is specifically configured to obtain a third signal sequence according to signals, which are received at the multiple logical ports of the first device 31 and sent by the second device 32 through the multiple logical ports of the second device 32; and determining a mapping relationship between the plurality of logical ports of the first device 31 and the plurality of logical ports of the second device 32 according to the third signal sequence.

In an implementation manner of the present application, if the signals sent by the second device 32 through the multiple logical ports of the second device 32 are signals in a preset signal sequence, where the signals sent by the logical ports are different, the first device 31 is specifically configured to determine a mapping relationship between the multiple logical ports of the first device 31 and the multiple logical ports of the second device 32 according to the third signal sequence and the preset signal sequence. For example, the first device 31 may perform a correlation operation on each signal in the third signal sequence and each signal in the preset signal sequence, and determine a signal in the preset signal sequence that has the highest correlation with each signal in the third signal sequence; and determining mapping relationships between the plurality of logical ports of the first device 31 and the plurality of logical ports of the second device 32 according to the logical port of the second device 32 corresponding to the signal with the highest correlation with each signal in the third signal sequence in the preset signal sequence and the logical port of the first device 31 corresponding to each signal in the third signal sequence.

In an implementation manner of the present application, if a signal sent by the second device 32 through each logical port of the second device 32 is an identifier of each logical port, the first device 31 is specifically configured to analyze the third signal sequence to obtain the identifier of the logical port of the second device 32 received by each logical port of the first device 31; and further determining a mapping relationship between the plurality of logical ports of the first device 31 and the plurality of logical ports of the second device 32 according to the identifiers of the logical ports of the second device 32 received by the logical ports of the first device 31.

Optionally, the first device 31 is specifically configured to receive the mapping relationship sent by the second device 32.

Further, when the first device 31 is a receiver, the second device 32 is a sender, and the first signal sequence is a training signal sequence, the first device 31 may determine the channel transmission matrix according to the second signal sequence after adjusting the position of the subsequence in the first signal sequence to be transmitted by the first device 31 according to the second sequence to obtain the second signal sequence.

The processing system for the cross line sequence provided by the application can be used for executing the method embodiment, and the specific implementation manner and the technical effect are similar, and are not described again here.

Optionally, the present application further provides a computer-readable storage medium. The computer-readable storage medium may include: instructions which, when run on a computer, cause the computer to perform the method of cross-line processing as described above with reference to any one of figures 3 to 4.

Optionally, the present application further provides a computer program product including instructions, which when run on a computer, causes the computer to execute the processing method of the cross-line order shown in any one of fig. 3 to 4.

The functions of the computer program product may be implemented in hardware or software, and when implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable storage medium.

It should be noted that, in the above embodiments, all or part of the implementation may be realized by software, hardware, firmware or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described herein to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device including one or more available media integrated servers, data centers, and the like. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.

Claims

1. A method for processing a cross-line order, the method is applied to a first device and a second device in a MIMO system, a physical port of the first device is connected to a physical port of the second device through a plurality of twisted wire pairs, wherein the physical port of the first device and the physical port of the second device each include a plurality of logical ports, the plurality of twisted wire pairs connect a plurality of logical ports of the first device in a first line order, and the plurality of twisted wire pairs connect a plurality of logical ports of the second device in a second line order; the method comprises the following steps:

the first equipment acquires the mapping relation between a plurality of logical ports of the first equipment and a plurality of logical ports of the second equipment;

the first equipment determines whether the first line sequence and the second line sequence are crossed or not according to the mapping relation;

and when the first equipment crosses the second line sequence, adjusting the position of a subsequence in a first signal sequence to be transmitted by the first equipment according to the second line sequence to obtain a second signal sequence.

2. The method of claim 1, wherein the obtaining, by the first device, a mapping relationship between a plurality of logical ports of the first device and a plurality of logical ports of the second device comprises:

the first device obtains a third signal sequence according to signals, received from the plurality of logical ports of the first device, sent by the second device through the plurality of logical ports of the second device;

and the first device determines the mapping relation between the plurality of logical ports of the first device and the plurality of logical ports of the second device according to the third signal sequence.

3. The method according to claim 2, wherein the signals sent by the second device through the plurality of logical ports of the second device are signals in a preset signal sequence, and the signals sent by the logical ports are different;

the determining, by the first device, a mapping relationship between a plurality of logical ports of the first device and a plurality of logical ports of the second device according to the third signal sequence includes:

and the first device determines the mapping relationship between the plurality of logical ports of the first device and the plurality of logical ports of the second device according to the third signal sequence and the preset signal sequence.

4. The method of claim 3, wherein the determining, by the first device, a mapping relationship between a plurality of logical ports of the first device and a plurality of logical ports of the second device according to the third signal sequence and the preset signal sequence comprises:

the first device performs correlation operation on each signal in the third signal sequence and each signal in the preset signal sequence, and determines a signal in the preset signal sequence which has the highest correlation with each signal in the third signal sequence;

and the first device determines the mapping relationship between the plurality of logical ports of the first device and the plurality of logical ports of the second device according to the logical port of the second device corresponding to the signal with the highest correlation with each signal in the third signal sequence in the preset signal sequence and the logical port of the first device corresponding to each signal in the third signal sequence.

5. The method of claim 2, wherein the signal sent by the second device through each logical port of the second device is an identification of each of the logical ports;

the first device analyzes the third signal sequence to obtain the identifier of the logical port of the second device, which is received by each logical port of the first device;

the first device determines a mapping relationship between a plurality of logical ports of the first device and a plurality of logical ports of the second device according to the identifiers of the logical ports of the second device, which are received by the logical ports of the first device.

6. The method of claim 1, wherein the obtaining, by the first device, a mapping relationship between a plurality of logical ports of the first device and a plurality of logical ports of the second device comprises:

7. The method according to any of claims 1-6, wherein the first device is a receiver, the second device is a sender, and the first signal sequence is a training signal sequence;

when the first device crosses the second line sequence, the first device adjusts, according to the second line sequence, a position of a subsequence in a first signal sequence to be transmitted by the first device, and after obtaining a second signal sequence, the method further includes:

and the first equipment determines a channel transmission matrix according to the second signal sequence.

8. A cross-line order processing device, wherein the device is a first device in a multiple-input multiple-output MIMO system, the MIMO system further comprises a second device, and a physical port of the first device is connected to a physical port of the second device through a plurality of twisted wire pairs, wherein the physical port of the first device and the physical port of the second device each comprise a plurality of logical ports, the plurality of twisted wire pairs connect a plurality of logical ports of the first device in a first line order, and the plurality of twisted wire pairs connect a plurality of logical ports of the second device in a second line order; the first device further comprises:

an obtaining module, configured to obtain mapping relationships between multiple logical ports of the first device and multiple logical ports of the second device;

a first determining module, configured to determine whether the first thread sequence and the second thread sequence cross according to the mapping relationship;

and the adjusting module is used for adjusting the position of a subsequence in a first signal sequence to be transmitted by the first equipment according to the second line sequence when the first line sequence and the second line sequence are crossed to obtain a second signal sequence.

9. The cross-line order processing device of claim 8, wherein the obtaining module comprises:

the processing unit is configured to obtain a third signal sequence according to signals, which are received at the multiple logical ports of the first device and sent by the second device through the multiple logical ports of the second device;

a determining unit, configured to determine, according to the third signal sequence, a mapping relationship between the multiple logical ports of the first device and the multiple logical ports of the second device.

10. The cross-line sequence processing device according to claim 9, wherein the signals sent by the second device through the plurality of logical ports of the second device are signals in a preset signal sequence, and the signals sent by the logical ports are different;

the determining unit is specifically configured to determine, according to the third signal sequence and the preset signal sequence, a mapping relationship between the plurality of logical ports of the first device and the plurality of logical ports of the second device.

11. The apparatus according to claim 10, wherein the determining unit is specifically configured to perform a correlation operation on each signal in the third signal sequence and each signal in the preset signal sequence, and determine a signal in the preset signal sequence that has a highest correlation with each signal in the third signal sequence; and determining mapping relationships between the plurality of logic ports of the first device and the plurality of logic ports of the second device according to the logic port of the second device corresponding to the signal with the highest correlation with each signal in the third signal sequence in the preset signal sequence and the logic port of the first device corresponding to each signal in the third signal sequence.

12. The cross-line order processing device of claim 9, wherein the signal sent by the second device through each logical port of the second device is an identification of each logical port;

the determining unit is specifically configured to analyze the third signal sequence to obtain an identifier of a logical port of the second device, where the identifier is received by each logical port of the first device; and determining the mapping relationship between the plurality of logical ports of the first device and the plurality of logical ports of the second device according to the received identifiers of the logical ports of the second device from the logical ports of the first device.

13. The apparatus for processing a cross-line sequence according to claim 8, wherein the obtaining module is specifically configured to receive the mapping relationship sent by the second apparatus.

14. The apparatus for processing cross line sequence according to any of claims 8-13, wherein the first apparatus is a receiver, the second apparatus is a sender, and the first signal sequence is a training signal sequence;

the first device further comprises:

and the second determining module is used for determining a channel transmission matrix according to the second signal sequence after the adjusting module adjusts the position of the subsequence in the first signal sequence to be transmitted by the first device according to the second sequence.

15. A cross-line order processing system, wherein the cross-line order processing system is a multiple-input multiple-output, MIMO, system, comprising: the physical port of the first device and the physical port of the second device are connected through a plurality of twisted wire pairs, wherein the physical port of the first device and the physical port of the second device both comprise a plurality of logical ports, the plurality of twisted wire pairs are connected with the plurality of logical ports of the first device in a first line order, and the plurality of twisted wire pairs are connected with the plurality of logical ports of the second device in a second line order; wherein the content of the first and second substances,

the first device is configured to obtain mapping relationships between a plurality of logical ports of the first device and a plurality of logical ports of the second device; determining whether the first line sequence and the second line sequence are crossed or not according to the mapping relation; and when the first line sequence and the second line sequence are crossed, adjusting the position of a subsequence in a first signal sequence to be transmitted by the first equipment according to the second line sequence to obtain a second signal sequence.

16. The system according to claim 15, wherein the first device is a receiver, the second device is a sender, and the first signal sequence is a training signal sequence;

the first device is further configured to, when the first line sequence crosses the second line sequence, adjust a position of a subsequence in a first signal sequence to be transmitted by the first device according to the second line sequence, obtain a second signal sequence, and then determine a channel transmission matrix according to the second signal sequence.