CN110471880B - ARINC429 bus module supporting Label number screening based on FPGA and data transmission method thereof - Google Patents
ARINC429 bus module supporting Label number screening based on FPGA and data transmission method thereof Download PDFInfo
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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Abstract
The invention discloses an ARINC429 bus module supporting Label number screening based on FPGA, which is used for realizing data transmission between an ARINC429 bus and a main control device and comprises the following components: the system comprises an ARINC429 communication module, a core main control module, a communication configuration module and a serial port communication module; the invention also discloses a data transmission method based on the bus module; the invention adopts FPGA chip to design, utilizes FPGA and EEPROM to realize communication parameter configuration logic, ARINC429 received data screening and sending logic, and serial port data receiving and sending logic, the FPGA chip carries an ARINC429 protocol chip for sending and receiving ARINC429 signals, and simultaneously uses serial port RS422 to construct communication between an ARINC429 bus module and a main control device, thereby improving the reliability and stability of communication. The flexible configurability and the rapid parallelism of the FPGA are fully utilized, and the configuration of communication parameters, the screening and filtering of ARINC429 signals and the effective, accurate and rapid transmission of the signals are realized.
Description
Technical Field
The invention relates to the technical field of bus signal processing, in particular to an ARINC429 bus module supporting Label number screening based on an FPGA and a data transmission method thereof.
Background
With the continuous development of avionics systems, a large amount of information interaction needs to be carried out among avionic devices, and the requirement of people on an aviation bus is gradually improved. Among a plurality of aviation buses, the ARINC429 bus is widely applied to aerospace aircrafts by virtue of the advantages of stable performance, simple structure, high reliability, strong anti-interference capability and the like, and occupies a dominating position in the field of large civil airliners, and the key for realizing ARINC429 communication is to design a high-speed transceiving interface circuit according to a communication protocol of an ARINC429 data bus.
At present, the ARINC429 bus interface developed in China has a plurality of defects, for example, the ARINC429 communication board developed by a singlechip is difficult to ensure the 4-bit interval between adjacent ARINC429 data words, the hardware circuit is complex, and the integration level is not high; the use of DSP to develop ARINC429 interface requires many digital circuits to be extended from the periphery, and the system can not be minimized. The ARINC429 communication board which is commercialized at present is expensive, fixed relative to a coding format and not flexible and convenient to use, so that researchers are required to find a corresponding solution.
On the other hand, parameter information from each avionics device is transmitted on the ARINC429 communication bus, and it is not necessary for any receiving device to receive all signals, so that it is necessary to screen the received ARINC429 data. In the prior art, a PCI bus or an Ethernet is mainly used as an expansion interface of an ARINC429 bus interface module, the PCI bus has a complex structure, high power consumption and poor environmental adaptability, is not suitable for working in an airborne strong vibration environment, and a network port also has the defect of unfixed network delay.
In summary, it is an urgent need to solve the above-mentioned problems by those skilled in the art to develop an ARINC429 bus interface module that can effectively screen signals and has high accuracy and flexibility.
Disclosure of Invention
In view of this, the present invention provides an ARINC429 bus module with strong real-time performance and wide universality and a data transmission method thereof, and in the process of communicating with an ARINC429 bus, the application aims to receive an ARINC429 signal within a 4-bit word interval, screen the signal, convert the signal into serial data, and transmit the serial data through a serial port.
In order to achieve the purpose, the invention adopts the following technical scheme:
an ARINC429 bus module based on FPGA supporting Label number screening is used for realizing data transmission between 429 bus and main control equipment, and comprises: the system comprises an ARINC429 communication module, a core main control module, a communication configuration module and a serial port communication module;
the ARINC429 communication module comprises an ARINC429 protocol chip and an ARINC429 interface circuit, the ARINC429 protocol chip is connected with the ARINC429 interface circuit, the ARINC429 interface circuit is connected with the ARINC429 bus, the ARINC429 interface circuit is connected with the core main control module, and the ARINC429 protocol chip is used for receiving and transmitting ARINC429 data;
the core main control module comprises an FPGA chip, the FPGA chip is connected with the ARINC429 interface circuit, and the FPGA chip is used for realizing communication parameter configuration logic and communication logic;
the communication parameter configuration logic is used for realizing the configuration of communication parameters;
the communication logic comprises conversion logic and screening logic, the conversion logic is used for realizing conversion between serial port data and the ARINC429 data, and the screening logic is used for realizing screening of the ARINC429 data based on Label numbers;
the communication configuration module comprises an EEPROM chip, the EEPROM chip is respectively connected with the FPGA chip, the EEPROM chip is used for realizing writing and reading of communication parameters, and the FPGA chip is used for completing configuration of the communication parameters;
the serial port communication module comprises an asynchronous RS232 communication circuit and an asynchronous RS422 communication circuit, the asynchronous RS232 communication circuit is connected with the FPGA chip through an RS232 serial port, the asynchronous RS422 communication circuit is connected with the FPGA chip through an RS422 serial port, and the asynchronous RS422 communication circuit is connected with the main control equipment;
the asynchronous RS232 communication circuit is used for changing the communication parameters, and the asynchronous RS422 communication circuit is used for exporting the screened ARINC429 data to be transmitted to the main control equipment and communicating with the main control equipment according to an asynchronous RS422 communication protocol.
Preferably, the FPGA chip comprises a configuration parameter register, and the configuration parameter register comprises an RS422 configuration parameter register and an ARINC429 configuration parameter register;
the RS422 configuration parameter register and the ARINC429 configuration parameter register are both connected with the EEPROM chip, and the RS422 configuration parameter register is used for storing RS422 serial port communication parameters; the ARINC429 configuration parameter register is used for storing parameters related to the ARINC429 communication;
the RS422 serial port communication parameters comprise communication rate and parity check bit setting parameters; parameters related to the ARINC429 communication include communication rate, byte bit number, parity check mode, SDI code, and Label number.
Preferably, the FPGA chip further comprises a FIFO memory, and the FIFO memory comprises a first FIFO memory and a second FIFO memory; the writing bit width of the first FIFO memory is 8bits, the reading bit width is 16bits, the writing bit width of the second FIFO memory is 16bits, and the reading bit width is 8 bits;
the first FIFO memory is connected with the ARINC429 configuration parameter register and used for storing screened ARINC429 data;
and the second FIFO memory is connected with the RS422 serial port and used for storing serial port data.
A data transmission method of an ARINC429 bus module supporting Label number screening based on an FPGA comprises the following steps:
s1: reading communication parameters from the EEPROM chip by the FPGA chip, and completing parameter configuration according to configuration logic or reconfiguring according to the changed communication parameters by the FPGA chip;
s2: the FPGA chip detects the received data, judges the data type and transmits and receives the data;
s21: if the detected data is ARINC429 bus data, the FPGA chip screens the ARINC429 bus data according to screening logic, and the screened ARINC429 bus data is converted and then sent to corresponding main control equipment through an asynchronous RS422 communication circuit and an RS422 serial port;
s22: and if the detected data is serial port data, converting the serial port data and then sending the serial port data to the ARINC429 bus.
Preferably, the specific steps of S1 are:
the RS422 configuration parameter register reads RS422 serial port communication parameters from the EEPROM chip to complete configuration;
the ARINC429 configuration parameter register reads parameters related to ARINC429 communication from the EEPROM chip and writes corresponding control words into the ARINC429 protocol chip to complete configuration;
the control words contain communication rate, byte number, parity check mode and SDI code information, and the configured working state is the default working state.
Preferably, the specific steps of reconfiguring according to the changed communication parameters are as follows:
and the asynchronous RS232 communication circuit writes new communication parameters into the EEPROM chip through the RS232 serial port to cover the previously stored communication parameters, and simultaneously, the new communication parameters are directly written into the RS422 configuration parameter register to complete the change of the communication parameters in real time.
Preferably, the specific steps of S21 are:
(1) when valid ARINC429 data is detected, dividing the current ARINC429 data into a first byte and a second byte within the ARINC429 protocol chip, wherein 0-7 bits of the first byte represent the Label number of the currently received ARINC429 data word; and sending a data receiving request to the ARINC429 configuration parameter register;
(2) the ARINC429 protocol chip transmits the first byte and the second byte to the ARINC429 configuration parameter register through a 16bits parallel data line in sequence; matching the Label number of the ARINC429 data currently received with the Label number in the ARINC429 configuration parameter register while receiving the second byte, and if the Label numbers are matched, completely writing the current ARINC429 data into the first FIFO memory;
(3) and the current ARINC429 data is sent to the corresponding main control equipment through the RS422 serial port.
Preferably, the specific steps of S22 are:
when effective serial port data are detected, generating an ARINC429 data parity bit, writing the current serial port data into a second FIFO memory, converting the serial port data into ARINC429 data, transmitting the ARINC429 data to the ARINC429 protocol chip through a 16bits parallel data line after the complete ARINC429 data are received, and simultaneously giving out a corresponding control command, wherein the ARINC429 protocol chip sends data to the ARINC429 bus according to preset communication parameters.
Through the technical scheme, compared with the prior art, the ARINC429 bus module supporting Label number screening based on the FPGA and the data transmission method thereof are disclosed.
Firstly, the invention adopts an FPGA chip for design, realizes communication parameter configuration logic, ARINC429 received data screening and sending logic and serial port data receiving and sending logic by utilizing the FPGA and the EEPROM, the FPGA chip carries an ARINC429 protocol chip for sending and receiving ARINC429 signals, and meanwhile, the serial port RS422 is used for constructing communication between an ARINC429 bus module and a main control device, thereby improving the reliability and stability of the communication. The flexible configurability and the rapid parallelism of the FPGA are fully utilized, and the configuration of communication parameters, the screening and filtering of ARINC429 signals and the effective, accurate and rapid transmission of the signals are realized.
Secondly, the communication parameters of the FPGA chip can be configured in real time by adopting RS232, the default working state is adopted when the communication parameters are not configured, the working mode can be changed in real time, and the configuration is good and the flexibility is high.
Finally, the invention also discloses a data transceiving method of the bus module, which screens ARINC429 data before the data is stored in the FIFO memory so as to relieve the cache pressure of the FIFO memory and improve the communication efficiency.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic diagram of the structure provided by the present invention;
fig. 2 is a schematic overall flow chart of sending ARINC429 data to a master control device according to the present invention;
fig. 3 is a schematic diagram illustrating an overall process for receiving serial data to the ARINC429 bus according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The first embodiment is as follows:
the embodiment discloses an ARINC429 bus module supporting Label number screening based on an FPGA, which is used for realizing data transmission between an ARINC429 bus and a main control device, and as shown in fig. 1, the ARINC429 bus module includes: the system comprises an ARINC429 communication module, a core main control module, a communication configuration module and a serial port communication module;
the ARINC429 communication module comprises an ARINC429 protocol chip and an ARINC429 interface circuit, the ARINC429 protocol chip is connected with the ARINC429 interface circuit, the ARINC429 interface circuit is connected with an ARINC429 bus, the ARINC429 interface circuit is connected with the core main control module, and the ARINC429 protocol chip is used for receiving and transmitting ARINC429 data;
the core main control module comprises an FPGA chip, the FPGA chip is connected with the ARINC429 interface circuit, and the FPGA chip is used for realizing communication parameter configuration logic and communication logic;
the communication parameter configuration logic is used for realizing the configuration of the communication parameters;
the communication logic comprises conversion logic and screening logic, the conversion logic is used for realizing the conversion between the serial port data and the ARINC429 data, and the screening logic is used for realizing the screening of the ARINC429 data based on the Label number;
the communication configuration module comprises an EEPROM chip, the EEPROM chip is respectively connected with the FPGA chip, the EEPROM chip is used for writing and reading communication parameters, and the FPGA chip is used for completing the configuration of the communication parameters;
the serial port communication module comprises an asynchronous RS232 communication circuit and an asynchronous RS422 communication circuit, the asynchronous RS232 communication circuit is connected with the FPGA chip through an RS232 serial port, the asynchronous RS422 communication circuit is connected with the FPGA chip through an RS422 serial port, and the asynchronous RS422 communication circuit is connected with the main control equipment;
the asynchronous RS232 communication circuit is used for changing communication parameters, and the asynchronous RS422 communication circuit is used for exporting screened ARINC429 data to be transmitted to the main control equipment and is communicated with the main control equipment according to an asynchronous RS422 communication protocol.
In order to further optimize the technical scheme, the FPGA chip comprises a configuration parameter register, and the configuration parameter register comprises an RS422 configuration parameter register and an ARINC429 configuration parameter register;
the RS422 configuration parameter register and the ARINC429 configuration parameter register are both connected with the EEPROM chip, and the RS422 configuration parameter register is used for storing RS422 serial port communication parameters; the ARINC429 configuration parameter register is used for storing parameters related to ARINC429 communication;
the RS422 serial port communication parameters comprise communication rate and parity check bit setting parameters; parameters related to ARINC429 communication include communication rate, byte bit number, parity check mode, SDI code, and Label number.
In order to further optimize the technical scheme, the FPGA chip further comprises an FIFO memory, and the FIFO memory comprises a first FIFO memory and a second FIFO memory; the writing bit width of the first FIFO memory is 8bits, the reading bit width is 16bits, the writing bit width of the second FIFO memory is 16bits, and the reading bit width is 8 bits;
the first FIFO memory is connected with an ARINC429 configuration parameter register and used for storing screened ARINC429 data;
and the second FIFO memory is connected with the RS422 serial port and used for storing serial port data.
The invention gives full play to the advantage of the rapid parallelism of the FPGA chip, realizes serial communication logic, ARINC429 bus communication logic and data screening logic by using the FPGA, realizes communication configuration logic by using the FPGA to be matched with the EEPROM, can update and configure communication parameters by RS232, can change the working mode in real time, has good configurability and high flexibility, and improves the reliability and stability of communication by externally transmitting ARINC429 data through RS 422; the FIFO buffer memory pressure can be effectively relieved by using the FIFO buffer memory, and meanwhile, the communication efficiency is improved.
Example two:
the embodiment discloses a data transmission method of an ARINC429 bus module supporting Label number screening based on an FPGA, which comprises the following steps:
s1: the FPGA chip reads the communication parameters from the EEPROM chip, and the FPGA chip completes the configuration of the parameters according to the configuration logic or reconfigures the parameters according to the changed communication parameters;
s2: the FPGA chip detects the received data, judges the data type and transmits and receives the data;
s21: if the detected data is ARINC429 bus data, the FPGA chip screens the 429 bus data according to screening logic, and the screened ARINC429 bus data is converted and then sent to corresponding main control equipment through an asynchronous RS422 communication circuit and an RS422 serial port;
s22: and if the detected data is serial port data, converting the serial port data and then sending the serial port data to an ARINC429 bus.
In order to further optimize the above technical solution, the specific steps of S1 are:
the RS422 configuration parameter register reads RS422 serial port communication parameters from the EEPROM chip to complete configuration;
the ARINC429 configuration parameter register reads parameters related to ARINC429 communication from the EEPROM chip and writes corresponding control words into the ARINC429 protocol chip to complete configuration;
the control word comprises communication rate, byte number, parity check mode and SDI code information, and the configured working state is the default working state.
In order to further optimize the above technical solution, the specific steps of reconfiguring according to the changed communication parameters are as follows:
the asynchronous RS232 communication circuit writes new communication parameters into the EEPROM chip through the RS232 serial port to cover the previously stored communication parameters, and meanwhile, the new communication parameters are directly written into the RS422 configuration parameter register to complete the change of the communication parameters in real time.
In order to further optimize the above technical solution, the specific steps of S21 are:
(1) when valid ARINC429 data is detected, dividing the current ARINC429 data into a first byte and a second byte within an ARINC429 protocol chip, wherein 0-7 bits of the first byte represent the Label number of the currently received ARINC429 data word; and sends a data receiving request to an ARINC429 configuration parameter register;
(2) the ARINC429 protocol chip transmits the first byte and the second byte to an ARINC429 configuration parameter register through a 16bits parallel data line in sequence; when receiving the second byte, matching the Label number of the ARINC429 data currently received with the Label number in the ARINC429 configuration parameter register, and if the Label numbers are matched, completely writing the current ARINC429 data into the first FIFO memory;
(3) and the current ARINC429 data is sent to the corresponding main control equipment through the RS422 serial port.
In order to further optimize the above technical solution, the specific steps of S22 are:
when effective serial port data are detected, generating an ARINC429 data parity bit, writing the current serial port data into a second FIFO memory, converting the serial port data into ARINC429 data, transmitting the ARINC429 data to an ARINC429 protocol chip through a 16bits parallel data line after the complete ARINC429 data are received, and simultaneously giving a corresponding control command, wherein the ARINC429 protocol chip sends the data to an ARINC429 bus according to preset communication parameters.
Specifically, as shown in fig. 2, the overall flow of sending ARINC429 data to the master device in the present invention is as follows:
(1) the FPGA chip controls and reads communication configuration parameters to complete configuration;
(2) starting an ARINC429 receiving channel and a serial port sending channel, monitoring ARINC429 bus data in real time, further detecting whether effective ARINC429 data exists, if yes, carrying out the next step, and if not, continuously detecting the effective ARINC429 data;
(3) matching the valid ARINC429 data with a Label number in an ARINC429 configuration parameter register, if the matching is successful, sending the ARINC429 data into a FIFO memory, and if the matching is unsuccessful, returning to the step (2) to detect the valid ARINC429 data again;
(4) and sending the data stored in the FIFO memory to the main control equipment through the 422 serial port.
As shown in fig. 3, the overall flow of receiving serial port data to the ARINC429 bus in the present invention is as follows:
(1) the FPGA chip controls and reads communication configuration parameters to complete configuration;
(2) opening a serial port receiving channel and an ARINC429 sending channel, and monitoring serial port data in real time;
(3) detecting whether effective serial port data exist or not, if so, carrying out the next step, and if not, continuously detecting the effective serial port data;
(4) the serial port data is fed into the FIFO memory and sent to the ARINC429 bus through the ARINC429 interface circuit.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (4)
1. The utility model provides an ARINC429 bus module based on screening of FPGA support Label number for realize the transmission of data between ARINC429 bus and the master control equipment, its characterized in that includes: the system comprises an ARINC429 communication module, a core main control module, a communication configuration module and a serial port communication module;
the ARINC429 communication module comprises an ARINC429 protocol chip and an ARINC429 interface circuit, the ARINC429 protocol chip is connected with the ARINC429 interface circuit, the ARINC429 interface circuit is connected with an ARINC429 bus, the ARINC429 interface circuit is connected with the core main control module, and the ARINC429 protocol chip is used for receiving and transmitting ARINC429 data;
the core main control module comprises an FPGA chip, the FPGA chip is connected with the ARINC429 interface circuit, and the FPGA chip is used for realizing communication parameter configuration logic and communication logic;
the communication parameter configuration logic is used for realizing the configuration of communication parameters;
the communication logic comprises conversion logic and screening logic, the conversion logic is used for realizing conversion between serial port data and the ARINC429 data, and the screening logic is used for realizing screening of the ARINC429 data based on Label numbers;
the communication configuration module comprises an EEPROM chip, the EEPROM chip is connected with the FPGA chip, the EEPROM chip is used for writing and reading communication parameters, and the FPGA chip is used for completing configuration of the communication parameters;
the serial port communication module comprises an asynchronous RS232 communication circuit and an asynchronous RS422 communication circuit, the asynchronous RS232 communication circuit is connected with the FPGA chip through an RS232 serial port, the asynchronous RS422 communication circuit is connected with the FPGA chip through an RS422 serial port, and the asynchronous RS422 communication circuit is connected with the main control equipment;
the asynchronous RS232 communication circuit is used for changing the communication parameters, and the asynchronous RS422 communication circuit is used for exporting the screened ARINC429 data to be transmitted to the main control equipment and communicating with the main control equipment according to an asynchronous RS422 communication protocol;
the FPGA chip comprises a configuration parameter register, wherein the configuration parameter register comprises an RS422 configuration parameter register and an ARINC429 configuration parameter register;
the RS422 configuration parameter register and the ARINC429 configuration parameter register are both connected with the EEPROM chip, and the RS422 configuration parameter register is used for storing RS422 serial port communication parameters; the ARINC429 configuration parameter register is used for storing parameters related to the ARINC429 communication;
the RS422 serial port communication parameters comprise communication rate and parity check bit setting parameters; parameters related to the ARINC429 communication include communication rate, byte bit number, parity check mode, SDI code and Label number;
the FPGA chip also comprises an FIFO memory, and the FIFO memory comprises a first FIFO memory and a second FIFO memory; the writing bit width of the first FIFO memory is 8bits, the reading bit width is 16bits, the writing bit width of the second FIFO memory is 16bits, and the reading bit width is 8 bits;
the first FIFO memory is connected with the ARINC429 configuration parameter register and used for storing screened ARINC429 data;
and the second FIFO memory is connected with the RS422 serial port and used for storing serial port data.
2. A data transmission method of an ARINC429 bus module supporting Label number screening based on an FPGA is characterized by comprising the following steps:
s1: reading communication parameters from the EEPROM chip by the FPGA chip, and completing parameter configuration according to configuration logic or reconfiguring according to the changed communication parameters by the FPGA chip;
the specific steps of reconfiguring according to the changed communication parameters are as follows:
the asynchronous RS232 communication circuit writes new communication parameters into the EEPROM chip through the RS232 serial port to cover the previously stored communication parameters, and meanwhile, the new communication parameters are directly written into an RS422 configuration parameter register to complete the change of the communication parameters in real time;
s2: the FPGA chip detects the received data, judges the data type and transmits and receives the data;
s21: if the detected data is ARINC429 bus data, the FPGA chip screens the ARINC429 bus data according to screening logic, and the screened ARINC429 bus data is converted and then sent to corresponding main control equipment through an asynchronous RS422 communication circuit and an RS422 serial port:
(1) when valid ARINC429 data is detected, dividing the current ARINC429 data into a first byte and a second byte within the ARINC429 protocol chip, wherein 0-7 bits of the first byte represent the Label number of the currently received ARINC429 data word; and sending a data receiving request to the ARINC429 configuration parameter register;
(2) the ARINC429 protocol chip transmits the first byte and the second byte to the ARINC429 configuration parameter register through a 16bits parallel data line in sequence; matching the Label number of the ARINC429 data currently received with the Label number in the ARINC429 configuration parameter register while receiving the second byte, and if the Label numbers are matched, completely writing the current ARINC429 data into the first FIFO memory;
(3) the current ARINC429 data is sent to corresponding main control equipment through an RS422 serial port;
s22: and if the detected data is serial port data, converting the serial port data and then sending the serial port data to the ARINC429 bus.
3. The data transmission method of the ARINC429 bus module based on the FPGA supporting Label number screening is characterized in that the specific steps of S1 are as follows:
the RS422 configuration parameter register reads RS422 serial port communication parameters from the EEPROM chip to complete configuration;
the ARINC429 configuration parameter register reads parameters related to ARINC429 communication from the EEPROM chip and writes corresponding control words into the ARINC429 protocol chip to complete configuration;
the control words contain communication rate, byte number, parity check mode and SDI code information, and the configured working state is the default working state.
4. The data transmission method of the ARINC429 bus module based on the FPGA supporting Label number screening is characterized in that the specific steps of S22 are as follows:
when effective serial port data are detected, generating an ARINC429 data parity bit, writing the current serial port data into a second FIFO memory, converting the serial port data into ARINC429 data, transmitting the ARINC429 data to the ARINC429 protocol chip through a 16bits parallel data line after the complete ARINC429 data are received, and simultaneously giving out a corresponding control command, wherein the ARINC429 protocol chip sends data to the ARINC429 bus according to preset communication parameters.
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| CN111121763A (en) * | 2019-12-09 | 2020-05-08 | 重庆鲲量科技有限公司 | FPGA-based data analysis method in optical fiber inertial navigation |
| CN113127400B (en) * | 2019-12-31 | 2023-04-18 | 中国科学院长春光学精密机械与物理研究所 | FPGA-based multi-channel serial port server and data transmission method thereof |
| CN112231266B (en) * | 2020-10-15 | 2023-03-24 | 天津津航计算技术研究所 | ARINC429 bus control method based on lookup table |
| CN113255156B (en) * | 2021-06-11 | 2023-09-01 | 中国商用飞机有限责任公司 | Loop real-time simulation system and method for civil aircraft ground dynamic test signals |
| CN115550098B (en) * | 2022-09-16 | 2023-05-05 | 哈尔滨工业大学 | ARINC429 bus communication assembly and device based on MiniVPX framework |
| CN115828814B (en) * | 2023-02-13 | 2023-05-12 | 中兵通信科技股份有限公司 | Circuit design method of ARINC429 protocol soft core based on FPGA |
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