CN201583945U

CN201583945U - Serial communication system for multiple singlechips based on FPGA

Info

Publication number: CN201583945U
Application number: CN2009202512121U
Authority: CN
Inventors: 张晓峰; 张志利; 王文博; 曹鹏飞; 陈伟峰
Original assignee: Tianjin Optical Electrical Communication Technology Co Ltd
Current assignee: Tianjin Optical Electrical Communication Technology Co Ltd
Priority date: 2009-12-02
Filing date: 2009-12-02
Publication date: 2010-09-15
Anticipated expiration: 2019-12-02

Abstract

The utility model relates to a serial communication system for multiple singlechips based on FPGA (field programmable gate array), which can integrate 16 simple UARTs (universal asynchronous receivers/transmitters) by adopting FPGA. The serial communication system comprises a microcomputer, a master singlechip, a FPGA and 16 slave singlechips, wherein the microcomputer, the master singlechip and the FPGA are connected in sequence; and the FPGA is respectively connected with the 16 slave singlechips through 16 simple UARTs, so that the mode that one master singlechip can access 16 slave singlechips at the same time is realized. The system has simple structure; and the module communication mode completely conforms to the universal serial communication protocol, and can be widely applied for monitoring computer-control systems (SCCs) and distributed control systems (DCSs).

Description

Single-chip microcomputer multi-computer serial communication system based on FPGA

Technical field

The utility model relates to communication and measurement and control area, particularly a kind of single-chip microcomputer multi-computer serial communication system based on FPGA.

Background technology

Along with the development of observation and control technology, the SURVEYING CONTROL NETWORK network that is made of multiple single chip microcomputer in the application of measurement and control area more and more widely.Exchanges data between the single-chip microcomputer adopts serial communication mode usually, and connected mode adopts bus topolopy more.Single-chip microcomputer is connected by one group of data line in this structure, one group of data line of all one-chip machine commons; Will be during communication to addressing from single-chip microcomputer, host scm visits from single-chip microcomputer by different addresses.Owing to have only one group of data line, so at one time in, host scm can only communicate with a single-chip microcomputer.If visit one time from single-chip microcomputer, host scm will at first send some visit orders from single-chip microcomputer so, could visit after waiting it to reply next from single-chip microcomputer.With regard to a large amount of time of waste, reduced the work efficiency of TT﹠C system like this.In some supervision computer control system (SCC) and collective and distributive type control system (DCS), host scm often need be visited from single-chip microcomputer simultaneously, requirement responds the visit order of host scm simultaneously from the monolithic function, and at this moment, existing topological type bus structure just can not meet the demands.

Summary of the invention

Problem in view of present technology existence, it is a kind of simple in structure that the utility model provides, module based on FPGA integrated 16 simple UART of design (the universal asynchronous transmitting apparatus of accepting), host scm links to each other with FPGA, FPGA links to each other from single-chip microcomputer with 16 respectively by 16 UART, realize that a host scm visits 16 simultaneously from single-chip microcomputer, make the topological type bus structure satisfy system requirements.

The technical solution of the utility model is: based on the single-chip microcomputer multi-computer serial communication system of FPGA is to adopt FPGA (field programmable gate array circuit) to realize the serial communication system of integrated 16 simple UART (universal asynchronous receiver/ transmitter), system mainly by microcomputer, 1 host scm, 1 FPGA, 16 form from single-chip microcomputer.It is characterized in that: computing machine, host scm, FPGA connect successively, and FPGA is connected from single-chip microcomputer with 16 respectively.Described single-chip microcomputer multi-computer serial communication system based on FPGA, wherein, computing machine is connected by USB (universal serial bus) RS232/485/422 with host scm, and host scm is that FPGA is connected by USB (universal serial bus) RS232/485/422 from single-chip microcomputer with 16 by parallel port and FPGA communication.

The utility model is simple in structure, module based on FPGA integrated 16 simple UART of design (the universal asynchronous transmitting apparatus of accepting), host scm links to each other with FPGA, FPGA links to each other from single-chip microcomputer with 16 respectively by 16 UART, realize that a host scm visits 16 simultaneously from single-chip microcomputer, when host scm need be visited from single-chip microcomputer simultaneously, a plurality of visit orders that respond host scm from the monolithic function simultaneously, can satisfy the requirement of system, by this system, main frame can be visited 16 simultaneously from single-chip microcomputer.This module communication mode is observed general serial communication protocol fully.In supervision computer control system (SCC) and collective and distributive type control system (DCS), have a wide range of applications.

Description of drawings

Fig. 1. single-chip microcomputer multi-computer communication principle schematic, and as Figure of abstract;

Fig. 2. host scm serial ports and network interface connection diagram;

Fig. 3 .FPGA inner function module synoptic diagram;

Fig. 4. the finite state machine state transition diagram.

Embodiment

As shown in Figures 1 to 4, host scm can be controlled from single-chip microcomputer simultaneously, and can gather the information of uploading from single-chip microcomputer simultaneously, judges and sends host computer to.The host scm function mainly contains: 1) communicate by letter with host computer, receive host computer order and parsing; 2) control downwards from single-chip microcomputer according to the host computer order; Whether 3) monitor the various indexs of uploading from single-chip microcomputer is meeting the requirements; 4) provide alarm to show.

As shown in Figure 1, FPGA finishes the multiple connection of separating multiple connection and uploading information from single-chip microcomputer of host scm order.For receiving the order that host scm issues by FPGA, finish control and uploading device state from the single-chip microcomputer major function to equipment.The single-chip microcomputer that uses in the utility model is the XC3S100E of XILINX company as the C8051F series monolithic of Cygnal company, FPGA.The C8051F series monolithic is the high-end single-chip microcomputer of Cygnal company exploitation, instruction and 8051 compatibilities, the highest processing power with 25MIPS, simultaneously integrated abundant peripheral hardwares such as ADC, DAC, programmable amplifier, voltage comparator, sensor are fit to be applied to measurement and control area very much.The C8051F series monolithic also has jtag interface, makes things convenient for user's on-line debugging, has greatly saved user's development time.Host scm adopts the C8051F020 single-chip microcomputer, and this single-chip microcomputer provides 2 serial ports, an I2C interface (SMBus), and the parallel port of P0～P3 or P4 ~ P7 is provided.Among the design, special function register EMIOCF=0x27 is set, makes external memory interface be operated in the address/data multiplex mode, select high port P4～P7.Special function register XBRO=0x15 is set, serial ports UARTO and SMBus are mapped to the P0 port.

C8051F020 is considered as external memory storage with FPGA, and P4 ~ P7 conducts interviews by the parallel port; C8051F020 connects serial EEPROM by the SMBus interface, and system information is write EEPROM in real time, reads the data in the EEPROM when powering on after the unexpected power down of system, finishes system's power-down protection.The instruction that the round-the-clock analysis of host scm is uploaded from single-chip microcomputer, the state of judgment device provide alarm and show, deposit the internal buffer simultaneously in and wait for the host computer inquiry.

As shown in the figure, 2C8051F020 provides 2 kinds of modes of serial ports and network interface to communicate by letter with host computer, and two interfaces can not use simultaneously.Network service adopts network interface serial ports modular converter to realize, network interface and serial ports are connected to the UARTO of C8051F020 by combinational logic circuit, realizes the local monitor and the remote monitoring function of system.

The design of FPGA is the core of communication network, and according to functional requirement, the FPGA internal separation becomes four big functional modules: the SRAM controller, send data buffering module, 16 UART modules, receive the data buffering module.Send the data buffering Module Division and become 16 RAM districts, each RAM district connects a UART respectively, and after the transmission buffer module received the control data that host scm issues, startup UART was sent to data from single-chip microcomputer; Send buffer is divided into 16 RAM districts equally, after sending the control control data, UART is sent to UART module from single-chip microcomputer with last state periodically to from single-chip microcomputer transmit status querying command, and the UART module deposits data in and accepts the corresponding RAM of buffer module district.As Fig. 3.FPGA inside has 16 pairs of read-writes and data bus, connects UART and corresponding buffer zone RAM of transmission and send buffer RAM respectively.

The FPGA internal module adopts top-down method for designing, and complication system is divided into single system, realizes each functions of modules by logic and Interface design then.The SRAM controller is used for the interface of FPGA and C8051F020, is responsible for the read-write control of internal RAM.UART is responsible for receiving the serial signal of uploading from single-chip microcomputer, its parallelization is deposited in accept data buffering RAM; The serial signal that the also responsible in addition data-switching that will send in the buffer RAM becomes to meet the RS232 protocol specification sends to from single-chip microcomputer.SRAM controller and UART module are same to adopt top-down mode to realize, about the FPGA implementation of SRAM controller and UART detailed argumentation is arranged in list of references, and this paper no longer introduces.The FPGA built-in system adopts the method for designing of synchronous finite state machine (FSM) to realize that FSM is responsible for allocating the cooperation between each functional module.State machine adopts solely heat (one-hot) coding, and the reliability of circuit and speed are increased significantly.The system state transition diagram as shown in Figure 4.

The traffic rate of host scm and host computer and FPGA and all be set to 38.4Kbps from the traffic rate of single-chip microcomputer mainly can more accurate control host scms and each is from the call duration time between the single-chip microcomputer.Communication instruction is made up of part fields such as header, device type, device number, command number, order data, verifications, header is used to notify single-chip microcomputer to begin serial communication, device type and device number are used for instruction and correctly are communicated to corresponding apparatus, command number is used to notify the function of single-chip microcomputer instruction, order data is used to notify the function of monolithic facility body, CRC check is adopted in verification, guarantees the accuracy of communication, avoids the false command EVAC (Evacuation Network Computer Model).The frame format of communication instruction is as follows, writes control command number and is 00H, and reading order number is 01H, and the reading command order data is 0 byte.

Header	Device type	Device number	Command number	Order data	Verification and
Header	Device type	Device number	Command number	Order data	Verification and	1 byte	1 byte	1 byte	1 byte	N byte	1 byte

Single-chip microcomputer receives the back after control command, if receive correctly, returns 00H, as if mistake, returns 01H, returns frame format and is:

Header	Device type	Device number	Command number	The result	Verification and
Header	Device type	Device number	Command number	The result	Verification and	1 byte	1 byte	1 byte	1 byte	1 byte	1 byte

Reading command does not have order data, and frame format is:

Header	Device type	Device number	Command number	Verification and
Header	Device type	Device number	Command number	Verification and	1 byte	1 byte	1 byte	1 byte	1 byte

Reception back single-chip microcomputer returns frame format and is:

Header	Device type	Device number	Command number	Equipment state	Verification and
Header	Device type	Device number	Command number	Equipment state	Verification and	1 byte	1 byte	1 byte	1 byte	N byte	1 byte

Claims

1. single-chip microcomputer multi-computer serial communication system based on FPGA, mainly form from single-chip microcomputer by microcomputer, host scm, FPGA, 16, it is characterized in that: computing machine, host scm, FPGA connect successively, and FPGA is connected from single-chip microcomputer with 16 respectively.

2. the single-chip microcomputer multi-computer serial communication system based on FPGA as claimed in claim 1, it is characterized in that: computing machine is connected by USB (universal serial bus) RS232/485/422 with host scm, host scm is that FPGA is connected by USB (universal serial bus) RS232/485/422 from single-chip microcomputer with 16 by parallel port and FPGA communication.