CN110471880A - A kind of ARINC429 bus module and its data transmission method for supporting No. Label screening based on FPGA - Google Patents
A kind of ARINC429 bus module and its data transmission method for supporting No. Label screening based on FPGA Download PDFInfo
- Publication number
- CN110471880A CN110471880A CN201910656952.1A CN201910656952A CN110471880A CN 110471880 A CN110471880 A CN 110471880A CN 201910656952 A CN201910656952 A CN 201910656952A CN 110471880 A CN110471880 A CN 110471880A
- Authority
- CN
- China
- Prior art keywords
- arinc429
- data
- parameter
- configuration
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Communication Control (AREA)
Abstract
The invention discloses the ARINC429 bus modules that No. Label screening is supported based on FPGA, for realizing the transmission of data between ARINC429 bus and main control device, comprising: ARINC429 communication module, core main control module, communication configuration module and serial communication module；The invention also discloses the data transmission methods based on above-mentioned bus module；The present invention is designed using fpga chip, realize that communication parameter configuration logic, ARINC429 receive the screening of data and sending logic, serial data send and receive logic using FPGA and EEPROM, fpga chip carries ARINC429 protocol chip, for sending and receiving ARINC429 signal, simultaneously using the communication between serial ports RS422 building ARINC429 bus module and main control device, the reliability and stability of communication are improved.The flexible configurability and fast parallel property, the screening, filtering and the effective of signal for realizing configuration and the ARINC429 signal to messaging parameter for taking full advantage of FPGA quickly and accurately transmit.
Description
Technical field
The present invention relates to bus signals processing technology fields, more particularly to a kind of to support Label based on FPGA
Number screening ARINC429 bus module and its data transmission method.
Background technique
With the continuous development of avionics system, need to carry out a large amount of information exchange, people between each avionic device
Requirement to Avionics data bus improves gradually.In numerous Avionics data bus, ARINC429 bus is stable by its performance, structure is simple
The advantages that list, high reliablity, strong antijamming capability, is widely used in aerospace craft, even more accounts in large-scale seating plane field
According to dominant position, and the communication protocol design high speed transceiver interface circuit according to ARINC429 data/address bus is to realize ARINC429
The key of communication.
There is shortcomings for the ARINC429 bus interface of domestic development exploitation at present, for example use microcomputer development
ARINC429 communication board, it is difficult to guarantee 4 bit intervals between adjacent ARINC429 data word, and hardware circuit is complicated, integrated
It spends not high；And ARINC429 interface is developed using DSP, periphery needs to expand many digital circuits, is unable to reach system most
Smallization.It is expensive for the ARINC429 communication board of present commercialization, and relative coding format is fixed, and uses not enough
Flexibly and easily, thus researcher is needed to find corresponding solution.
On the other hand, the parameter information from each avionic device is deliver in ARINC429 communication bus, it is right
It for some receiving device, does not need to receive all signals, it is therefore necessary to the ARINC429 data received
It is screened.The prior art mainly uses pci bus or Ethernet as the expansion interface of ARINC429 bus interface module,
Structure is complicated for pci bus, and power consumption is high, and environmental suitability is poor, is not suitable for working under airborne strong vibration environment, and network interface there is also
The unfixed disadvantage of network delay.
In conclusion develop it is a kind of can effectively to signal carry out screening and accuracy height be capable of flexible configuration
The problem of ARINC429 bus interface module is those skilled in the art's urgent need to resolve.
Summary of the invention
In view of this, the present invention provides the wide ARINC429 bus module of a kind of strong real-time, versatility and its data
Transmission method, during being communicated with ARINC429 bus, the purpose of the application is received in 4bits word interval
ARINC429 signal and it is screened and be converted into serial data pass through serial ports send.
To achieve the goals above, the present invention adopts the following technical scheme:
A kind of ARINC429 bus module for being supported No. Label screening based on FPGA, is set for realizing 429 buses with master control
The transmission of data between standby, comprising: ARINC429 communication module, core main control module, communication configuration module and serial communication mould
Block；
It is described including ARINC429 protocol chip and ARINC429 interface circuit in the ARINC429 communication module
ARINC429 protocol chip is connected with the ARINC429 interface circuit, described in the ARINC429 interface circuit connection
ARINC429 bus, and the ARINC429 interface circuit is connected with the core main control module, the ARINC429 agreement core
Piece sends and receivees for realizing ARINC429 data；
It include fpga chip, the fpga chip and the ARINC429 interface circuit phase in the core main control module
Even, the fpga chip is for realizing communication parameter configuration logic and communication logic；
The communication parameter configuration logic for realizing messaging parameter configuration；
The communication logic include conversion logic and screening logic, the conversion logic for realizing serial data with it is described
Conversion between ARINC429 data, the screening logic is for realizing based on No. Label sieve to the ARINC429 data
Choosing；
In the communication configuration module include eeprom chip, the eeprom chip respectively with the fpga chip phase
Even, the eeprom chip is for realizing the write-in and reading to messaging parameter, and the fpga chip is for completing messaging parameter
Configuration；
It is described asynchronous including asynchronous RS232 communicating circuit and asynchronous RS422 communicating circuit in the serial communication module
RS232 communicating circuit is connected by RS232 serial ports with the fpga chip, and the asynchronous RS422 communicating circuit is gone here and there by RS422
Mouth is connected with the fpga chip, and the asynchronous RS422 communicating circuit is connected with the main control device；
The asynchronous RS232 communicating circuit is for being modified the messaging parameter, the asynchronous RS422 communicating circuit
For export by screening the ARINC429 data be transmitted to the main control device, according to asynchronous RS422 communications protocol with
The main control device communication.
It preferably, include configuration parameter registers in the fpga chip, the configuration parameter registers include that RS422 matches
Set parameter register and ARINC429 configuration parameter registers；
The RS422 configuration parameter registers and the ARINC429 configuration parameter registers with the eeprom chip
It is connected, the RS422 configuration parameter registers are for storing RS422 serial communication parameter；The ARINC429 configuration parameter is posted
Storage is for storing parameter relevant to ARINC429 communication；
Wherein, the RS422 serial communication parameter includes the setting parameter of traffic rate and parity check bit；With it is described
It includes traffic rate, byte digit, parity check system, SDI code and No. Label that ARINC429, which communicates relevant parameter,.
It preferably, further include FIFO memory in the fpga chip, the FIFO memory is stored including the first FIFO
Device and the second FIFO memory；The write-in bit wide of first FIFO memory is 8bits, and reading bit wide is 16bits, described
It is 16bits that bit wide, which is written, in second FIFO memory, and reading bit wide is 8bits；
First FIFO memory is connected with the ARINC429 configuration parameter registers, after storing screening
ARINC429 data；
Second FIFO memory is connected with the RS422 serial ports, for storing serial data.
A kind of data transmission method of ARINC429 bus module that supporting No. Label screening based on FPGA, including it is following
Step:
S1:FPGA chip reads messaging parameter to eeprom chip, is completed by the fpga chip according to configuration logic
The configuration of parameter is reconfigured according to the messaging parameter after change；
S2: the received data of the fpga chip detection judge data type, and receive and dispatch to data；
S21: if the data detected are ARINC429 bus data, by the fpga chip according to screening logic to described
ARINC429 bus data is screened, and the ARINC429 bus data after screening is passed through asynchronous RS422 after conversion
Communicating circuit is sent to corresponding main control device by RS422 serial ports；
S22: if the data detected are serial data, the serial data is sent to after conversion described
ARINC429 bus.
Preferably, the specific steps of S1 are as follows:
RS422 configuration parameter registers read RS422 serial communication parameter out of described eeprom chip and complete configuration；
ARINC429 configuration parameter registers read parameter relevant to ARINC429 communication out of described eeprom chip,
And corresponding control word is written to the ARINC429 protocol chip and completes configuration；
Include traffic rate, byte digit, parity check system and SDI code information in the control word, and configures
Working condition after is to default working condition.
Preferably, the specific steps reconfigured according to the messaging parameter after change are as follows:
By the RS232 serial ports EEPROM core is written in new messaging parameter by the asynchronous RS232 communicating circuit
The messaging parameter stored before covering in piece, at the same time, the new messaging parameter writes direct the RS422 configuration parameter
In register, the change of the messaging parameter is completed in real time.
Preferably, the specific steps of S21 are as follows:
It (1), will be current in the ARINC429 protocol chip when detecting effective ARINC429 data
ARINC429 data are divided into the first byte and the second byte, and the 0-7bit of first byte represents currently received ARINC429
No. Label of data word；And data receiver request is issued to the ARINC429 configuration parameter registers；
(2) first byte and the second byte are successively passed through 16bits parallel data by the ARINC429 protocol chip
Line is transmitted to the ARINC429 configuration parameter registers；While receiving the second byte, by currently received ARINC429
No. Label of data is matched with No. Label in the ARINC429 configuration parameter registers, if being matched to identical
It No. Label, then will be in current ARINC429 data all the first FIFO memory of write-in；
(3) current ARINC429 data are sent to corresponding main control device by RS422 serial ports.
Preferably, the specific steps of S22 are as follows:
After detecting effective serial data, ARINC429 data parity check position is generated, current serial data is write
Enter in the second FIFO memory while serial data is converted to ARINC429 data, it is waiting to harvest complete ARINC429 data
Afterwards, the ARINC429 protocol chip is transmitted to by 16bits parallel data line, while provides corresponding control command, it is described
ARINC429 protocol chip will send data to the ARINC429 bus according to preconfigured messaging parameter.
It can be seen via above technical scheme that compared with prior art, the present disclosure provides one kind to be based on FPGA branch
Hold the ARINC429 bus module and its data transmission method of No. Label screening.
Firstly, the present invention is designed using fpga chip, using FPGA and EEPROM realize communication parameter configuration logic,
ARINC429 receives the screening of data and sending logic, serial data send and receive logic, and fpga chip carries
ARINC429 protocol chip constructs ARINC429 bus for sending and receiving ARINC429 signal, while using serial ports RS422
Communication between module and main control device improves the reliability and stability of communication.The flexible of FPGA is taken full advantage of to match
Setting property and fast parallel property realize having for the screening of configuration and the ARINC429 signal to messaging parameter, filtering and signal
Effect is quickly and accurately transmitted.
The messaging parameter of fpga chip is configured in real time secondly, RS232 can be used in the present invention, using silent when being not configured
Recognize working condition, its working method can be changed in real time, configurability is good, flexibility ratio is high.
Finally, also disclosing the method for the bus module data transmit-receive in the present invention, it is stored in ARINC429 data
The screening of data is carried out before FIFO memory to it, to alleviate the pressure of FIFO memory caching, while improving communication effect
Rate.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 attached drawing is structural schematic diagram provided by the invention；
Fig. 2 attached drawing is overall flow schematic diagram of the transmission ARINC429 data provided by the invention to main control device；
Fig. 3 attached drawing is overall flow schematic diagram of the reception serial data provided by the invention to ARINC429 bus.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Embodiment one:
No. Label ARINC429 bus module screened is supported based on FPGA present embodiment discloses a kind of, for realizing
The transmission of data between ARINC429 bus and main control device, as shown in Figure 1, comprising: ARINC429 communication module, core master control
Module, communication configuration module and serial communication module；
It include ARINC429 protocol chip and ARINC429 interface circuit, ARINC429 agreement in ARINC429 communication module
Chip is connected with ARINC429 interface circuit, and ARINC429 interface circuit connects ARINC429 bus, and ARINC429 interface electricity
Road is connected with core main control module, and ARINC429 protocol chip sends and receivees for realizing ARINC429 data；
It include fpga chip in core main control module, fpga chip is connected with ARINC429 interface circuit, and fpga chip is used
In realization communication parameter configuration logic and communication logic；
Communication parameter configuration logic for realizing messaging parameter configuration；
Communication logic includes conversion logic and screening logic, and conversion logic is for realizing serial data and ARINC429 data
Between conversion, screen logic for realizing based on No. Label screening to ARINC429 data；
It include eeprom chip in communication configuration module, eeprom chip is connected with fpga chip respectively, eeprom chip
For realizing the write-in and reading to messaging parameter, fpga chip is used to complete the configuration of messaging parameter；
It include asynchronous RS232 communicating circuit and asynchronous RS422 communicating circuit, asynchronous RS232 communication in serial communication module
Circuit is connected by RS232 serial ports with fpga chip, and asynchronous RS422 communicating circuit is connected by RS422 serial ports with fpga chip,
And asynchronous RS422 communicating circuit is connected with main control device；
For being modified to messaging parameter, asynchronous RS422 communicating circuit passes through asynchronous RS232 communicating circuit for exporting
The ARINC429 data of screening are transmitted to main control device, are communicated according to asynchronous RS422 communications protocol with main control device.
It in order to further optimize the above technical scheme, include configuration parameter registers, configuration parameter deposit in fpga chip
Device includes RS422 configuration parameter registers and ARINC429 configuration parameter registers；
RS422 configuration parameter registers and ARINC429 configuration parameter registers are connected with eeprom chip, and RS422 matches
Parameter register is set for storing RS422 serial communication parameter；ARINC429 configuration parameter registers for store with
ARINC429 communicates relevant parameter；
Wherein, RS422 serial communication parameter includes the setting parameter of traffic rate and parity check bit；It is logical with ARINC429
Believe that relevant parameter includes traffic rate, byte digit, parity check system, SDI code and No. Label.
It in order to further optimize the above technical scheme, further include FIFO memory in fpga chip, FIFO memory includes
First FIFO memory and the second FIFO memory；The write-in bit wide of first FIFO memory is 8bits, reads bit wide and is
16bits, it is 16bits that bit wide, which is written, in the second FIFO memory, and reading bit wide is 8bits；
First FIFO memory is connected with ARINC429 configuration parameter registers, for storing the ARINC429 number after screening
According to；
Second FIFO memory is connected with RS422 serial ports, for storing serial data.
The present invention gives full play to the advantage of the fast parallel property of fpga chip, using FPGA realize serial communication logic,
ARINC429 bus communication logic, data screening logic are realized communication configuration logic using FPGA cooperation EEPROM, can also be passed through
RS232 carries out the update configuration of messaging parameter, can change its working method in real time, configurability is good, flexibility ratio is high, and leads to
RS422 unofficial biography ARINC429 data are crossed, the reliability and stability of communication are improved；It is slow that FIFO can be effectively relieved in the use of FIFO
The pressure deposited, while improving communication efficiency.
Embodiment two:
Present embodiment discloses a kind of data transmission of ARINC429 bus module that No. Label screening is supported based on FPGA
Method, comprising the following steps:
S1:FPGA chip reads messaging parameter to eeprom chip, completes parameter according to configuration logic by fpga chip
Configuration or reconfigured according to the messaging parameter after change；
The received data of S2:FPGA chip detection, judge data type, and receive and dispatch to data；
S21: if the data detected are ARINC429 bus data, by fpga chip according to screening logic to 429 buses
Data are screened, and the ARINC429 bus data after screening is passed through after conversion by asynchronous RS422 communicating circuit
RS422 serial ports is sent to corresponding main control device；
S22: if the data detected are serial data, it is total that serial data is sent to ARINC429 after conversion
Line.
In order to further optimize the above technical scheme, the specific steps of S1 are as follows:
RS422 configuration parameter registers read RS422 serial communication parameter out of eeprom chip and complete configuration；
ARINC429 configuration parameter registers read parameter relevant to ARINC429 communication out of eeprom chip, and to
ARINC429 protocol chip is written corresponding control word and completes configuration；
It include traffic rate, byte digit, parity check system and SDI code information in control word, and after the completion of configuration
Working condition be default working condition.
In order to further optimize the above technical scheme, the specific steps reconfigured according to the messaging parameter after change
Are as follows:
New messaging parameter is written in eeprom chip before covering by RS232 serial ports for asynchronous RS232 communicating circuit
The messaging parameter of storage, at the same time, new messaging parameter write direct in RS422 configuration parameter registers, complete in real time logical
Believe the change of parameter.
In order to further optimize the above technical scheme, the specific steps of S21 are as follows:
(1) when detecting effective ARINC429 data, by current ARINC429 number in ARINC429 protocol chip
According to the first byte and the second byte is divided into, the 0-7bit of the first byte represents the Label of currently received ARINC429 data word
Number；And data receiver request is issued to ARINC429 configuration parameter registers；
(2) the first byte and the second byte are successively passed through 16bits parallel data line and are transmitted to by ARINC429 protocol chip
ARINC429 configuration parameter registers；While receiving the second byte, by No. Label of currently received ARINC429 data
It is matched with No. Label in ARINC429 configuration parameter registers, it, will be current if being matched to identical No. Label
ARINC429 data are all in the first FIFO memory of write-in；
(3) current ARINC429 data are sent to corresponding main control device by RS422 serial ports.
In order to further optimize the above technical scheme, the specific steps of S22 are as follows:
After detecting effective serial data, ARINC429 data parity check position is generated, current serial data is write
Enter in the second FIFO memory while serial data is converted to ARINC429 data, it is waiting to harvest complete ARINC429 data
Afterwards, ARINC429 protocol chip is transmitted to by 16bits parallel data line, while provides corresponding control command, ARINC429
Protocol chip will send data to ARINC429 bus according to preconfigured messaging parameter.
Specifically, as shown in Fig. 2, the present invention sends the overall flow of ARINC429 data to main control device are as follows:
(1) fpga chip control reads communication configuration parameter and completes configuration；
(2) ARINC429 receiving channel, serial ports sendaisle are opened, real-time monitoring ARINC429 bus data goes forward side by side one
Step detects whether that there are effective ARINC429 data, if so, then carrying out in next step, if nothing, continuing to test effective ARINC429
Data；
(3) effective ARINC429 data are matched with No. Label in ARINC429 configuration parameter registers,
Then ARINC429 data are sent into FIFO memory with success, unsuccessful then return step (2) is matched and detects again effectively
ARINC429 data；
(4) data being stored into FIFO memory are sent to main control device by 422 serial ports.
As shown in figure 3, the present invention receives the overall flow of serial data to ARINC429 bus are as follows:
(1) fpga chip control reads communication configuration parameter and completes configuration；
(2) serial ports receiving channel, ARINC429 sendaisle, real-time monitoring serial data are opened；
(3) detect whether that there are effective serial datas, if so, then carrying out in next step, if nothing, continuing to test effective string
Mouth data；
(4) serial data is sent into FIFO memory, and is sent data to by ARINC429 interface circuit
ARINC429 bus.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other
The difference of embodiment, the same or similar parts in each embodiment may refer to each other.For device disclosed in embodiment
For, since it is corresponded to the methods disclosed in the examples, so being described relatively simple, related place is said referring to method part
It is bright.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (8)
1. a kind of ARINC429 bus module for supporting No. Label screening based on FPGA, for realizing ARINC429 bus and master
Control the transmission of data between equipment characterized by comprising ARINC429 communication module, core main control module, communication configuration mould
Block and serial communication module；
It include ARINC429 protocol chip and ARINC429 interface circuit, the ARINC429 in the ARINC429 communication module
Protocol chip is connected with the ARINC429 interface circuit, and the ARINC429 interface circuit connects the ARINC429 bus,
And the ARINC429 interface circuit is connected with the core main control module, the ARINC429 protocol chip for realizing
ARINC429 data send and receive；
It include fpga chip in the core main control module, the fpga chip is connected with the ARINC429 interface circuit, institute
Fpga chip is stated for realizing communication parameter configuration logic and communication logic；
The communication parameter configuration logic for realizing messaging parameter configuration；
The communication logic include conversion logic and screening logic, the conversion logic for realizing serial data with it is described
Conversion between ARINC429 data, the screening logic is for realizing based on No. Label sieve to the ARINC429 data
Choosing；
It include eeprom chip in the communication configuration module, the eeprom chip is connected with the fpga chip respectively, institute
Eeprom chip is stated for realizing the write-in and reading to messaging parameter, the fpga chip is for completing matching for messaging parameter
It sets；
It include asynchronous RS232 communicating circuit and asynchronous RS422 communicating circuit, the asynchronous RS232 in the serial communication module
Communicating circuit is connected by RS232 serial ports with the fpga chip, the asynchronous RS422 communicating circuit pass through RS422 serial ports and
The fpga chip is connected, and the asynchronous RS422 communicating circuit is connected with the main control device；
For being modified to the messaging parameter, the asynchronous RS422 communicating circuit is used for the asynchronous RS232 communicating circuit
Export by screening the ARINC429 data be transmitted to the main control device, according to asynchronous RS422 communications protocol with it is described
Main control device communication.
2. a kind of ARINC429 bus module for supporting No. Label screening based on FPGA according to claim 1, feature
It is, includes configuration parameter registers in the fpga chip, the configuration parameter registers includes the deposit of RS422 configuration parameter
Device and ARINC429 configuration parameter registers；
422 configuration parameter registers and the ARINC429 configuration parameter registers are connected with the eeprom chip,
The RS422 configuration parameter registers are for storing RS422 serial communication parameter；The ARINC429 configuration parameter registers are used
In storage parameter relevant to ARINC429 communication；
Wherein, the RS422 serial communication parameter includes the setting parameter of traffic rate and parity check bit；With it is described
It includes traffic rate, byte digit, parity check system, SDI code and No. Label that ARINC429, which communicates relevant parameter,.
3. a kind of ARINC429 bus module for supporting No. Label screening based on FPGA according to claim 2, feature
It is, further includes FIFO memory in the fpga chip, the FIFO memory includes the first FIFO memory and second
FIFO memory；The write-in bit wide of first FIFO memory is 8bits, and reading bit wide is 16bits, the 2nd FIFO
It is 16bits that bit wide, which is written, in memory, and reading bit wide is 8bits；
First FIFO memory is connected with the ARINC429 configuration parameter registers, after storing screening
ARINC429 data；
Second FIFO memory is connected with the RS422 serial ports, for storing serial data.
4. a kind of data transmission method for the ARINC429 bus module for supporting No. Label screening based on FPGA, which is characterized in that
The following steps are included:
S1:FPGA chip reads messaging parameter to eeprom chip, completes parameter according to configuration logic by the fpga chip
Configuration or reconfigured according to the messaging parameter after change；
S2: the received data of the fpga chip detection judge data type, and receive and dispatch to data；
S21: if the data detected are ARINC429 bus data, by the fpga chip according to screening logic to described
ARINC429 bus data is screened, and the ARINC429 bus data after screening is passed through asynchronous RS422 after conversion
Communicating circuit is sent to corresponding main control device by RS422 serial ports；
S22: if the data detected are serial data, the serial data is sent to the ARINC429 after conversion
Bus.
5. a kind of data of ARINC429 bus module for supporting No. Label screening based on FPGA according to claim 4
Transmission method, which is characterized in that the specific steps of S1 are as follows:
RS422 configuration parameter registers read RS422 serial communication parameter out of described eeprom chip and complete configuration；
ARINC429 configuration parameter registers read parameter relevant to ARINC429 communication out of described eeprom chip, and to
The ARINC429 protocol chip is written corresponding control word and completes configuration；
It include traffic rate, byte digit, parity check system and SDI code information in the control word, and after the completion of configuration
Working condition be default working condition.
6. a kind of ARINC429 bus module for supporting No. Label screening based on FPGA according to claim 4, feature
It is, the specific steps reconfigured according to the messaging parameter after change are as follows:
New messaging parameter is written in the eeprom chip by the RS232 serial ports for the asynchronous RS232 communicating circuit
The messaging parameter stored before covering, at the same time, the new messaging parameter write direct the RS422 configuration parameter deposit
In device, the change of the messaging parameter is completed in real time.
7. a kind of data of ARINC429 bus module for supporting No. Label screening based on FPGA according to claim 4
Transmission method, which is characterized in that the specific steps of S21 are as follows:
(1) when detecting effective ARINC429 data, by current ARINC429 number in the ARINC429 protocol chip
According to the first byte and the second byte is divided into, the 0-7bit of first byte represents currently received ARINC429 data word
No. Label；And data receiver request is issued to the ARINC429 configuration parameter registers；
(2) first byte and the second byte are successively passed through 16bits parallel data line and passed by the ARINC429 protocol chip
Transport to the ARINC429 configuration parameter registers；While receiving the second byte, by currently received ARINC429 data
No. Label and the ARINC429 configuration parameter registers in No. Label matched, if being matched to identical Label
Number, then it will be in current ARINC429 data all the first FIFO memory of write-in；
(3) current ARINC429 data are sent to corresponding main control device by RS422 serial ports.
8. a kind of ARINC429 bus module for supporting No. Label screening based on FPGA according to claim 4, feature
It is, the specific steps of S22 are as follows:
After detecting effective serial data, ARINC429 data parity check position is generated, by current serial data write-in the
Serial data is converted to ARINC429 data simultaneously in two FIFO memories, it is waiting harvest complete ARINC429 data after, lead to
It crosses 16bits parallel data line and is transmitted to the ARINC429 protocol chip, while providing corresponding control command, it is described
ARINC429 protocol chip will send data to the ARINC429 bus according to preconfigured messaging parameter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910656952.1A CN110471880B (en) | 2019-07-19 | 2019-07-19 | ARINC429 bus module supporting Label number screening based on FPGA and data transmission method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910656952.1A CN110471880B (en) | 2019-07-19 | 2019-07-19 | ARINC429 bus module supporting Label number screening based on FPGA and data transmission method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110471880A true CN110471880A (en) | 2019-11-19 |
| CN110471880B CN110471880B (en) | 2021-01-12 |
Family
ID=68508242
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910656952.1A Active CN110471880B (en) | 2019-07-19 | 2019-07-19 | ARINC429 bus module supporting Label number screening based on FPGA and data transmission method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110471880B (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111121763A (en) * | 2019-12-09 | 2020-05-08 | 重庆鲲量科技有限公司 | FPGA-based data analysis method in optical fiber inertial navigation |
| CN112231266A (en) * | 2020-10-15 | 2021-01-15 | 天津津航计算技术研究所 | ARINC429 bus control method based on lookup table |
| CN113127400A (en) * | 2019-12-31 | 2021-07-16 | 中国科学院长春光学精密机械与物理研究所 | FPGA-based multi-channel serial port server and data transmission method thereof |
| CN113255156A (en) * | 2021-06-11 | 2021-08-13 | 中国商用飞机有限责任公司 | Loop real-time simulation system and method for civil aircraft ground dynamic test signals |
| CN115550098A (en) * | 2022-09-16 | 2022-12-30 | 哈尔滨工业大学 | ARINC429 bus communication assembly and device based on MiniVPX framework |
| CN115828814A (en) * | 2023-02-13 | 2023-03-21 | 中兵通信科技股份有限公司 | Circuit design method of ARINC429 protocol soft core based on FPGA |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080133805A1 (en) * | 2005-07-04 | 2008-06-05 | Shenzhen Donjin Communication Tech Co., Ltd. | Interface Card and Cti System Applying Interface Cards |
| CN201583945U (en) * | 2009-12-02 | 2010-09-15 | 天津光电通信技术有限公司 | Serial communication system for multiple singlechips based on FPGA |
| US20110071709A1 (en) * | 2009-09-23 | 2011-03-24 | Eurocopter | Highly representative real-time simulation of an avionics system |
| CN202339544U (en) * | 2011-12-12 | 2012-07-18 | 西安瑞日电子发展有限公司 | Multi-channel and multi-rate avionic communication device based on USB (universal serial bus) interface |
| CN104021102A (en) * | 2014-05-26 | 2014-09-03 | 北京佳讯飞鸿电气股份有限公司 | CPCI serial port plate based on state machine and on-chip bus and working method of CPCI serial port plate |
| CN105116772A (en) * | 2015-07-15 | 2015-12-02 | 中国航空工业集团公司上海航空测控技术研究所 | Device used for aircraft cabin interface management and operation method |
| CN106331056A (en) * | 2016-08-11 | 2017-01-11 | 四川九洲电器集团有限责任公司 | Data format conversion device and airborne electronic mission system |
| CN208460081U (en) * | 2018-07-31 | 2019-02-01 | 山东欧龙电子科技有限公司 | A kind of flying quality collector |
| CN109445325A (en) * | 2018-10-15 | 2019-03-08 | 四川九洲空管科技有限责任公司 | A kind of high speed ARINC429 data processing method based on FPGA |
-
2019
- 2019-07-19 CN CN201910656952.1A patent/CN110471880B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080133805A1 (en) * | 2005-07-04 | 2008-06-05 | Shenzhen Donjin Communication Tech Co., Ltd. | Interface Card and Cti System Applying Interface Cards |
| US20110071709A1 (en) * | 2009-09-23 | 2011-03-24 | Eurocopter | Highly representative real-time simulation of an avionics system |
| CN201583945U (en) * | 2009-12-02 | 2010-09-15 | 天津光电通信技术有限公司 | Serial communication system for multiple singlechips based on FPGA |
| CN202339544U (en) * | 2011-12-12 | 2012-07-18 | 西安瑞日电子发展有限公司 | Multi-channel and multi-rate avionic communication device based on USB (universal serial bus) interface |
| CN104021102A (en) * | 2014-05-26 | 2014-09-03 | 北京佳讯飞鸿电气股份有限公司 | CPCI serial port plate based on state machine and on-chip bus and working method of CPCI serial port plate |
| CN105116772A (en) * | 2015-07-15 | 2015-12-02 | 中国航空工业集团公司上海航空测控技术研究所 | Device used for aircraft cabin interface management and operation method |
| CN106331056A (en) * | 2016-08-11 | 2017-01-11 | 四川九洲电器集团有限责任公司 | Data format conversion device and airborne electronic mission system |
| CN208460081U (en) * | 2018-07-31 | 2019-02-01 | 山东欧龙电子科技有限公司 | A kind of flying quality collector |
| CN109445325A (en) * | 2018-10-15 | 2019-03-08 | 四川九洲空管科技有限责任公司 | A kind of high speed ARINC429 data processing method based on FPGA |
Non-Patent Citations (3)
| Title |
|---|
| OLYPER: ""基于FPGA设计的RS422-Arinc429通讯模块及软件"", 《百度文库》 * |
| XUE HONGLIN; GUI HONGYUN; HONG XUEHUAN; WU ZHAOJUN; WANG QIANG: ""Design and Implementation of the ARINC429 Bus Protocol Converter"", 《PROCESS AUTOMATION INSTRUMENTATION》 * |
| 张德银: "《民航飞机航电设备故障检测与诊断》", 31 May 2017 * |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111121763A (en) * | 2019-12-09 | 2020-05-08 | 重庆鲲量科技有限公司 | FPGA-based data analysis method in optical fiber inertial navigation |
| CN113127400A (en) * | 2019-12-31 | 2021-07-16 | 中国科学院长春光学精密机械与物理研究所 | FPGA-based multi-channel serial port server and data transmission method thereof |
| CN113127400B (en) * | 2019-12-31 | 2023-04-18 | 中国科学院长春光学精密机械与物理研究所 | FPGA-based multi-channel serial port server and data transmission method thereof |
| CN112231266A (en) * | 2020-10-15 | 2021-01-15 | 天津津航计算技术研究所 | ARINC429 bus control method based on lookup table |
| CN112231266B (en) * | 2020-10-15 | 2023-03-24 | 天津津航计算技术研究所 | ARINC429 bus control method based on lookup table |
| CN113255156A (en) * | 2021-06-11 | 2021-08-13 | 中国商用飞机有限责任公司 | Loop real-time simulation system and method for civil aircraft ground dynamic test signals |
| CN113255156B (en) * | 2021-06-11 | 2023-09-01 | 中国商用飞机有限责任公司 | Loop real-time simulation system and method for civil aircraft ground dynamic test signals |
| CN115550098A (en) * | 2022-09-16 | 2022-12-30 | 哈尔滨工业大学 | ARINC429 bus communication assembly and device based on MiniVPX framework |
| CN115828814A (en) * | 2023-02-13 | 2023-03-21 | 中兵通信科技股份有限公司 | Circuit design method of ARINC429 protocol soft core based on FPGA |
| CN115828814B (en) * | 2023-02-13 | 2023-05-12 | 中兵通信科技股份有限公司 | Circuit design method of ARINC429 protocol soft core based on FPGA |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110471880B (en) | 2021-01-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110471880A (en) | A kind of ARINC429 bus module and its data transmission method for supporting No. Label screening based on FPGA | |
| CN102760111B (en) | FPGA-based (Field Programmable Gate Array) extended multi-serial port device and data receiving-transmitting method thereof | |
| CN102647320B (en) | Integrated circuit suitable for high-speed 1553 bus protocol control | |
| CN101571842B (en) | PCI integrated circuit board device used for ARINC429 communication | |
| CN104954096B (en) | A kind of high-speed synchronous serial communication data transmission method of one master and multiple slaves | |
| CN105573239A (en) | High speed backboard bus communication control device and method | |
| CN108228513A (en) | A kind of intelligent serial communication module and control method based on FPGA architecture | |
| CN103942014B (en) | FC-AE-1553 protocol interface card storage mapping device and storage mapping method | |
| CN205229465U (en) | Baseband chip and multimode GNSS receiver of multimode GNSS receiver | |
| CN105553883A (en) | Multi-DSP data exchange apparatus based on FPGA | |
| CN104679702A (en) | Multi-path high-speed serial interface controller | |
| CN107436851A (en) | The line shielding system of Serial Peripheral Interface (SPI) four and its control method | |
| CN102075397A (en) | Direct interfacing method for ARINC429 bus and high-speed intelligent unified bus | |
| CN104380273B (en) | The adaptive offset synchronous of data based on circular buffer | |
| CN108429707B (en) | Time trigger service repeater and method adapting to different transmission rates | |
| CN206461608U (en) | Transceiver based on ethernet physical layer chip rate continuous variable | |
| CN105472782A (en) | Wireless communication terminal | |
| WO2021109525A1 (en) | Method for digital wave control signal interface of large-scale antenna array | |
| CN106059927B (en) | A kind of automatic reconstructed network routing device of the limited cascade of hub-and-spoke configuration and its network | |
| CN103107862A (en) | Logic device and management data input/output (MDIO) data transmission method thereof | |
| CN203554492U (en) | Controller LAN bus intelligent interface device and satellite | |
| CN107066419A (en) | Expansible adaptive N × N channel data communication system | |
| CN108268416B (en) | Asynchronous interface to synchronous interface control circuit | |
| CN105007151A (en) | High/low-speed bus communication method and device | |
| CN207503220U (en) | A kind of circuit for extending microcontroller serial port and Modbus buses |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |