WO2021109525A1

WO2021109525A1 - Method for digital wave control signal interface of large-scale antenna array

Info

Publication number: WO2021109525A1
Application number: PCT/CN2020/095236
Authority: WO
Inventors: 赵涤燹
Original assignee: 南京汇君半导体科技有限公司
Priority date: 2019-12-03
Filing date: 2020-06-09
Publication date: 2021-06-10
Also published as: CN110932748A; CN110932748B

Abstract

Disclosed is a solution for a digital wave control signal interface of a large-scale antenna array. The present invention uses an improved SPI four-wire interface solution, in which a digital logic module having an SPI slave interface is integrated to a radio frequency front end, and uses a communication protocol added with ID tags, such that a single SPI host controller in a large-scale antenna system (such as 1024 antennas) can control all antenna units separately or control the antenna units as a whole. The interface solution improves on conventional SPI control solutions by reducing the number of required interfaces and wires to only four, such that a low-cost FPGA or MCU can be used as a host controller without having to wastefully provide additional interfaces. Another advantage of the invention is that the board-level wiring of the antenna array is simple. The invention reduces the number of required PCB wiring layers to two, and provides a feasible wiring solution.

Description

A large-scale antenna array digital wave control signal interface scheme

Technical field

The invention relates to a digital wave control signal interface scheme for a large-scale antenna array, which belongs to the technical field of electronic circuit design, and is particularly suitable for the design of a large-scale antenna array.

Background technique

In the hardware foundation of satellite communications and radar technology, large-scale antenna arrays are indispensable key modules. In order to transmit and receive electromagnetic waves in different directions, the transceiver needs to constantly adjust the gain and phase of each antenna in the antenna array. After entering the era of 5G and millimeter waves, the throughput and reliability requirements of communications have greatly increased, the number of antennas used has increased significantly, the arrays have become denser, and the difficulty of achieving accurate, real-time, and efficient digital wave control signal interfaces has become more difficult.

Traditional antenna array control uses Serial Peripheral Interface (SPI) for one-to-one, full-duplex communication between the controller and the RF front-end chip. As shown in Figure 1 (a), the traditional control scheme has the advantages of simple implementation and low logic complexity of the on-chip digital module when the number of antenna arrays is small. When the chip select signal SS corresponding to the kth SPI slave is pulled low, it is selected and the host can communicate with it. However, for an N×N antenna array, ^{when the number of antennas N 2} increases, the number of board-level control signal lines tends to triple the number of antennas (3N ² +1), which makes board-level wiring difficult. Increased, the interface overhead of the SPI host controller is large and the efficiency is low. Take the 32×32 (N=32) antenna array used in millimeter wave communication as an example. The number of interfaces required to use the SPI host is 3073, which means that the same number of controls must be arranged on the PCB board. Signal line, this is obviously difficult to achieve. The reasons are as follows: On the one hand, the number of interfaces of a general single FPGA chip is limited, and it is difficult to reach 3073; on the other hand, ordinary double-layer PCB boards are also difficult to arrange so many signal lines, which may require four-layer boards or even More layers increase the PCB area and cost.

Summary of the invention

In this design, through the improvement and optimization of the traditional SPI protocol, a four-wire solution is proposed to realize the communication scheme of the SPI host controller and large-scale antenna array. Different digital ID tags are added to each RF front-end chip in the antenna array. This solution can realize low-cost, one-to-many, full-duplex digital wave control signal interface. Since only four signal lines are used, an ordinary low-cost double-sided PCB can be used to realize the antenna array design when a low-cost MCU or a single-chip small-capacity FPGA is used as the host. At the same time, this design provides a feasible SPI slave circuit design scheme.

In order to achieve the above objectives, the present invention adopts the following technical solutions:

A large-scale antenna array digital wave control signal interface solution. Each phased array chip in the antenna array integrates a digital logic module with an SPI slave interface. The communication protocol with ID tags is used to realize a single SPI master. The controller individually controls all the antenna units in the antenna array or controls all the antenna units. Among them, each RF front end in the antenna array has a different digital ID tag;

The digital logic module includes a core control logic module based on the Moore finite state machine, a reset control module, an error mechanism module, a general register, a phased array amplitude and phase register, and an SPI slave; the SPI slave connects the SPI master The transmission frame of the transmission frame is transmitted to the core control logic module, and the transmission frame includes the digital ID and the amplitude and phase code; the core control logic module controls the reading and writing of the general register, if and only if the ID in the transmission frame corresponds to the digital logic module When the digital ID of the RF front-end is the same, the core control logic module assigns the amplitude and phase codes to the phased array amplitude and phase control registers through the general-purpose register, and the phased array amplitude and phase control registers are directly connected to the RF front end; error mechanism module When the sending frame is turned on, when a frame error is found through the frame length check and CRC detection, the communication between the general register and the phased array amplitude and phase register and the SPI slave interface is automatically closed, and the frame error is recorded in the general register. When the SPI master makes an error inquiry, it will give feedback through the MISO port of the SPI slave. After the SPI master sends a reset frame, it will reset sequentially under the control of the reset control module.

Further, the SCLK, MOSI, MISO and SS four interfaces of the SPI slave correspond to the SCLK, MOSI, MISO and SS four interfaces of the SPI master respectively. Among them, SCLK is the system synchronization clock of the SPI master and slave, and SS is Low-level active chip select synchronization signal, MOSI is the interface of master output/slave input, and MISO is the interface of slave output/host input.

Furthermore, the MISO of only one SPI slave is in the output state at any time, and the MISO of the remaining SPI slaves are in the high-impedance state.

Further, the communication protocol added to the ID tag is: the writing and output of the SPI interface are in units of frames; the SPI host outputs MOSI on the falling edge of SCLK, and MISO is sampled on the falling edge of SCLK; when SS changes from high to low, phase control When the array chip is selected, the serial input signal of MOSI starts to be stored in the buffer in the phased array chip until the serial input signal is all stored, and when SS changes from low to high, data processing starts, reading and writing the corresponding registers, And prepare the output of MISO; when SS is high, the rising edge of SCLK resets the state machine of the phased array chip, and SPI is in the standby state; when the MODE register inside the phased array chip is 1, SPI works in the state of identifying digital ID, Read and write, and the digital ID must be correct to read and write. Once the digital ID is incorrect, the SPI slave immediately enters the standby state; when the MODE register is 0, it is in the no ID state, which can only be written but not read.

Technical effect

Compared with the prior art, the technical solution of the present invention has the following advantages:

The invention adopts an improved SPI four-wire interface scheme, integrates a digital logic module with an SPI slave interface in the radio frequency front end, and adopts a communication protocol with ID tag added, so that it can be used in the case of extremely large antennas (such as 1024 antennas). Next, a single SPI host controller can control all antenna units individually, or control all antenna units; the described interface scheme improves the traditional SPI control scheme and reduces the number of required interfaces to only 4 wires, Therefore, a low-cost FPGA or MCU can be used as the host controller without wasting additional interfaces; another advantage of the present invention is that the board-level antenna array wiring is simple, and the present invention reduces the number of PCB wiring layers required to two layers .

Description of the drawings

Figure 1 is a schematic block diagram of the traditional SPI control method and the improved four-wire control method. Among them, (a) is the traditional SPI control method, and (b) is the improved four-wire control method;

Figure 2 is a schematic diagram of the wiring of an antenna array based on a double-layer PCB;

Figure 3 is the internal control logic architecture of the RF front-end chip;

Figure 4 is the SPI chip write timing;

Figure 5 is the read timing of the SPI chip.

Detailed ways

The technical solution of the present invention will be further described below in conjunction with the accompanying drawings and specific embodiments:

First introduce the digital control scheme of the overall system.

As shown in Figure 1(b), this solution can reduce the number of digital control signal lines to four, that is, SCLK, MOSI, MISO, and SS in the common SPI protocol. Among them, SCLK is the system clock, MOSI is the output of the master and the input of the slave, MISO is the input of the master and the output of the slave, and SS is the chip select and synchronization signal. This solution is suitable for the specific system architecture and wiring method shown in Figure 2. Because there are only four digital signal lines, the SPI host controller can choose a small-capacity FPGA or a low-cost MCU.

Taking Figure 2 as an example, the double-layer PCB wiring method is an achievable wiring method, in which the RF front-end and antenna array are arranged on the front of the PCB; SCLK, MOSI, MISO and SS are divided into MOSI and SS, MISO and SCLK. Group, each group goes on the front or back of the PCB respectively (ie MOSI and SS go to the front of the PCB and MISO and SCLK go to the back of the PCB, or MOSI and SS go to the back of the PCB and MISO and SCLK go to the front of the PCB). VDD is the power supply. By laying copper on the front of the PCB and connecting the divided areas on the back to ensure that the front of the PCB is VDD; the ground VSS uses the same method to spread copper on the back of the PCB and connect it on the front. Compared with the traditional solution that can only be realized by using multi-pin FPGA and multilayer PCB, the cost and design complexity are significantly reduced.

The following describes the structure of the digital logic module inside the corresponding phased array chip, taking an SPI communication protocol with a frame length of 24 bits as an example.

First, as shown in Figure 1 (b), each RF front-end chip in the antenna array has a different digital ID tag, numbered from 1 to N ² . The digital ID tag here can be implemented using off-chip signal input or on-chip fuse (Efuse). Take a 32×32 antenna array as an example, assuming that the transmitted and received amplitude and phase signals are both 6 bits, and the frame length specified by the SPI communication protocol is 24 bits.

The architecture of the digital logic module in the phased array chip is shown in Figure 3. It includes a core control logic module based on Moore's finite state machine, a reset control module, an error mechanism module, a general register, a phased array amplitude and Phase register and a SPI slave. In addition to the 3.3V and 1.1V power ports and ground ports, the digital logic module also has 7 inputs and outputs.

The function of each sub-module in the digital logic module is described as follows:

The SPI slave transmits the transmission frame of the SPI master to the core control logic module, and the transmission frame includes ID, amplitude and phase code;

The core control logic assigns the amplitude and phase codes to the internal buffer and controls the reading and writing of general registers. If and only if the ID in the sending frame is the same as the digital ID of the RF front-end corresponding to the digital logic module, the read and write functions of the general-purpose register will work normally;

The amplitude and phase codes are stored in the phased array amplitude and phase registers and directly connected to the RF front-end;

General registers control the state of the entire phased array chip;

The error mechanism module, when it is detected that the error mechanism module is turned on to send the frame, the error mechanism is turned on. When a frame error is found through frame length check and CRC detection, this module will automatically close the communication between the internal registers of the digital logic module and the SPI interface (that is, the error content will not be sent to the RF front-end), and record the error in the general register. When the SPI master makes an error inquiry, it will give feedback through the MISO port. Since the multiple output interfaces are directly connected on MISO, MISO is a three-state bus. At any time, only one MISO of the SPI slave is in the output state, and the MISO of the remaining SPI slaves are in the high-impedance state. After the SPI host sends the reset frame, the entire phased array chip will be reset synchronously in sequence under the control of the reset module.

The following describes the specific communication protocol.

The improved SPI four-wire interface protocol in the present invention mainly relies on the four interfaces of SCLK, MOSI, MISO and SS, which can complete the read and write operations of wave control signals. Among them, SCLK is the system synchronization clock of the SPI master and slave, and SS is the low-level active chip select synchronization signal. MOSI is the interface for host output (chip input), and MISO is the interface for chip output (host input).

Both writing and output are based on frames, and the length of each frame is fixed at 24 bits.

SDI samples MOSI on the rising edge of SCLK and outputs MISO on the rising edge of SCLK. Therefore, the SPI master needs to output MOSI on the falling edge of SCLK and sample MISO on the falling edge of SCLK. When SS changes from high to low, the phased array chip is selected, and the serial input signal of MOSI starts to be stored in the 24-bit buffer in the phased array chip until the 24bit signals are all stored, and when SS changes from low to high, it starts to proceed. Data processing, read and write corresponding registers, and prepare MISO output. When SS is high, the rising edge of SCLK resets the state machine of the phased array, and the SPI is in the standby state. When the MODE register inside the phased array chip is 1, the SPI works in the ID state, which can be read and written, and the ID must be correct. Once the first 4bit ID is incorrect, the SPI will immediately enter the standby state. When MODE is 0, it is in no ID state, which can only be written but not readable. At this time, all N ² chips can be controlled at the same time.

The write sequence is shown in Figure 4. After the falling edge of SS, MOSI writes a 24bit write command frame. At the rising edge of SS, the function of this frame is realized. During continuous writing, MISO assumes a high-impedance state.

The read sequence only exists in the ID mode, that is, when the MODE register is written to 1. As shown in Figure 5. After the falling edge of SS, MOSI writes the 24bit read command frame. At the rising edge of SS, the output content is put into the MISO buffer in advance and output in the next frame. At the same time, the next frame will also take effect. If you don’t need the next frame to take effect, you can write an invalid frame with the correct ID number. At this time, the MISO state when reading the command frame is not concerned, because the current MISO state is only related to the previous frame.

In the actual application scenario, the frames are sent in the following order. First send the ID frame, the ID frame has its own frame header, followed by the ID number to be written next, assuming ID=k. After that, all frames sent by the SPI host only communicate with the phased array chip with a digital ID of k. After the communication with the phased array chip with ID=k is completed, a new ID frame can be sent to communicate with the chip with the next ID.

The invention adopts an improved SPI four-wire interface scheme, integrates a digital logic module with an SPI slave interface in the radio frequency front end, and adopts a communication protocol with ID tag added, so that it can be used in the case of extremely large antennas (such as 1024 antennas). Next, a single SPI host controller can control all antenna units individually, or control all antenna units. The described interface scheme improves the traditional SPI control scheme and reduces the number of required interfaces to only 4 wires, so that a low-cost FPGA or MCU can be used as a host controller without wasting additional interfaces.

The above are only specific implementations of the present invention, but the protection scope of the present invention is not limited to this. Anyone familiar with the technology can understand conceivable changes or substitutions within the technical scope disclosed in the present invention. All should be covered within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

A large-scale antenna array digital wave control signal interface scheme, which is characterized in that each phased array chip in the antenna array integrates a digital logic module with an SPI slave interface, and uses a communication protocol that adds ID tags. A single SPI host controller can individually control all antenna units in the antenna array or control all antenna units. Among them, each RF front end in the antenna array has a different digital ID tag;

The digital logic module includes a core control logic module based on the Moore finite state machine, a reset control module, an error mechanism module, a general register, a phased array amplitude and phase register, and an SPI slave; the SPI slave will be the SPI master The transmission frame of the transmission frame is transmitted to the core control logic module, and the transmission frame includes the digital ID and the amplitude and phase code; the core control logic module controls the reading and writing of the general register, if and only if the ID in the transmission frame corresponds to the digital logic module When the digital ID of the RF front-end is the same, the core control logic module assigns the amplitude and phase codes to the phased array amplitude and phase control registers through the general-purpose register, and the phased array amplitude and phase control registers are directly connected to the RF front end; error mechanism module When the sending frame is turned on, when a frame error is found through the frame length check and CRC detection, the communication between the general register and the phased array amplitude and phase register and the SPI slave interface is automatically closed, and the frame error is recorded in the general register. When the SPI master makes an error inquiry, it will give feedback through the MISO port of the SPI slave. After the SPI master sends a reset frame, it will reset in sequence under the control of the reset control module.
The digital wave control signal interface scheme of a large-scale antenna array according to claim 1, characterized in that the SCLK, MOSI, MISO, and SS four interfaces of the SPI slave correspond to the SCLK, MOSI, MISO, and MOSI of the SPI master. Four interfaces with SS, among which, SCLK is the system synchronization clock of the SPI master and slave, SS is the low-level active chip select synchronization signal, MOSI is the interface of the master output/slave input, and MISO is the slave output/master The input interface.
The digital wave control signal interface scheme of a large-scale antenna array according to claim 1, wherein the MISO of only one SPI slave is in the output state at any time, and the MISO of the remaining SPI slaves are in the high impedance state.
The digital wave control signal interface scheme of a large-scale antenna array according to claim 1, characterized in that the communication protocol added to the ID tag is: the writing and output of the SPI interface are in units of frames; the SPI host falls on the SCLK Output MOSI along the edge, and sample MISO on the falling edge of SCLK; when SS changes from high to low, the phased array chip is selected, and the serial input signal of MOSI starts to be stored in the buffer in the phased array chip until the serial input signals are all After storing, when SS changes from low to high, data processing starts, the corresponding registers are read and written, and the output of MISO is ready; when SS is high, the rising edge of SCLK resets the state machine of the phased array chip, and SPI is in the standby state ; When the MODE register inside the phased array chip is 1, the SPI is working in the state of identifying the digital ID, which can be read and written, and the digital ID must be correct to read and write. Once the digital ID is incorrect, the SPI slave immediately enters the standby state; the MODE register is When it is 0, it is in no ID state, which can only be written but not readable.