CN111104353B - Multifunctional aviation bus interface card based on FPGA - Google Patents
Multifunctional aviation bus interface card based on FPGA Download PDFInfo
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- CN111104353B CN111104353B CN201911302391.1A CN201911302391A CN111104353B CN 111104353 B CN111104353 B CN 111104353B CN 201911302391 A CN201911302391 A CN 201911302391A CN 111104353 B CN111104353 B CN 111104353B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
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- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention discloses a multifunctional aviation bus interface card based on an FPGA (field programmable gate array), which mainly solves the problems that the existing aviation bus interface is inflexible to use, low in integration level and complicated in communication among different bus devices. It includes: the device comprises an FPGA circuit, a PLX9054 bridge circuit, an interface circuit, a power supply circuit and a VGA backboard. The FPGA circuit is used as a core, data received by the interface circuit is processed, and the data is sent to the CPCI bus by the bridge circuit to complete data receiving; the FPGA circuit finishes data processing by receiving control instructions and data from the CPCI bus and sends the data to an external bus interface through an interface circuit to finish data sending; the VGA backboard selects one path from the input 3 paths of XGA signals according to the control instruction, outputs the selected path, converts the selected path into a VGA signal and sends the VGA signal to the video acquisition equipment. The invention has strong universality, high integration level and convenient operation, and can be used for avionic equipment which needs mutual communication among different buses.
Description
Technical Field
The invention belongs to the technical field of communication, and particularly relates to an aviation bus interface card which can be used in an avionics system.
Background
With the development of digital technology, more and more avionic devices adopt digital technology, avionic systems with relatively independent functions gradually go to synthesis, data communication among subsystems becomes more important, and an avionic bus is promoted to come into play. At present, the types of buses are various, and mainly ARINC429 and ARINC453 exist in avionics systems. Since avionics subsystems are usually only simple single bus protocols, it is necessary to be able to communicate between different bus devices.
At present, the ARINC429 and ARINC453 interface designs are realized by adopting imported special devices, such as DEI-1016 of Device Engineering company, HS-3282 of INTERSIL company and BU-61580 of DDC company. Wherein DEI-1016 from DeviCe Engineering needs to be used with the level shifter BD429, comprising a one-pass transmitter, two independent receive channels. HS-3282 from INTERSIL corporation is a CMOS 429 interface with two-way reception and one-way transmission. The BU-61580 from DDC corporation is a multi-protocol interface chip that requires an 8-bit/16-bit/32-bit single chip, ARM, DSP, or CPU as the BUs interface main processor, and has two low-power dual-port transceivers. The special devices are imported devices, are high in price, are limited in path number and not flexible enough, and need to be matched by a plurality of groups of chips when multi-path multi-interface data communication is completed, so that the hardware occupies a large volume, different bus devices are complicated to communicate with each other, and the integration level is not high.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a multifunctional aviation bus interface card based on an FPGA (field programmable gate array) so as to effectively reduce the system volume, improve the integration level and increase the flexibility of the configuration of a transceiving channel.
The technical idea of the invention is as follows: the method comprises the following steps of (1) carrying out caching, data decoding, serial/parallel conversion, data framing and other processing on received multi-channel ARINC429 and ARINC453 data by adopting the size of a standard 6U board card and taking an FPGA as core control, and transmitting the data to a single board computer through a CPCI bus to complete data receiving; the CPCI bus receives instruction control from the single board computer, data caching and data framing are completed in the FPGA, and data are transmitted to corresponding external bus interfaces after level conversion is carried out on ARINC429 and ARINC45 at a required data transmission rate, so that data transmission is completed. By adopting the FPGA as a core controlled full digital circuit, the bus equipment is flexibly set and conveniently controlled by data transmission so as to meet the mutual communication among different bus equipment. The implementation scheme is as follows:
the utility model provides a with multi-functional aviation bus interface card based on FPGA, includes interface circuit, power supply circuit which characterized in that:
the input end of the interface circuit is connected with an FPGA circuit and is used for data caching, data sending parallel/serial conversion, data receiving serial/parallel conversion and data framing control; an output IO pin of the FPGA circuit is connected with a PLX9054 bridging circuit and a VGA backboard in parallel, and the PLX9054 bridging circuit is used for receiving a data transmission request of a CPCI bus or the FPGA circuit and sending cache data to a corresponding data bus; the VGA back plate is used for receiving a video switching control signal of the FPGA circuit and selecting one XGA signal from three XGA signals input by external equipment through the connector to be converted into a VGA signal;
the FPGA circuit comprises:
the CPCI interface read-write control module is used for completing the read-write operation of 32bits of data on the CPCI bus, and carrying out address decoding and time sequence control on the related time sequence signals of the CPCI bus;
the data transmission caching module is used for storing the 32bits data formed by framing the CPCI interface read-write control module data;
the data transmission control module is used for reading a plurality of 32bits data from the data transmission cache module, performing parallel-serial conversion on the read data according to a corresponding data format, and outputting the data according to an agreed interface bus rate;
the data receiving control module is used for receiving, frame header detecting and serial-parallel converting serial data input from the outside, and framing the converted data into 32bits of data according to a set format;
and the data receiving and caching module is used for storing the 32bits data formed by framing of the data receiving control module.
Compared with the prior art, the invention has the following advantages:
1. the invention adopts the size of a standard 6U board card, can finish data transmission with a PC (personal computer) or a single board computer through a CPCI (compact peripheral component interconnect) bus, and has strong universality and convenient operation;
2. the invention is designed based on FPGA as core control, integrates a plurality of paths of ARINC429 and ARINC453 aviation bus interfaces and a plurality of paths of RS422 and RS232 universal communication serial interfaces, has high integration level and strong flexibility, and can complete the mutual communication among different bus devices by receiving CPCI bus control instructions.
Drawings
FIG. 1 is a functional block diagram of the present invention;
FIG. 2 is a block diagram of the FPGA circuit of the present invention.
FIG. 3 is a circuit block diagram of a VGA backplane of the present invention
Detailed Description
Embodiments of the present invention are described in further detail below with reference to the accompanying drawings.
Referring to fig. 1, the FPGA-based multifunctional bus interface card of the present embodiment includes an FPGA circuit 1, a PLX9054 bridge circuit 2, an interface circuit 3, a power circuit 4, and a VGA backplane 5. The interface card receives control instructions and data transmitted by a PC/single board computer/other equipment through a CPCI bus, can complete the receiving and sending of external ARINC453, ARINC429, RS422 and RS232 interface data, can complete the interactive communication among the interface data, and simultaneously has the function of converting three switchable XGA signals into VGA video signals. Wherein:
the FPGA circuit 1, which is used as a control core of the interface card, performs data transmission with the CPCI bus through the PLX9054 bridge circuit 2, performs functions of identification, caching, serial-to-parallel conversion, framing and the like on external interface data according to instruction control on the received CPCI bus, and performs communication with an external device interface through the interface circuit 3, and the structure of the FPGA circuit is shown in fig. 2.
The PLX9054 bridge circuit 2 adopts a PCI protocol processing chip PLX9054 or PLX9052 chip to work in a C mode, and adopts an EEPROM as a configuration chip thereof to build a hardware bridge for data transmission between the CPCI bus and the FPGA circuit 1.
The interface circuit 3 adopts HI2579, HI8591, HI8592, MAX3045, MAX3096 and MAX3160 chips to form a plurality of transceiving interfaces, and can convert an input signal level into a signal level required by an output end so as to meet the interface requirements of two paths of ARINC453, five paths of ARINC429, four paths of RS422 and four paths of RS232, and the transceiving modes, the data transmission rate and other working states of the interface circuit can be flexibly configured by the FPGA circuit 1.
The power supply circuit 4 converts the standard voltage input by the CPCI bus and outputs the converted standard voltage to the FPGA circuit 1, the PLX9054 bridge circuit 2 and the interface circuit 3, so that the power supply requirements of the FPGA circuit 1, the PLX9054 bridge circuit 2 and the interface circuit 3 are guaranteed.
The VGA backboard 5 converts one of the three groups of XGA signals input from the outside into a VGA signal through the video switching control signal sent by the FPGA circuit 1, and only 1 channel of XGA signal is output to the external video capture device, i.e. mutual exclusion occurs between 3 channels of VGA signals, and only 1 channel of XGA signal is output to the video capture device, and the output video resolution is not lower than 1024 × 768, the frame rate is not lower than 24 frames per second, and the structure is shown in fig. 3.
Referring to fig. 2, the FPGA circuit 1 adopts a v5 series FPGA to build a hardware circuit, and mainly completes serial-parallel conversion, data framing, data transmission control and interface chip working state control functions in the interface data transceiving process, and includes an interface read-write control module 11, a data transmission cache module 12, a data transmission control module 13, a data reception control module 14, and a data reception cache module 15. The data transmission control module 13 includes a data reading sub-module 131 and a data framing sub-module 132; the data receiving control module 14 includes a frame header detection sub-module 141 and a data reassembly sub-module 142. The interface read-write control module 11 receives the CPCI bus control signal and caches the CPCI bus data in the data sending cache module 12; when the complete data is stored for one time, the data sending buffer module 12 generates a data receiving state trigger signal to act on the data sending control module 13, that is, the data reading sub-module 131 in the module, so that the data reading sub-module 131 generates a reading enable signal, the data sending buffer module 12 reads the data and transmits the data to the data sending control module 13, and the data framing sub-module 132 in the module performs parallel/serial conversion on the data read by the data reading sub-module 131 according to a corresponding data format and transmits the data to the data output port. In the data receiving process, the data receiving control module 14 receives the data input in serial, and the frame header detection sub-module 141 in the module performs serial/parallel conversion on each input frame signal, detects a certain number of bits of the identification data according to the agreed data format, determines the correctness of the transmitted data, and sends the data to the data reassembly sub-module 142 in the module; the data restructuring submodule 142 restructures the data of the frame header detecting submodule 141 into data of a data length required by the data receiving cache module 15 by bytes, generates a write enable signal, caches the restructured data to the data receiving cache module 15, and sends the data of the data receiving cache module 15 to the CPCI bus when the read signal of the interface read-write control module 11 is valid.
Referring to fig. 3, the VGA backplane 5 includes a video switch 51 and an XGA to VGA video converter 52. The method is characterized in that MAX4885 and AD8145 chips are adopted to build a hardware circuit, three paths of video signals in XGA format input by a connector are sent to a video switch 51, the video switch 51 selects one path of XGA video signals according to the state of video switching control signals generated by an FPGA circuit 1 and sends the XGA video signals to an XGA-to-VGA video converter 52, the XGA-to-VGA video converter 52 converts the XGA video signals into VGA video signals and outputs the VGA video signals to an external VGA interface.
The working principle of this example is as follows:
the embodiment can receive control instructions and data transmitted by external equipment through the CPCI bus, can finish the receiving and sending of data of external aviation bus data interfaces ARINC453 and ARINC429 and general data interfaces RS422 and RS232, can also finish interactive communication among the interface data, and simultaneously has the function of converting three switchable XGA signals into VGA video signals. The PLX9054 bridge circuit 2 receives control instructions and data transmitted by the CPCI bus through the CPCI connector, and converts the control instructions and data to a local bus port through the CPCI connector, that is, the interface read-write control module 11, performs address decoding according to transmitted time sequence signals, generates read-write enable signals, and buffers 32bits of data on the bus to the data sending buffer module 12, when one-time complete data storage is completed, the data sending buffer module 12 generates a data receiving state trigger signal to act on the data reading submodule 131, so that the data reading submodule 131 generates read enable signals, reads out the data from the data sending buffer module 12 and transmits the data to the data reading submodule 131, the data framing submodule 132 performs parallel-serial conversion on multiple groups of 32bits of data read according to corresponding data formats and transmits the data to the interface circuit 3, and the circuit converts the input signal level into the signal level required by the external device interface, and transmits the signal level to the external device interface through the connector at the transmission rate and the data format set by the data framing submodule 132. The interface data of the external equipment can also be connected with the board card through a connector, the standard aerobus interface ARINC453, ARINC429 data or the universal data interface RS422, RS232 data are input into the interface circuit 3 of the board block, the circuit converts the input signal level and inputs the converted signal level into the frame head detection submodule 141, the module carries out serial/parallel conversion on each input frame signal, then detects a certain digit of the identification data according to the appointed data format, and sends the data to the data recombination submodule 142 after the correctness of the transmission data is determined; the module recombines the data of the frame header detection submodule 141 into 32bits data according to bytes, generates a write enable signal, buffers the recombined data into the data receiving buffer module 15, and sends the data of the data receiving buffer module 15 to the PLX9054 bridge circuit 2 in a direct transmission mode when the read signal of the interface read-write control module 11 is effective, and the circuit transfers the received data to the CPCI bus external equipment. The interactive communication between the interfaces can be completed through the internal data processing and conversion of the FPGA, and the data can also be received to the CPCI bus external equipment, and the data is transmitted out through the board card in a required data format after the data identification and conversion processing of the external equipment are completed. The principle of the output function of converting three XGA signals into VGA signals can be realized by the method that the three XGA signals input from the outside are sent to the video switch 51 through a connector, the video switch 51 selects one XGA video signal according to the state of the video switching control signal generated by the FPGA and sends the XGA video signal to the XGA-to-VGA video converter 52, and the XGA-to-VGA video converter 52 converts the input XGA video signal into the VGA video signal and outputs the VGA video signal to an external VGA interface.
The foregoing description is only an example of the present invention and should not be construed as limiting the invention, as it will be apparent to those skilled in the art that various modifications and variations in form and detail can be made without departing from the principle and structure of the invention after understanding the present disclosure and the principles, but such modifications and variations are considered to be within the scope of the appended claims.
Claims (5)
1. The utility model provides a multi-functional aviation bus interface card based on FPGA, includes interface circuit (3), power supply circuit (4), its characterized in that:
the input end of the interface circuit (3) is connected with an FPGA circuit (1) and is used for data caching, data sending parallel/serial conversion, data receiving serial/parallel conversion and data framing control; an output IO pin of the FPGA circuit (1) is connected with a PLX9054 bridging circuit (2) and a VGA backboard (5), and the PLX9054 bridging circuit (2) is used for receiving a data transmission request of the CPCI bus or the FPGA circuit (1) and sending cache data to a corresponding data bus; the VGA back plate (5) is used for receiving a video switching control signal of the FPGA circuit (1) and converting one of the three XGA signals input by external equipment through the connector into a VGA signal;
the FPGA circuit (1) comprises:
the interface read-write control module (11) is used for completing the read-write operation of 32bits data on the CPCI bus, and carrying out address decoding and time sequence control on a related time sequence signal of the CPCI bus;
the data sending and caching module (12) is used for storing 32bits data formed after framing the data of the interface read-write control module (11);
the data transmission control module (13) is used for reading a plurality of 32bits of data from the data transmission cache module (12), performing parallel-serial conversion on the read data according to a corresponding data format, and outputting the data according to an agreed interface bus rate;
the data receiving control module (14) is used for receiving, frame header detecting and serial-parallel converting serial data input from the outside, and framing the converted data into 32bits data according to a set format;
the data receiving and buffering module (15) is used for storing 32bits data formed by framing of the data receiving control module (14);
the VGA backplane (5) comprises: a video switch (51) and an XGA-to-VGA video converter (52), wherein the input end of the video switch (51) is connected with the FPGA circuit (1) and is used for receiving video switching control signals generated by the FPGA circuit and selecting one group of XGA signals from three groups of input XGA signals for output; the output end of the video selector switch (51) is connected with the XGA-to-VGA video converter (52) and used for converting a group of XGA signals selected by the video selector switch (51) into VGA signals to be output;
the data receiving control module (14) comprises: the frame header detection submodule (141) and the data reorganization submodule (142), the frame header detection submodule (141) is used for completing the serial/parallel conversion of each frame signal input from the outside, then detecting a certain number of bits of the identification data according to the agreed data format, and sending the data to the data reorganization submodule (142) after the correctness of the transmission data is determined; the data restructuring submodule (142) is used for restructuring the data passing through the frame header detection submodule (141) into the data with the data length required by the data receiving cache module (15) according to bytes, generating a write enable signal and sending the restructured data to the data receiving cache module (15).
2. An interface card according to claim 1, characterised in that said power supply circuit (4) has its output connected to, respectively supply power to, said FPGA circuit (1), said PLX9054 bridge circuit (2), said interface circuit (3) and said VGA backplane (5).
3. An interface card according to claim 1, characterised in that said data transmission control module (13) comprises: the data reading submodule (131) and the data framing submodule (132), the data reading submodule (131) is used for generating a reading enabling signal according to a one-time complete data receiving state triggering signal, and reading out data of the data sending cache module (12) to the output data framing submodule (132); the data framing submodule (132) is used for performing parallel/serial conversion on the read data of the data reading submodule (131) according to a corresponding data format and sending the read data to an output port.
4. The interface card according to claim 1, wherein the PLX9054 bridge circuit (2) employs a PCI protocol processing chip PLX9054 or PLX9052 chip, operates in C mode, and selects EEPROM as its configuration chip.
5. An interface card according to claim 1, characterised in that the interface circuit (3) is arranged to form a plurality of transceiving interfaces using HI2579, HI8591, HI8592, MAX3045, MAX3096 and MAX3160 chips to meet the interface requirements of two-way ARINC453, five-way ARINC429, four-way RS422 and four-way RS232, the operating state of which is flexibly configurable by the FPGA circuit (1).
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