CN114003543B - High-speed serial bus clock compensation method and system - Google Patents
High-speed serial bus clock compensation method and system Download PDFInfo
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- CN114003543B CN114003543B CN202111277454.XA CN202111277454A CN114003543B CN 114003543 B CN114003543 B CN 114003543B CN 202111277454 A CN202111277454 A CN 202111277454A CN 114003543 B CN114003543 B CN 114003543B
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- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
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Abstract
The invention belongs to the field of communication, and discloses a high-speed serial bus clock compensation method and a system, wherein the method comprises the following steps: acquiring the written data quantity and the read data quantity of each channel of the high-speed serial bus, and generating a compensation application of each channel according to the written data quantity and the read data quantity; acquiring current writing data and current reading data of each channel of the high-speed serial bus, and generating state signals of each channel according to the current writing data and the current reading data; generating a compensation enabling signal of each channel according to the state signal of each channel and the compensation application, and carrying out preset compensation operation on each channel according to the compensation enabling signal of each channel. The method has no phase requirement on each input clock of multiple channels, has flexible usability, can be applied to various high-speed bus protocols, solves the problem of multi-channel interconnection of various high-speed bus physical layers, controls the compensation operation of each channel through a state signal, and effectively improves the reliability and the correctness of circuit transmission.
Description
Technical Field
The invention belongs to the field of communication, and relates to a high-speed serial bus clock compensation method and a system.
Background
In high-speed inter-board communication under high bandwidth requirements, a multi-channel high-speed serial bus is generally used for data transmission. In this case, in order to avoid data errors caused by asynchronous clock communication, it is necessary to consider clock relationships through the respective high-speed serial buses.
Currently, the following two approaches are generally available for the above-mentioned cases. One is that the multiple channels of the data link all use the same reference clock, but this loses flexibility in the use of multiple channels. The other is to perform clock compensation on a single channel of the data link, however, when performing clock compensation on the single channel at present, SKIP characters are usually required to be deleted, but after the SKIP characters are deleted, multi-channel binding mismatch of the data link is often caused, and then the multi-channel binding mismatch state is frequently entered, so that the multi-channel communication efficiency is affected.
Disclosure of Invention
The present invention is directed to a method and system for compensating a clock of a high-speed serial bus, which overcomes the drawbacks of the prior art.
In order to achieve the purpose, the invention is realized by adopting the following technical scheme:
in a first aspect of the present invention, a high-speed serial bus clock compensation method includes the steps of:
acquiring the written data quantity and the read data quantity of each channel of the high-speed serial bus, and generating a compensation application of each channel according to the written data quantity and the read data quantity;
acquiring current writing data and current reading data of each channel of the high-speed serial bus, and generating state signals of each channel according to the current writing data and the current reading data;
generating a compensation enabling signal of each channel according to the state signal of each channel and the compensation application, and carrying out preset compensation operation on each channel according to the compensation enabling signal of each channel.
The high-speed serial bus clock compensation method of the invention is further improved in that:
the specific method for generating the compensation application of each channel according to the written data quantity and the read data quantity comprises the following steps: when the number of the written data of the current channel is at least a first preset number more than the number of the read data, the compensation application of the current channel is a writing compensation application; when the read data quantity of the current channel is at least a second preset quantity more than the write data quantity, the compensation application of the current channel is a read compensation application.
The specific method for generating the state signals of all channels according to the current writing data and the current reading data comprises the following steps: when the current writing data of the current channel is a compensation code, the state signal of the current channel is capable of writing compensation, and when the current writing data of the current channel is not the compensation code, the state signal of the current channel is incapable of writing compensation; when the current read data of the current channel is the compensation code, the state signal of the current channel is read compensation capable, and when the current read data of the current channel is not the compensation code, the state signal of the current channel is read compensation incapable.
The specific method for generating the compensation enabling signal of each channel according to the state signal of each channel comprises the following steps: when the state signals of all the channels are write compensation incapable, and the compensation application is write compensation application, the compensation enabling signals of all the channels are write compensation enabling signals; when the status signals of all the channels are read compensation disabled and the compensation application is a read compensation application, the compensation enabling signal of each channel is a read compensation enabling signal.
The preset compensation operation comprises a write compensation operation and a read compensation operation; the specific method for carrying out preset compensation operation on each channel according to the compensation enabling signals of each channel comprises the following steps: when the compensation enabling signal of the current channel is a write compensation enabling signal, performing write compensation operation when the next time that the written data is detected as a compensation code; when the compensation enable signal of the current channel is a read compensation enable signal, a read compensation operation is performed when the read data is detected as a compensation code next time.
The write compensation operation is specifically: writing one beat of compensation code when writing the compensation code; the read compensation operation is specifically: one more beat of compensation code is read out when the compensation code is read out.
Further comprises: and acquiring the written data of the preset bit of each channel, and when the written data of the preset bit of each channel has the alignment code, acquiring the position number of the alignment code which is written by each channel last time, and outputting the written data according to the position number of the alignment code which is written by each channel last time.
When the position number of the last written alignment code of each channel is not 0, synchronously reducing the position number of the last written alignment code of each channel to 0.
The invention relates to a high-speed serial bus clock compensation system, which comprises a plurality of single-channel compensation modules and a compensation scheduling module, wherein one end of each single-channel compensation module is used for connecting a plurality of channels of a high-speed serial bus, and the other end of each single-channel compensation module is connected with the compensation scheduling module;
the single-channel compensation modules are respectively used for acquiring the written data quantity and the read data quantity of each channel, and generating a compensation application of each channel according to the written data quantity and the read data quantity; the system is also used for respectively acquiring current writing data and current reading data of each channel and generating state signals of each channel according to the current writing data and the current reading data; the compensation control module is also used for respectively receiving the compensation enabling signals of the channels sent by the compensation scheduling module and carrying out preset compensation operation on the channels according to the compensation enabling signals of the channels;
the compensation scheduling module is used for receiving and generating compensation enabling signals of all channels according to the state signals of all channels and the compensation application and sending the compensation enabling signals to all single-channel compensation modules respectively.
Preferably, the system further comprises a multi-channel alignment module, wherein one end of the multi-channel alignment module is connected with a plurality of single-channel compensation modules; the multi-channel alignment module is used for acquiring the write-in data of each channel preset bit, acquiring the position number of the last written-in alignment code of each channel when the write-in data of each channel preset bit has the alignment code, and outputting the write-in data according to the position number of the last written-in alignment code of each channel.
Compared with the prior art, the invention has the following beneficial effects:
the invention relates to a high-speed serial bus clock compensation method, which comprises the steps of obtaining the written data quantity and the read data quantity of each channel of a high-speed serial bus, generating a compensation application of each channel according to the written data quantity and the read data quantity, generating a state signal of each channel according to the current written data and the current read data of each channel, generating a compensation enabling signal of each channel according to the state signal of each channel, and finally carrying out preset compensation operation on each channel according to the compensation enabling signal and the written or read data. The multi-channel bus has no phase requirement on each input clock of multiple channels, has very flexible usability, can be applied to various high-speed bus protocols, and can solve the problem of multi-channel interconnection of various high-speed bus physical layers. Meanwhile, the compensation operation of each channel is controlled through the state signal, so that the reliability and the correctness of circuit transmission are effectively improved.
Further, by acquiring the write-in data of the preset bit of each channel, and when the write-in data of the preset bit of each channel has the alignment code, acquiring the position number of the alignment code which is written in each channel last time, and then outputting the write-in data according to the position number of the alignment code which is written in each channel last time, the alignment process is realized based on the cache array, and the time delay of data transmission is effectively reduced.
Drawings
FIG. 1 is a flow chart of a method for high speed serial bus clock compensation according to the present invention;
FIG. 2 is a block diagram of a high speed serial bus clock compensation system of the present invention;
FIG. 3 is a schematic diagram of the clock compensation principle of the high-speed serial bus clock compensation method of the present invention;
FIG. 4 is a timing diagram of a high-speed serial bus clock compensation method according to the present invention;
FIG. 5 is a schematic diagram of a multi-channel alignment module according to the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or modules is not necessarily limited to those steps or modules that are expressly listed or inherent to such process, method, article, or apparatus.
The invention is described in further detail below with reference to the attached drawing figures:
referring to fig. 1, in an embodiment of the present invention, a high-speed serial bus clock compensation method is provided, which includes the following steps: acquiring the written data quantity and the read data quantity of each channel of the high-speed serial bus, and generating a compensation application of each channel according to the written data quantity and the read data quantity; acquiring current writing data and current reading data of each channel of the high-speed serial bus, and generating state signals of each channel according to the current writing data and the current reading data; generating a compensation enabling signal of each channel according to the state signal of each channel and the compensation application, and carrying out preset compensation operation on each channel according to the compensation enabling signal of each channel.
The specific method for generating the compensation application of each channel according to the written data quantity and the read data quantity comprises the following steps: when the number of the written data of the current channel is at least a first preset number more than the number of the read data, the compensation application of the current channel is a writing compensation application; when the read data quantity of the current channel is at least a second preset quantity more than the write data quantity, the compensation application of the current channel is a read compensation application.
The specific method for generating the state signals of the channels according to the current writing data and the current reading data comprises the following steps: when the current writing data of the current channel is a compensation code, the state signal of the current channel is capable of writing compensation, and when the current writing data of the current channel is not the compensation code, the state signal of the current channel is incapable of writing compensation; when the current read data of the current channel is the compensation code, the state signal of the current channel is read compensation capable, and when the current read data of the current channel is not the compensation code, the state signal of the current channel is read compensation incapable.
The specific method for generating the compensation enabling signal of each channel according to the state signal of each channel comprises the following steps: when the state signals of all channels are write compensation incapable and the compensation application is a write compensation application, the compensation enabling signals of all channels are write compensation enabling signals; when the status signals of all channels are read compensation disabled and the compensation application is a read compensation application, the compensation enabling signal of each channel is a read compensation enabling signal.
The preset compensation operation comprises a write compensation operation and a read compensation operation; the specific method for carrying out preset compensation operation on each channel according to the compensation enabling signals of each channel comprises the following steps: when the compensation enabling signal of the current channel is a write compensation enabling signal, performing write compensation operation when the next time that the written data is detected as a compensation code; when the compensation enable signal of the current channel is a read compensation enable signal, a read compensation operation is performed when the read data is detected as a compensation code next time.
The write compensation operation specifically includes: writing one beat of compensation code when writing the compensation code; the read compensation operation is specifically: one more beat of compensation code is read out when the compensation code is read out.
In one possible implementation, the high-speed serial bus clock compensation method further includes: and acquiring the written data of the preset bit of each channel, and when the written data of the preset bit of each channel has the alignment code, acquiring the position number of the alignment code which is written by each channel last time, and outputting the written data according to the position number of the alignment code which is written by each channel last time.
When the position number of the last written alignment code of each channel is not 0, the position number of the last written alignment code of each channel is synchronously reduced to 0.
In summary, the high-speed serial bus clock compensation method of the present invention obtains the number of write data and the number of read data of each channel of the high-speed serial bus, generates a compensation application of each channel according to the number of write data and the number of read data, then generates a status signal of each channel according to the current write data and the current read data of each channel, generates a compensation enable signal of each channel according to the status signal of each channel, and finally performs a preset compensation operation on each channel according to the compensation enable signal and the compensation application, has no phase requirement on each input clock of multiple channels, has very flexible usability, can be applied to multiple high-speed bus protocols, and can solve the multi-channel interconnection problem of multiple high-speed bus physical layers. Meanwhile, the compensation operation of each channel is controlled through the state signal, so that the reliability and the correctness of circuit transmission are effectively improved.
Further, by acquiring the write-in data of the preset bit of each channel, and when the write-in data of the preset bit of each channel has the alignment code, acquiring the position number of the alignment code which is written in each channel last time, and then outputting the write-in data according to the position number of the alignment code which is written in each channel last time, the alignment process is realized based on the cache array, and the time delay of data transmission is effectively reduced.
The following are device embodiments of the present invention that may be used to perform method embodiments of the present invention. For details of the device embodiment that are not careless, please refer to the method embodiment of the present invention.
Referring to fig. 2, in still another embodiment of the present invention, a high-speed serial bus clock compensation system is provided, which includes a plurality of single-channel compensation modules and a compensation scheduling module, wherein one end of each single-channel compensation module is used for connecting a plurality of channels of the high-speed serial bus, and the other end of each single-channel compensation module is connected with the compensation scheduling module; the single-channel compensation modules are respectively used for acquiring the written data quantity and the read data quantity of each channel, and generating a compensation application of each channel according to the written data quantity and the read data quantity; the system is also used for respectively acquiring current writing data and current reading data of each channel and generating state signals of each channel according to the current writing data and the current reading data; the compensation control module is also used for respectively receiving the compensation enabling signals of the channels sent by the compensation scheduling module and carrying out preset compensation operation on the channels according to the compensation enabling signals of the channels; the compensation scheduling module is used for receiving and generating compensation enabling signals of all channels according to the state signals of all channels and the compensation application and sending the compensation enabling signals to all single-channel compensation modules respectively.
In one possible implementation manner, the high-speed serial bus clock compensation system further comprises a multi-channel alignment module, wherein one end of the multi-channel alignment module is connected with a plurality of single-channel compensation modules; the multi-channel alignment module is used for acquiring the write-in data of each channel preset bit, acquiring the position number of the last written-in alignment code of each channel when the write-in data of each channel preset bit has the alignment code, and outputting the write-in data according to the position number of the last written-in alignment code of each channel.
All relevant contents of each step related to the foregoing embodiment of the high-speed serial bus clock compensation method may be cited to the functional description of the functional module corresponding to the high-speed serial bus clock compensation system in the embodiment of the present invention, which is not repeated herein.
The division of the modules in the embodiments of the present invention is schematically only one logic function division, and there may be another division manner in actual implementation, and in addition, each functional module in each embodiment of the present invention may be integrated in one processor, or may exist separately and physically, or two or more modules may be integrated in one module. The integrated modules may be implemented in hardware or in software functional modules.
The high-speed serial bus clock compensation method and system of the invention are described in detail below.
The high-speed serial bus clock compensation method and the system can be used as IP to be provided for various high-speed bus protocol circuits based on Serdes, such as RapidIO, spaceFirbe, PCIe and the like, and can effectively solve the problem of multi-channel interconnection of a high-speed bus phy layer (physical layer) such as RapidIO, spaceFirbe, PCIe and the like.
The IP (intellectualproperty) kernel module is a pre-designed and even verified integrated circuit, device or component with certain determined functions, and is used for assembly or integration selection by chip designers. Serdes is an acronym for English Serializer/Deserializer. It is a mainstream Time Division Multiplexing (TDM), point-to-point (P2P) serial communication technology. The multi-path low-speed parallel signals are converted into high-speed serial signals at the transmitting end, and finally the high-speed serial signals are converted into low-speed parallel signals at the receiving end through a transmission medium (an optical cable or a copper wire). The point-to-point serial communication technology fully utilizes the channel capacity of a transmission medium, reduces the number of required transmission channels and device pins, and greatly reduces the communication cost. RapidIO is a high-performance, low-pin-count, packet-switching-based interconnect architecture advocated by Motorola, mercury and other companies, and is an open interconnect technology standard designed to meet and future requirements of high-performance embedded systems. rapidIO is mainly applied to internal interconnection of an embedded system, supports chip-to-chip and board-to-board communication, and can be used as a backboard (back p channel) connection of embedded equipment. SpaceFoibe is a spacecraft on-board data link and network technology that can run on both copper and fiber optic cables. Originally aimed at very high data rate instruments like Synthetic Aperture Radar (SAR) and multispectral imaging instruments, spacefibe enabled a wider range of spacecraft on-board communication applications because of its built-in QoS (quality of service) and FDIR (fault detection, isolation and recovery) capabilities and its backward compatibility with SpaceWire technology. The spacefibore runs at 2.5Gbits/s or higher, providing 12 times the throughput of a SpaceWire link with current technology meeting flight requirements, and allowing data from multiple SpaceWire devices to be concentrated on a single spacefiber link. This significantly reduces cable bundle quality and simplifies redundancy strategies. PCI-Express (peripheral component interconnect express) is a high-speed serial computer expansion bus standard originally named "3GIO" and was proposed by Intel in 2001 to replace the old PCI, PCI-X and AGP bus standards. PCIe belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission, where connected devices allocate exclusive channel bandwidth, do not share bus bandwidth, and mainly support functions such as active power management, error reporting, end-to-end reliability transmission, hot plug, and quality of service (QOS). PCIe is not named "PCI-Express", abbreviated as "PCI-e" until it is issued by PCI-SIG (PCI special interest group) authentication.
In this embodiment, the high-speed serial bus clock compensation system includes 2 modules, which are respectively a clock compensation module and a multi-channel alignment module, wherein the clock compensation module is composed of a plurality of single-channel compensation modules and a compensation scheduling module. The system comprises a plurality of single-channel compensation modules, a compensation scheduling module and a multi-channel alignment module in the whole system structure. The clock compensation module completes the clock compensation function of each channel and consists of a single-channel compensation module and a compensation scheduling module.
The single channel compensation module is implemented based on asynchronous fifo (First Input First Output, first-in-first-out queue), which is a traditional sequential execution method, where an incoming instruction completes and retires first, and then a second instruction is executed. For asynchronous fifo, data is written into fifo by a control signal of one clock domain, and data is read out of fifo by a control signal of another clock domain, that is, the changing action of the read-write pointer is generated by different clocks, so that there is no phase requirement for each input clock.
The single channel compensation module is internally provided with a memory or a register for storage, which can be configured according to specific use conditions, and default is 16, namely 16 data can be stored, one write pointer, one read pointer, one group (2 pointers for writing and reading respectively) of the single channel compensation module is used for asynchronously converting the pointers into Gray codes/binary conversion logic modules, and one group (2 pointers for writing and reading clock domain pointers) of the single channel compensation module is used for comparing and controlling the logic modules. Wherein the write pointer is used to record how many data are written in the write clock domain and the read pointer is used to record how many data are read out in the read clock domain. Because the read-write clock domains are different, the read pointer is required to be synchronized to the write clock domain through the Gray code/binary conversion logic module and is used for comparing with the write pointer to judge whether the data is full; similarly, the write pointer also needs to be synchronized to the read clock domain for comparison with the read pointer to determine whether the data is empty.
The comparison control logic module has 3 functions: 1. the monitoring read-write pointer determines whether the current state requires clock compensation. In the writing clock domain, when the written data is greater than or equal to the read data value, outputting a writing compensation application; similarly, in the read clock domain, when the number of written data is less than or equal to m, a read compensation application is output. Wherein, the specific numerical parameters of n and m can be matched, and the user can set according to the actual requirements. 2. The states of the written data and the read data are detected to determine whether clock compensation is possible at the present time, and a state signal is output. The data passing through the module consists of general data and a compensation code sequence, which is a fixed character prescribed according to a specific high-speed bus protocol. The comparison control logic module monitors the data to be written and read in real time, and if the data is a compensation code, the data can be immediately compensated, and the state signal is write compensation enabled or read compensation enabled. 3. And receiving a compensation enabling signal and executing a compensation operation. When the compensation enable signal is received, the compensation operation is performed at the next time when the compensation code is detected. Performing write compensation operation, namely writing one beat of compensation code when writing the compensation code sequence, and reading data normally, so that the number difference of write and read pointers can be reduced; similarly, when the read compensation is performed, one more beat of the compensation code is output when the compensation code sequence is read out, so that the number difference between the write pointer and the read pointer can be enlarged.
The number of the single-channel compensation modules is the same as the number of the channels, and the parameters of the depth of the storage buffer, the compensation code sequence judgment and the n and m values compared with the difference value of the read-write pointers are matched, so that the universality of the single-channel compensation module can be expanded, and the single-channel compensation module can be used in various high-speed bus protocols.
The compensation scheduling module is mainly responsible for coordinating the compensation execution time of each single-channel compensation module, increasing the reliability of a circuit and ensuring that multichannel transmission errors are not caused by compensation behaviors.
Referring to fig. 3, each single channel compensation module monitors the internal state in real time, mainly detects whether a compensation operation is currently required or not, and whether the currently output data is general data or a compensation sequence. And when the compensation operation is needed, a compensation request is initiated to the compensation scheduling module. The compensation scheduling module monitors whether each single-channel compensation module is in a state capable of being compensated immediately when receiving the compensation request, namely, write compensation can be performed, write compensation can not be performed, read compensation can not be performed or read compensation can be performed. Specifically, the compensation scheduling module receives status signals output by each single-channel compensation module, and the status signals represent whether the single-channel compensation module is currently in a state of receiving compensation codes, i.e. whether compensation operation can be immediately executed. When they are not in a state where they can be compensated immediately, that is, when both write compensation and both read compensation are not performed, a compensation enable signal may be issued to them to perform timing compensation. In particular, since the input clocks of the respective channels may be different, there are times when some single channel compensation modules may perform the compensation operation, while other single channel compensation modules may not. At this time, errors in data alignment may be positively generated if the compensation operation is performed. In order to avoid this, the compensation scheduling module initiates the clock compensation command at the time when each single-channel compensation module cannot execute compensation, and each single-channel compensation module performs the clock compensation operation when the next compensation time arrives, as shown in fig. 4, the compensation time refers to a state that each single-channel compensation module is not in a state that the compensation operation can be immediately executed.
Meanwhile, because the input clocks of the channels and the receiving clocks are asynchronous, unavoidable data offset is generated between the channels. The multichannel alignment module mainly comprises a Ram or a register array, and aligns and outputs data according to an input alignment code (A code). Wherein the alignment code is similar to the compensation sequence and is also a fixed character specified by the high-speed bus protocol, and is specially used when channels are synchronized. Ram or a register array will buffer the data of each channel, and the output data of each channel is output from the selected location in the buffer. Each channel has a counter for calculating the position of the latest incoming a-code. When the A codes exist in the caches of all the channels, the counter values of all the channels are stored, and all the channels select corresponding cache positions according to the values to output data. Referring to fig. 5, channel 0 has a 4 code position and channel 1 has a 5 code position, and if channel 0 is to be aligned with channel 1, the counters of the two channels are stored as 4 and 5, respectively, and the output positions are 4 and 5, i.e. they output the a code at the same time in this beat and output D5 at the same time in the next beat.
Meanwhile, in order to reduce the transmission delay, when the counter value of each channel is not 0, all the counter values are reduced to one of them is 0. For example, in FIG. 5, when channel 0 and channel 1 need to be aligned, the counters are 4 and 5, respectively, which are not 0, and the counter is decremented by 1. At this point, the counters of channel 0 and channel 1 are 3 and 4, respectively, which are still not 0, continue to decrement by 1, and so on. Until the counters for channel 0 and channel 1 are 0 and 1, respectively. The purpose of this is to reduce the link delay, since the counter is the register that selects the number of beats of data to output in the register array, the smaller the counter value, the smaller the number of beats of data to output to register in the register array, the shorter the link delay.
The length of the buffer queue can be matched according to a specific protocol and the actual system condition, and the alignment code can be matched according to the specific protocol, so that the buffer queue is compatible with various bus protocols such as rapidIO, PCIe and the like.
In a further embodiment of the present invention, the high-speed serial bus clock compensation system is applied to a 16-port RapidIO switching circuit, and the interface can be configured to be in two working states of X1 or X4, and the current working states pass through front-end verification, FPGA prototype verification, and rear-end layout netlist simulation, and enter a slice stage. The circuit can correctly and stably communicate data with other external rapidIO interfaces. The parameters according to the actual conditions are configured as follows: the compensation sequence is KRR, the alignment code is A, the compensation fifo depth is 12, the non-compensation range is 5-7, the register array is 8-level, and four single-channel compensation modules, one compensation scheduling module and one multi-channel alignment module are adopted. In the alignment part, the used Serdes outputs 16bit data based on 8b/10b, so that in each single-channel compensation module, whether the character to be detected is in a state of being immediately compensated is discriminated and detected by two beats of character detection of KR and RR and three beats of data detection of xK, RR and Rx (x represents any character). They must meet the requirement that in both character identifications, the compensation scheduling module will send out compensation operation enabling to compensate when not in the state of being compensated immediately. And when the device works in an X1 mode, the connection is stable, and no data is lost. The clock compensation and data alignment functions of 4 channels are realized when the device works in an X4 mode. The alignment processing adopts a cache array, and compared with the alignment function completed by fifo, the time delay of data transmission is reduced. The IP module based on the invention has simple interface, is convenient to integrate, and reduces the complexity of design.
The above is only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited by this, and any modification made on the basis of the technical scheme according to the technical idea of the present invention falls within the protection scope of the claims of the present invention.
Claims (5)
1. A method for high-speed serial bus clock compensation, comprising the steps of:
acquiring the written data quantity and the read data quantity of each channel of the high-speed serial bus, and generating a compensation application of each channel according to the written data quantity and the read data quantity;
acquiring current writing data and current reading data of each channel of the high-speed serial bus, and generating state signals of each channel according to the current writing data and the current reading data;
generating a compensation enabling signal of each channel according to the state signal of each channel and the compensation application, and carrying out preset compensation operation on each channel according to the compensation enabling signal of each channel;
the specific method for generating the compensation application of each channel according to the written data quantity and the read data quantity comprises the following steps:
when the number of the written data of the current channel is at least a first preset number more than the number of the read data, the compensation application of the current channel is a writing compensation application; when the number of read data of the current channel is at least a second preset number more than the number of write data, the compensation application of the current channel is a read compensation application;
the specific method for generating the state signals of all channels according to the current writing data and the current reading data comprises the following steps:
when the current writing data of the current channel is a compensation code, the state signal of the current channel is capable of writing compensation, and when the current writing data of the current channel is not the compensation code, the state signal of the current channel is incapable of writing compensation; when the current read-out data of the current channel is a compensation code, the state signal of the current channel is capable of reading compensation, and when the current read-out data of the current channel is not the compensation code, the state signal of the current channel is incapable of reading compensation;
the specific method for generating the compensation enabling signal of each channel according to the state signal of each channel comprises the following steps:
when the state signals of all the channels are write compensation incapable, and the compensation application is write compensation application, the compensation enabling signals of all the channels are write compensation enabling signals; when the state signals of all the channels are read compensation incapable, and the compensation application is a read compensation application, the compensation enabling signals of all the channels are read compensation enabling signals;
the preset compensation operation comprises a write compensation operation and a read compensation operation;
the specific method for carrying out preset compensation operation on each channel according to the compensation enabling signals of each channel comprises the following steps: when the compensation enabling signal of the current channel is a write compensation enabling signal, performing write compensation operation when the next time that the written data is detected as a compensation code; when the compensation enabling signal of the current channel is a read compensation enabling signal, performing read compensation operation when the next time that the read data is detected as a compensation code;
the write compensation operation is specifically: writing one beat of compensation code when writing the compensation code; the read compensation operation is specifically: one more beat of compensation code is read out when the compensation code is read out.
2. The high-speed serial bus clock compensation method of claim 1, further comprising: and acquiring the written data of the preset bit of each channel, and when the written data of the preset bit of each channel has the alignment code, acquiring the position number of the alignment code which is written by each channel last time, and outputting the written data according to the position number of the alignment code which is written by each channel last time.
3. The method of claim 2, wherein when the position numbers of the last written alignment codes of the channels are not 0, the position numbers of the last written alignment codes of the channels are synchronously reduced to 0.
4. The high-speed serial bus clock compensation system is characterized by comprising a plurality of single-channel compensation modules and a compensation scheduling module, wherein one ends of the single-channel compensation modules are used for connecting a plurality of channels of a high-speed serial bus, and the other ends of the single-channel compensation modules are connected with the compensation scheduling module;
the single-channel compensation modules are respectively used for acquiring the written data quantity and the read data quantity of each channel, and generating a compensation application of each channel according to the written data quantity and the read data quantity; the system is also used for respectively acquiring current writing data and current reading data of each channel and generating state signals of each channel according to the current writing data and the current reading data; the compensation control module is also used for respectively receiving the compensation enabling signals of the channels sent by the compensation scheduling module and carrying out preset compensation operation on the channels according to the compensation enabling signals of the channels;
the compensation scheduling module is used for receiving and generating compensation enabling signals of all channels according to the state signals of all channels and the compensation application and respectively sending the compensation enabling signals to all single-channel compensation modules;
the specific method for generating the compensation application of each channel according to the written data quantity and the read data quantity comprises the following steps:
when the number of the written data of the current channel is at least a first preset number more than the number of the read data, the compensation application of the current channel is a writing compensation application; when the number of read data of the current channel is at least a second preset number more than the number of write data, the compensation application of the current channel is a read compensation application;
the specific method for generating the state signals of all channels according to the current writing data and the current reading data comprises the following steps:
when the current writing data of the current channel is a compensation code, the state signal of the current channel is capable of writing compensation, and when the current writing data of the current channel is not the compensation code, the state signal of the current channel is incapable of writing compensation; when the current read-out data of the current channel is a compensation code, the state signal of the current channel is capable of reading compensation, and when the current read-out data of the current channel is not the compensation code, the state signal of the current channel is incapable of reading compensation;
the specific method for generating the compensation enabling signal of each channel according to the state signal of each channel comprises the following steps:
when the state signals of all the channels are write compensation incapable, and the compensation application is write compensation application, the compensation enabling signals of all the channels are write compensation enabling signals; when the state signals of all the channels are read compensation incapable, and the compensation application is a read compensation application, the compensation enabling signals of all the channels are read compensation enabling signals;
the preset compensation operation comprises a write compensation operation and a read compensation operation;
the specific method for carrying out preset compensation operation on each channel according to the compensation enabling signals of each channel comprises the following steps: when the compensation enabling signal of the current channel is a write compensation enabling signal, performing write compensation operation when the next time that the written data is detected as a compensation code; when the compensation enabling signal of the current channel is a read compensation enabling signal, performing read compensation operation when the next time that the read data is detected as a compensation code;
the write compensation operation is specifically: writing one beat of compensation code when writing the compensation code; the read compensation operation is specifically: one more beat of compensation code is read out when the compensation code is read out.
5. The high-speed serial bus clock compensation system of claim 4, further comprising a multi-channel alignment module, wherein one end of the multi-channel alignment module is connected to a plurality of single-channel compensation modules;
the multi-channel alignment module is used for acquiring the write-in data of each channel preset bit, acquiring the position number of the last written-in alignment code of each channel when the write-in data of each channel preset bit has the alignment code, and outputting the write-in data according to the position number of the last written-in alignment code of each channel.
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