CN114003543A - High-speed serial bus clock compensation method and system - Google Patents
High-speed serial bus clock compensation method and system Download PDFInfo
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- CN114003543A CN114003543A CN202111277454.XA CN202111277454A CN114003543A CN 114003543 A CN114003543 A CN 114003543A CN 202111277454 A CN202111277454 A CN 202111277454A CN 114003543 A CN114003543 A CN 114003543A
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- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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Abstract
The invention belongs to the field of communication, and discloses a high-speed serial bus clock compensation method and a system, which comprise the following steps: acquiring the written data quantity and the read data quantity of each channel of the high-speed serial bus, and generating a compensation application of each channel according to the written data quantity and the read data quantity; acquiring current write-in data and current read-out data of each channel of the high-speed serial bus, and generating a state signal of each channel according to the current write-in data and the current read-out data; and generating a compensation enabling signal of each channel according to the state signal and the compensation application of each channel, and performing preset compensation operation on each channel according to the compensation enabling signal of each channel. The method has no phase requirement on each input clock of multiple channels, has flexible usability, can be applied to multiple high-speed bus protocols, solves the problem of multi-channel interconnection of multiple high-speed bus physical layers, controls the compensation operation of each channel through a state signal, and effectively improves the reliability and the correctness of circuit transmission.
Description
Technical Field
The invention belongs to the field of communication, and relates to a high-speed serial bus clock compensation method and system.
Background
When high-speed communication is performed between boards under high bandwidth requirements, a multi-channel high-speed serial bus is generally adopted for data transmission. In this case, in order to avoid data errors caused by asynchronous clock communication, it is necessary to consider the clock relationship through each high-speed serial bus.
At present, the following two approaches are generally available for the above situation. One is that multiple lanes of the data link all use the same reference clock, but this loses flexibility in the use of multiple lanes. The other is to perform clock compensation on a single channel of the data link, but at present, when performing clock compensation on a single channel, SKIP characters are usually required to be deleted and added, but deletion and addition of SKIP characters often causes multi-channel binding mismatch of the data link, and then frequently enters a multi-channel binding mismatch state to affect multi-channel communication efficiency.
Disclosure of Invention
The present invention is directed to overcoming the above-mentioned shortcomings of the prior art and providing a method and system for high-speed serial bus clock compensation.
In order to achieve the purpose, the invention adopts the following technical scheme to realize the purpose:
in a first aspect of the present invention, a method for compensating a clock of a high-speed serial bus includes the following steps:
acquiring the written data quantity and the read data quantity of each channel of the high-speed serial bus, and generating a compensation application of each channel according to the written data quantity and the read data quantity;
acquiring current write-in data and current read-out data of each channel of the high-speed serial bus, and generating a state signal of each channel according to the current write-in data and the current read-out data;
and generating a compensation enabling signal of each channel according to the state signal and the compensation application of each channel, and performing preset compensation operation on each channel according to the compensation enabling signal of each channel.
The high-speed serial bus clock compensation method of the invention is further improved in that:
the specific method for generating the compensation application of each channel according to the number of the written data and the number of the read data comprises the following steps: when the written data quantity of the current channel is more than the read data quantity by at least a first preset quantity, the compensation application of the current channel is a write compensation application; and when the read data quantity of the current channel is more than the write data quantity by at least a second preset quantity, the compensation application of the current channel is a read compensation application.
The specific method for generating the state signal of each channel according to the current write data and the current read data is as follows: when the current written data of the current channel is the compensation code, the state signal of the current channel is that the write compensation can be carried out, and when the current written data of the current channel is not the compensation code, the state signal of the current channel is that the write compensation can not be carried out; when the current read data of the current channel is the compensation code, the state signal of the current channel is that the read compensation can be performed, and when the current read data of the current channel is not the compensation code, the state signal of the current channel is that the read compensation cannot be performed.
The specific method for generating the compensation enable signal of each channel according to the state signal of each channel comprises the following steps: when the state signals of all the channels are write compensation disabled and the compensation application is a write compensation application, the compensation enabling signal of each channel is a write compensation enabling signal; when the state signals of all the channels are read compensation disabled and the compensation application is a read compensation application, the compensation enable signal of each channel is a read compensation enable signal.
The preset compensation operation comprises a write compensation operation and a read compensation operation; the specific method for performing the preset compensation operation on each channel according to the compensation enabling signal of each channel comprises the following steps: when the compensation enabling signal of the current channel is a write compensation enabling signal, performing write compensation operation when the write data is detected to be a compensation code next time; and when the compensation enabling signal of the current channel is a read compensation enabling signal, performing read compensation operation when the read data is detected to be the compensation code next time.
The write compensation operation is specifically as follows: writing one beat of compensation code when writing the compensation code; the read compensation operation specifically comprises: when the compensation code is read out, one beat of compensation code is read out.
Further comprising: and acquiring the written data of the preset bit of each channel, acquiring the position number of the alignment code which is written in each channel at the latest time when the alignment code exists in the written data of the preset bit of each channel, and outputting the written data by each channel according to the position number of the alignment code which is written in each channel at the latest time.
When the position numbers of the alignment codes written in the last time by each channel are not 0, synchronously reducing the position numbers of the alignment codes written in the last time by each channel to the position number of the alignment code written in the last time by at least one channel to be 0.
In a second aspect of the invention, a high-speed serial bus clock compensation system comprises a plurality of single-channel compensation modules and a compensation scheduling module, wherein one ends of the plurality of single-channel compensation modules are used for connecting a plurality of channels of a high-speed serial bus, and the other ends of the plurality of single-channel compensation modules are connected with the compensation scheduling module;
the single-channel compensation modules are respectively used for acquiring the written data quantity and the read data quantity of each channel and generating compensation applications of each channel according to the written data quantity and the read data quantity; the data processing device is also used for respectively acquiring current write-in data and current read-out data of each channel and generating a state signal of each channel according to the current write-in data and the current read-out data; the compensation scheduling module is also used for respectively receiving the compensation enabling signals of each channel sent by the compensation scheduling module and carrying out preset compensation operation on each channel according to the compensation enabling signals of each channel;
and the compensation scheduling module is used for receiving and generating a compensation enabling signal of each channel according to the state signal and the compensation application of each channel and respectively sending the compensation enabling signal to each single-channel compensation module.
Preferably, the system also comprises a multi-channel alignment module, wherein one end of the multi-channel alignment module is connected with a plurality of single-channel compensation modules; the multi-channel alignment module is used for acquiring the write-in data of the preset bits of each channel, acquiring the position number of the alignment code which is written in each channel at the latest time when the alignment code is in the write-in data of the preset bits of each channel, and outputting the write-in data by each channel according to the position number of the alignment code which is written in each channel at the latest time.
Compared with the prior art, the invention has the following beneficial effects:
the invention relates to a high-speed serial bus clock compensation method, which comprises the steps of obtaining the written data quantity and the read data quantity of each channel of a high-speed serial bus, generating compensation applications of each channel according to the written data quantity and the read data quantity, then generating state signals of each channel according to the current written data and the current read data of each channel, generating compensation enabling signals of each channel according to the state signals of each channel, and finally performing preset compensation operation on each channel according to the compensation enabling signals and the written or read data. The method has no phase requirement on each input clock of multiple channels, has very flexible usability, can be applied to multiple high-speed bus protocols, and can solve the problem of multi-channel interconnection of multiple high-speed bus physical layers. Meanwhile, the compensation operation of each channel is controlled through the state signal, and the reliability and the correctness of circuit transmission are effectively improved.
Furthermore, by acquiring the written data of the preset bits of each channel, and when the written data of the preset bits of each channel has the alignment code, acquiring the position number of the alignment code written last time by each channel, and then outputting the written data by each channel according to the position number of the alignment code written last time by each channel, the alignment process is realized based on the cache array, and the time delay of data transmission is effectively reduced.
Drawings
FIG. 1 is a flow chart of a high speed serial bus clock compensation method of the present invention;
FIG. 2 is a block diagram of a high speed serial bus clock compensation system of the present invention;
FIG. 3 is a schematic diagram of the clock compensation principle of the high-speed serial bus clock compensation method according to the present invention;
FIG. 4 is a timing diagram illustrating a high-speed serial bus clock compensation method according to the present invention;
FIG. 5 is a schematic diagram of data output of the multi-channel alignment module of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Moreover, the terms "comprises," "comprising," and any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or modules is not necessarily limited to those steps or modules explicitly listed, but may include other steps or modules not expressly listed or inherent to such process, method, article, or apparatus.
The invention is described in further detail below with reference to the accompanying drawings:
referring to fig. 1, in an embodiment of the present invention, a method for compensating a clock of a high-speed serial bus is provided, which includes the following steps: acquiring the written data quantity and the read data quantity of each channel of the high-speed serial bus, and generating a compensation application of each channel according to the written data quantity and the read data quantity; acquiring current write-in data and current read-out data of each channel of the high-speed serial bus, and generating a state signal of each channel according to the current write-in data and the current read-out data; and generating a compensation enabling signal of each channel according to the state signal and the compensation application of each channel, and performing preset compensation operation on each channel according to the compensation enabling signal of each channel.
The specific method for generating the compensation application of each channel according to the number of the written data and the number of the read data comprises the following steps: when the written data quantity of the current channel is more than the read data quantity by at least a first preset quantity, the compensation application of the current channel is a write compensation application; and when the read data quantity of the current channel is more than the write data quantity by at least a second preset quantity, the compensation application of the current channel is a read compensation application.
The specific method for generating the state signal of each channel according to the current write data and the current read data is as follows: when the current written data of the current channel is the compensation code, the state signal of the current channel is that the write compensation can be carried out, and when the current written data of the current channel is not the compensation code, the state signal of the current channel is that the write compensation can not be carried out; when the current read data of the current channel is the compensation code, the state signal of the current channel is that the read compensation can be performed, and when the current read data of the current channel is not the compensation code, the state signal of the current channel is that the read compensation cannot be performed.
The specific method for generating the compensation enable signal of each channel according to the state signal of each channel comprises the following steps: when the state signals of all the channels are write compensation impossible and the compensation application is a write compensation application, the compensation enabling signal of each channel is a write compensation enabling signal; when the state signals of all the channels are read compensation disabled and the compensation application is a read compensation application, the compensation enable signal of each channel is a read compensation enable signal.
Wherein the preset compensation operation comprises a write compensation operation and a read compensation operation; the specific method for performing the preset compensation operation on each channel according to the compensation enabling signal of each channel comprises the following steps: when the compensation enabling signal of the current channel is a write compensation enabling signal, performing write compensation operation when the write data is detected to be a compensation code next time; and when the compensation enabling signal of the current channel is a read compensation enabling signal, performing read compensation operation when the read data is detected to be the compensation code next time.
Wherein the write compensation operation specifically comprises: writing one beat of compensation code when writing the compensation code; the read compensation operation specifically comprises: when the compensation code is read out, one beat of compensation code is read out.
In one possible implementation, the high-speed serial bus clock compensation method further includes: and acquiring the written data of the preset bit of each channel, acquiring the position number of the alignment code which is written in each channel at the latest time when the alignment code exists in the written data of the preset bit of each channel, and outputting the written data by each channel according to the position number of the alignment code which is written in each channel at the latest time.
In order to reduce the transmission delay, when the position numbers of the alignment codes written in the last time by each channel are not all 0, the position numbers of the alignment codes written in the last time by each channel are synchronously reduced to the position number of the alignment code written in the last time by at least one channel is 0.
In summary, the high-speed serial bus clock compensation method of the present invention obtains the write data amount and the read data amount of each channel of the high-speed serial bus, generates the compensation application for each channel according to the write data amount and the read data amount, generates the status signal of each channel according to the current write data and the current read data of each channel, generates the compensation enable signal of each channel according to the status signal of each channel, and finally performs the preset compensation operation on each channel according to the compensation enable signal and the compensation application. Meanwhile, the compensation operation of each channel is controlled through the state signal, and the reliability and the correctness of circuit transmission are effectively improved.
Furthermore, by acquiring the written data of the preset bits of each channel, and when the written data of the preset bits of each channel has the alignment code, acquiring the position number of the alignment code written last time by each channel, and then outputting the written data by each channel according to the position number of the alignment code written last time by each channel, the alignment process is realized based on the cache array, and the time delay of data transmission is effectively reduced.
The following are embodiments of the apparatus of the present invention that may be used to perform embodiments of the method of the present invention. For details of non-careless mistakes in the embodiment of the apparatus, please refer to the embodiment of the method of the present invention.
Referring to fig. 2, in another embodiment of the present invention, a high-speed serial bus clock compensation system is provided, which includes a plurality of single-channel compensation modules and a compensation scheduling module, where one end of each of the plurality of single-channel compensation modules is used to connect to a plurality of channels of a high-speed serial bus, and the other end of each of the plurality of single-channel compensation modules is connected to the compensation scheduling module; the single-channel compensation modules are respectively used for acquiring the written data quantity and the read data quantity of each channel and generating compensation applications of each channel according to the written data quantity and the read data quantity; the data processing device is also used for respectively acquiring current write-in data and current read-out data of each channel and generating a state signal of each channel according to the current write-in data and the current read-out data; the compensation scheduling module is also used for respectively receiving the compensation enabling signals of each channel sent by the compensation scheduling module and carrying out preset compensation operation on each channel according to the compensation enabling signals of each channel; and the compensation scheduling module is used for receiving and generating a compensation enabling signal of each channel according to the state signal and the compensation application of each channel and respectively sending the compensation enabling signal to each single-channel compensation module.
In a possible implementation manner, the high-speed serial bus clock compensation system further comprises a multi-channel alignment module, wherein one end of the multi-channel alignment module is connected with a plurality of single-channel compensation modules; the multi-channel alignment module is used for acquiring the write-in data of the preset bits of each channel, acquiring the position number of the alignment code which is written in each channel at the latest time when the alignment code is in the write-in data of the preset bits of each channel, and outputting the write-in data by each channel according to the position number of the alignment code which is written in each channel at the latest time.
All relevant contents of the steps involved in the embodiment of the high-speed serial bus clock compensation method can be introduced to the functional description of the functional module corresponding to the high-speed serial bus clock compensation system in the embodiment of the present invention, and are not described herein again.
The division of the modules in the embodiments of the present invention is schematic, and only one logical function division is provided, and in actual implementation, there may be another division manner, and in addition, each functional module in each embodiment of the present invention may be integrated in one processor, or may exist alone physically, or two or more modules are integrated in one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode.
The high-speed serial bus clock compensation method and system of the present invention are described in the following with specific implementation modes.
The high-speed serial bus clock compensation method and the system can be used as IP (Internet protocol) to be provided for various high-speed bus protocol circuits based on Serdes, such as RapidIO, SpaceFirbe, PCIe and the like, and can effectively solve the multi-channel interconnection problem of high-speed bus phy (physical layer) such as RapidIO, SpaceFirbe, PCIe and the like.
The ip (intellectual property) kernel module is a pre-designed or even verified integrated circuit, device or component with certain function, and is used for assembly or integration by chip designers. Serdes is an abbreviation for Serializer/Deserializer. It is a mainstream Time Division Multiplexing (TDM), point-to-point (P2P) serial communication technology. That is, at the transmitting end, the multi-path low-speed parallel signals are converted into high-speed serial signals, and finally, at the receiving end, the high-speed serial signals are converted into low-speed parallel signals again through a transmission medium (an optical cable or a copper wire). The point-to-point serial communication technology fully utilizes the channel capacity of a transmission medium, reduces the number of required transmission channels and device pins, and greatly reduces the communication cost. RapidIO is a high-performance, low-pin-count, packet-switching-based interconnect architecture pioneered by Motorola and Mercury, and is an open interconnect technology standard designed to meet the demand of high-performance embedded systems in the future. RapidIO is mainly applied to internal interconnection of an embedded system, supports communication from a chip to a chip and from a board to a board, and can be used as a backboard (backhaul) connection of embedded equipment. Spacefiber is a spacecraft airborne data link and network technology that can operate on both copper and fiber optic cables. Initially for very high data rate instruments like Synthetic Aperture Radar (SAR) and multispectral imaging instruments, spacefiber enabled a wider range of spacecraft on-board communication applications due to its built-in QoS (quality of service) and FDIR (fault detection, isolation and recovery) capabilities and its backward compatibility with SpaceWire technology. SpaceWire runs at 2.5Gbits/s or higher, providing 12 times the throughput of SpaceWire links using current technologies that meet flight requirements, and allowing data from multiple SpaceWire devices to be aggregated on a single SpaceFire link. This significantly reduces the cable bundle quality and simplifies the redundancy strategy. PCI-express (peripheral component interconnect express) is a high-speed serial computer expansion bus standard, originally named "3 GIO", which was proposed by Intel in 2001, to replace the old PCI, PCI-X and AGP bus standards. PCIe belongs to high-speed serial point-to-point double-channel high-bandwidth transmission, connected devices distribute independent channel bandwidth and do not share bus bandwidth, and the PCIe mainly supports functions of active power management, error reporting, end-to-end reliable transmission, hot plug, quality of service (QOS) and the like. PCIe is renamed to PCI-Express, which is called PCI-e for short, after being authenticated and issued by PCI-SIG (PCI Special interest group).
In this embodiment, the high-speed serial bus clock compensation system includes 2 modules, which are a clock compensation module and a multi-channel alignment module, respectively, where the clock compensation module is composed of a plurality of single-channel compensation modules and a compensation scheduling module. The whole system structure is composed of a plurality of single-channel compensation modules, a compensation scheduling module and a multi-channel alignment module. The clock compensation module completes the clock compensation function of each channel and consists of a single-channel compensation module and a compensation scheduling module.
The single-channel compensation module is implemented based on asynchronous fifo (First Input First Output, First in First out queue), which is a traditional sequential execution method, and an instruction entered First completes and retires First, and then executes a second instruction. For asynchronous fifo, data is written into fifo by a control signal of one clock domain, and data is read out of fifo by a control signal of the other clock domain, that is, the changing action of the read-write pointer is generated by different clocks, so that no phase requirement is required for each input clock.
The single-channel compensation module is internally provided with a memory or a register for storage, can be configured according to specific use conditions, defaults to 16, and can store 16 data, a write pointer, a read pointer, a group (2, respectively used for the write pointer and the read pointer) of gray code/binary conversion logic modules for pointer asynchronous conversion, and a group (2, respectively used for the write pointer and the read pointer) of comparison control logic modules. The write pointer is used for recording how many data are written in the write clock domain, and the read pointer is used for recording how many data are read in the read clock domain. Because the read-write clock domains are different, the read pointer needs to be synchronized to the write clock domain through a Gray code/binary conversion logic module for comparing with the write pointer to judge whether the data is full; similarly, the write pointer needs to be synchronized to the read clock field for comparing with the read pointer to determine whether the data is read empty.
The comparison control logic module has 3 functions: 1. and monitoring the read-write pointer to judge whether the current state needs clock compensation. In a write clock domain, when the written data is greater than or equal to n than the read data value, outputting a write compensation application; similarly, in the read clock domain, when the number of the written data is more than the number of the read data and is less than or equal to m, the read compensation application is output. The specific numerical parameters of n and m can be matched, and the user can set the parameters according to the actual requirements of the user. 2. The states of the write data and the read data are detected to determine whether clock compensation is possible at the present time, and a state signal is output. The data passing through the module consists of general data and a compensating code sequence, which is a fixed character specified according to a particular high-speed bus protocol. The comparison control logic module can monitor the data to be written and read in real time, if the data is a compensation code, the compensation operation can be carried out immediately, and the status signal is that the write compensation can be carried out or the read compensation can be carried out. 3. And receiving a compensation enabling signal and executing compensation operation. When the compensation enable signal is received, the compensation operation is performed when the compensation code is detected next time. The write compensation operation is carried out, namely, one beat of compensation code is written in less when the compensation code sequence is written in, and the operation of reading data is normal, so that the difference of the number of writing and reading pointers can be reduced; similarly, when reading compensation, the compensation code sequence is read out, and the compensation code is output by one beat, so that the difference between the numbers of the write pointer and the read pointer can be enlarged.
The number of the single-channel compensation module is the same as the number of the channels, and the parameters of the depth of the storage buffer, the judgment of the compensation code sequence and the comparison of the difference values of the read-write pointer and the m value are matched, so that the universality of the single-channel compensation module can be expanded, and the single-channel compensation module can be used in various high-speed bus protocols.
The compensation scheduling module is mainly responsible for coordinating the compensation execution time of each single-channel compensation module, increasing the reliability of the circuit and ensuring that multi-channel transmission errors are not caused by compensation behaviors.
Referring to fig. 3, each single-channel compensation module monitors the internal state in real time, and mainly detects whether a compensation operation is currently required, and whether currently output data is general data or a compensation sequence. And initiating a compensation request to a compensation scheduling module when the compensation operation is needed. And the compensation scheduling module monitors whether each single-channel compensation module is in a state of being compensated immediately or not in real time while receiving the compensation request, namely write compensation can be carried out, write compensation cannot be carried out, read compensation cannot be carried out or read compensation can be carried out. Specifically, the compensation scheduling module receives state signals output by each single-channel compensation module, and the state signals indicate whether the single-channel compensation module is currently receiving the compensation code, i.e., whether the compensation operation can be immediately performed. When they are not in a state in which they can be compensated immediately, that is, both write compensations cannot be performed or both read compensations cannot be performed, they may be sent out a compensation enable signal to perform timing compensation. Specifically, since the input clocks of the channels may be different, there are times when some of the single-channel compensation modules can perform the compensation operation, but other single-channel compensation modules cannot perform the compensation operation. In this case, if the compensation operation is performed, a data alignment error is generated. In order to avoid this situation, the compensation scheduling module initiates a clock compensation command at a time when each single-channel compensation module cannot perform compensation, and each single-channel compensation module performs clock compensation operation when a next compensation opportunity arrives, as shown in fig. 4, the compensation opportunity means that each single-channel compensation module is not in a state capable of performing compensation operation immediately.
Meanwhile, because the input clocks of the channels and the receiving clocks are asynchronous, inevitable data offset can be generated among the channels. The multi-channel alignment module mainly comprises Ram or a register array, and aligns and outputs data according to an input alignment code (A code). The alignment code is similar to the compensation sequence and is a fixed character specified by the high-speed bus protocol, and is specially used for synchronous use of channels. Ram or a register array buffers the data for each lane and the output data for each lane is output from selected locations in these buffers. There is a counter per channel to count the location of the last incoming a-code. And when the A codes exist in the caches of all the channels, the counter value of each channel is stored, and each channel selects the corresponding cache position according to the value to output data. Referring to fig. 5, the a code bit of channel 0 is 4, the a code bit of channel 1 is 5, if channel 0 is aligned with channel 1, the counters of the two channels are respectively stored as 4 and 5, the output positions, i.e. 4 and 5, are output, i.e. they output a code at the same time in the beat, and D5 is output at the same time in the next beat.
Meanwhile, in order to reduce the propagation delay of transmission, when the counter values of the channels are not all 0, all the counter values are reduced until one of the counter values is 0. For example, in FIG. 5, when channel 0 and channel 1 need to be aligned, the counters are 4 and 5, respectively, and they are not 0, and the counters are both decremented by 1. The counters for channel 0 and channel 1 are now 3 and 4, respectively, which are still not 0, and continue to decrement by 1, and so on. The counters up to channel 0 and channel 1 are 0 and 1, respectively. The purpose of this is to reduce the link delay, since the counter is the beat register for selecting the data output in the register array, the smaller the counter value, the smaller the beat number registered in the register array for the output data, and the shorter the link delay.
The length of the buffer queue can be matched according to a specific used protocol and the actual used system condition, and the alignment code can be matched according to the specific used protocol and is compatible with various bus protocols such as RapidIO, PCIe and the like.
In another embodiment of the invention, the high-speed serial bus clock compensation system is applied to a 16-port RapidIO switching circuit, the interface can be configured to be in two working states of X1 or X4, and the current stage of tape-out is entered through front-end verification, FPGA prototype verification and rear-end layout netlist simulation. The circuit can accurately and stably carry out data communication with other external RapidIO interfaces. The parameters according to the actual situation are configured as follows: the compensation sequence is KRRR, the alignment code is A, the compensation fifo depth is 12, the uncompensated range is 5-7, the register array is 8-level, and four single-channel compensation modules, one compensation scheduling module and one multi-channel alignment module are adopted. In the alignment part, because the used Serdes is based on 8b/10b and outputs 16bit data, when each single-channel compensation module is used for distinguishing whether the single-channel compensation module is in a state of being compensated immediately, characters needing to be detected are divided into two-beat character detection of KR and RR and three-beat data detection of xK, RR and Rx (x represents any character). They must satisfy the above two character discriminations at the same time, and the compensation scheduling module will send out the compensation operation to enable the compensation when they are not in the state of being compensated immediately. When the device works in the X1 mode, the connection is stable and no data is lost. And the clock compensation and data alignment function of 4 channels is realized when the device works in an X4 mode. The alignment processing adopts a cache array, and compared with the alignment function completed by fifo, the time delay of data transmission is reduced. The IP module based on the invention has simple interface, convenient integration and reduced design complexity.
The above-mentioned contents are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modification made on the basis of the technical idea of the present invention falls within the protection scope of the claims of the present invention.
Claims (10)
1. A high-speed serial bus clock compensation method is characterized by comprising the following steps:
acquiring the written data quantity and the read data quantity of each channel of the high-speed serial bus, and generating a compensation application of each channel according to the written data quantity and the read data quantity;
acquiring current write-in data and current read-out data of each channel of the high-speed serial bus, and generating a state signal of each channel according to the current write-in data and the current read-out data;
and generating a compensation enabling signal of each channel according to the state signal and the compensation application of each channel, and performing preset compensation operation on each channel according to the compensation enabling signal of each channel.
2. The method for compensating the clock of the high-speed serial bus according to claim 1, wherein the specific method for generating the compensation application of each channel according to the number of the write data and the number of the read data is as follows:
when the written data quantity of the current channel is more than the read data quantity by at least a first preset quantity, the compensation application of the current channel is a write compensation application; and when the read data quantity of the current channel is more than the write data quantity by at least a second preset quantity, the compensation application of the current channel is a read compensation application.
3. The method for compensating the clock of the high-speed serial bus according to claim 2, wherein the specific method for generating the status signal of each channel according to the current write data and the current read data is as follows:
when the current written data of the current channel is the compensation code, the state signal of the current channel is that the write compensation can be carried out, and when the current written data of the current channel is not the compensation code, the state signal of the current channel is that the write compensation can not be carried out; when the current read data of the current channel is the compensation code, the state signal of the current channel is that the read compensation can be performed, and when the current read data of the current channel is not the compensation code, the state signal of the current channel is that the read compensation cannot be performed.
4. The method for compensating the clock of the high-speed serial bus according to claim 3, wherein the specific method for generating the compensation enable signal of each channel according to the status signal of each channel comprises:
when the state signals of all the channels are write compensation disabled and the compensation application is a write compensation application, the compensation enabling signal of each channel is a write compensation enabling signal; when the state signals of all the channels are read compensation disabled and the compensation application is a read compensation application, the compensation enable signal of each channel is a read compensation enable signal.
5. The high-speed serial bus clock compensation method of claim 4, wherein the preset compensation operation comprises a write compensation operation and a read compensation operation;
the specific method for performing the preset compensation operation on each channel according to the compensation enabling signal of each channel comprises the following steps: when the compensation enabling signal of the current channel is a write compensation enabling signal, performing write compensation operation when the write data is detected to be a compensation code next time; and when the compensation enabling signal of the current channel is a read compensation enabling signal, performing read compensation operation when the read data is detected to be the compensation code next time.
6. The high-speed serial bus clock compensation method of claim 5, wherein the write compensation operation is specifically: writing one beat of compensation code when writing the compensation code; the read compensation operation specifically comprises: when the compensation code is read out, one beat of compensation code is read out.
7. The high-speed serial bus clock compensation method of claim 1, further comprising: and acquiring the written data of the preset bit of each channel, acquiring the position number of the alignment code which is written in each channel at the latest time when the alignment code exists in the written data of the preset bit of each channel, and outputting the written data by each channel according to the position number of the alignment code which is written in each channel at the latest time.
8. The method according to claim 7, wherein when the position numbers of the alignment codes written last time in each channel are not all 0, the position numbers of the alignment codes written last time in each channel are synchronously decreased to 0.
9. A high-speed serial bus clock compensation system is characterized by comprising a plurality of single-channel compensation modules and a compensation scheduling module, wherein one ends of the single-channel compensation modules are used for being connected with a plurality of channels of a high-speed serial bus, and the other ends of the single-channel compensation modules are connected with the compensation scheduling module;
the single-channel compensation modules are respectively used for acquiring the written data quantity and the read data quantity of each channel and generating compensation applications of each channel according to the written data quantity and the read data quantity; the data processing device is also used for respectively acquiring current write-in data and current read-out data of each channel and generating a state signal of each channel according to the current write-in data and the current read-out data; the compensation scheduling module is also used for respectively receiving the compensation enabling signals of each channel sent by the compensation scheduling module and carrying out preset compensation operation on each channel according to the compensation enabling signals of each channel;
and the compensation scheduling module is used for receiving and generating a compensation enabling signal of each channel according to the state signal and the compensation application of each channel and respectively sending the compensation enabling signal to each single-channel compensation module.
10. The system according to claim 9, further comprising a multi-channel alignment module, wherein one end of the multi-channel alignment module is connected to the plurality of single-channel compensation modules;
the multi-channel alignment module is used for acquiring the write-in data of the preset bits of each channel, acquiring the position number of the alignment code which is written in each channel at the latest time when the alignment code is in the write-in data of the preset bits of each channel, and outputting the write-in data by each channel according to the position number of the alignment code which is written in each channel at the latest time.
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