CN116737624B - High-performance data access device - Google Patents
High-performance data access device Download PDFInfo
- Publication number
- CN116737624B CN116737624B CN202310669039.1A CN202310669039A CN116737624B CN 116737624 B CN116737624 B CN 116737624B CN 202310669039 A CN202310669039 A CN 202310669039A CN 116737624 B CN116737624 B CN 116737624B
- Authority
- CN
- China
- Prior art keywords
- data transmission
- access device
- data access
- performance data
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000005540 biological transmission Effects 0.000 claims abstract description 314
- 238000004891 communication Methods 0.000 claims description 56
- 239000002131 composite material Substances 0.000 claims description 15
- 238000012545 processing Methods 0.000 claims description 12
- 239000005441 aurora Substances 0.000 claims description 7
- 238000011144 upstream manufacturing Methods 0.000 claims description 6
- 239000007787 solid Substances 0.000 claims description 3
- 238000013461 design Methods 0.000 description 18
- 238000010586 diagram Methods 0.000 description 12
- 238000000034 method Methods 0.000 description 12
- 238000007726 management method Methods 0.000 description 10
- 230000008054 signal transmission Effects 0.000 description 6
- 239000013307 optical fiber Substances 0.000 description 5
- 238000013403 standard screening design Methods 0.000 description 4
- 230000011664 signaling Effects 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000013500 data storage Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 238000000547 structure data Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a high-performance data access device, which takes a PCIe bus interface or an instrument expansion bus interface based on PCIe as a management control interface of the high-performance data access device, takes a set of high-speed data transmission interfaces based on FPGA as high-speed data transmission channels between the high-performance data access device and other I/O modules or among a plurality of cascade or parallel high-performance data access devices, and can strengthen the data transmission capacity and the data access capacity of the modules and the expansion coordination capacity with other I/O modules while considering the usability and compatibility of the modules.
Description
Technical Field
The invention belongs to the technical field of data communication and data access, and particularly relates to a high-performance data access device.
Background
With the rapid development of analog circuits, digital circuits and signal processing technologies, the requirements for wideband radio frequency signal acquisition, analysis, processing and generation are increasing, and the acquisition, analysis, processing and generation of wideband radio frequency signals are involved in many industries and applications; such as wireless communication, satellite communication, navigation, electronic countermeasure, intelligent driving, weather prediction, etc., and applications in these fields require a lot of tests and verification often; meanwhile, the data volume of the signals required to be collected and analyzed by the applications is very large, taking a broadband radio frequency signal with an instantaneous bandwidth of 1GHz as an example, the generated data rate is 5GB/s (each sampling sample is 2 bytes), particularly in the test of a MIMO or phased array radio frequency system, a plurality of channels are required to collect, store and generate the signals at the same time, the data rate is multiplied by the number of corresponding channels on the basis of 5GB/s, for example, a typical MIMO system with an instantaneous bandwidth of 1GHz with 8 receivers and 8 transmitters generates 40GB of data volume per second, and if the instantaneous bandwidth of the signals is further increased, the data rate generated by single channel signal collection is further increased; thus, high data rates in applications place extremely high demands on data access devices, and few devices are available on the market to accomplish this.
In addition, the broadband radio frequency signal can accumulate mass data after long-time acquisition and storage, when the storage capacity of one storage device cannot meet the requirement, a plurality of storage devices can be combined to obtain more storage space, and not only is the common high-performance storage device capable of only achieving the data access capacity of 5-10 GB/s at most, but also the access requirement of 1-2 signal channels can be met for the broadband radio frequency signal with the instantaneous bandwidth of 1GHz, so that each signal channel is required to correspond to an independent data access device for one-to-one data access by a more complex broadband radio frequency signal acquisition task; at the same time, these requirements are not met by standardized products, so users often have to choose expensive special custom systems to meet the requirements, which increases the cost of the test considerably.
In summary, in practical applications, a high-speed data access device with data high-speed access capability, interface capacity expansion capability, connection topology variable characteristics, and data high-speed access capability, which is compatible with commercial shelving platforms to reduce the overall cost of the system, is very helpful for such applications.
At present, data access equipment with characteristics of commercial shelf platform support, data high-speed transmission interface, high-speed data access performance, expandable modularized structure and the like in the market is mainly bus type custom equipment, mainly based on buses for data transmission, main stream bus protocols adopted are PCIe, PXIe, CPCIe, VPX and the like, and the latter three are expansion based on PCIe buses, and the main data transmission technology still takes the PCIe buses as cores.
In the prior art, the total bandwidth of a system based on a PCIe bus is limited by the number of PCIe connections and single-connection data communication bandwidth supported by a CPU and a back plate of a system case, and takes an advanced PXIe system in the market as an example, wherein the PXIe system supports up to 24 PCIe connections, each connection supports up to 1GB/s of theoretical bandwidth, and the theoretical bandwidth of the system is up to 24GB/s; therefore, no matter how many data access modules are configured in the system, the amount of data that can be accessed by the system per second does not exceed 24GB, and because the system has other data communication overhead, the performance that can be achieved actually is smaller than this value; if the user needs to store or read more than 24GB of data per second, a plurality of PXIe systems must be constructed to realize the operation; meanwhile, the theoretical data bandwidth of a single PXIe module is 8GB/s, which means that the single PXIe module cannot continuously transmit signals with the instantaneous bandwidth of more than 1.6GHz through the bus of the backboard.
In addition, when the PCIe bus-based system performs data reading and writing, the disk I/O operation needs CPU scheduling, which makes the CPU a bottleneck of data reading and writing capability, and meanwhile, the priority and time allocation of the CPU for completing other processing tasks are limited, especially when large data volume data access is performed; therefore, the data access module in the prior art is difficult to meet the requirements of high-bandwidth signal data access and high-speed data access by more channels on the premise that the total data access rate and the throughput rate of single module number are limited by the PCIe bandwidth of the system and high-priority I/O task processing of the CPU is required, and based on this, how to provide a high-performance data access device which can simultaneously meet the requirements of high-speed data access, PCIe bus system support, modularly expansion, variable topology connection and no CPU intervention scheduling is needed has become a problem to be solved.
Disclosure of Invention
The invention aims to provide a high-performance data access device which is used for solving the problem that the prior art is difficult to meet the requirements of high-bandwidth signal data access and high-speed data access of more channels at the same time.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
in a first aspect, there is provided a high performance data access apparatus comprising:
the FPGA module is in communication connection with the system controller through the communication and control bus interface so as to perform data communication with the system controller based on the communication and control bus interface, and the communication and control bus interface comprises a PCIe bus interface or an instrument expansion bus interface based on PCIe;
the high performance data access device further includes:
the system comprises a plurality of high-speed data transmission interfaces based on FPGA modules and a plurality of storage modules, wherein the FPGA modules are respectively and electrically connected with each storage module and each high-speed data transmission interface;
the plurality of high-speed data transmission interfaces comprise an uplink data transmission interface and a downlink data transmission interface;
the uplink data transmission interface is used for being in communication connection with a signal receiving and transmitting device or a downlink data transmission interface of a previous-stage high-performance data access device with a cascade relation with the high-performance data access device, and the downlink data transmission interface is used for being in communication connection with the signal receiving and transmitting device or an uplink data transmission interface of a subsequent-stage high-performance data access device with a cascade relation with the high-performance data access device, so that the high-performance data access device forms a cascade connection mode, a parallel connection mode, a point-to-point connection mode, a star connection mode or a composite connection mode combining any connection modes with the signal receiving and transmitting device and the other high-performance data access devices based on the uplink data transmission interface and/or the downlink data transmission interface of the high-performance data access device.
Based on the above disclosure, the high performance data access device provided by the invention uses the PCIe bus interface or the PCIe-based instrument expansion bus interface as a management control interface of the system controller to the high performance data access device, so that a complete signal acquisition, storage, reading and generation system can be combined and constructed by using the mature hardware and software ecosystem of the bus platform, so that the device has good compatibility; meanwhile, a control interface based on PCIe is adopted, the interface bandwidth of an 8GB/s module can be provided, and the high-performance data access device is connected with external data equipment by adopting a high-speed data transmission interface of the high-performance data access device, so that the data access device can provide data transmission bandwidth of more than 24GB/s, and the requirements of most high-speed data access applications can be met.
Furthermore, the device uses a set of high-speed data transmission interfaces based on the FPGA as high-speed data transmission channels between the high-performance data access devices and other I/O modules (namely external data equipment and signal receiving and transmitting equipment), or between a plurality of cascade or parallel high-performance data access devices, based on the high-speed data transmission channels, a cascade, a butt connection, a parallel connection, a star connection or a combined connection mode of the cascade between the other I/O modules and the rest high-performance data access devices can be realized, so that a very flexible topological connection structure can be realized between the high-performance data access devices and the other I/O modules, each high-performance data access device can provide 24GB/s data transmission bandwidth, and based on the high-speed data transmission bandwidth, the device can obtain high-performance data transmission capacity far higher than that of a traditional system after being expanded, and therefore, the data access requirement of a multi-channel broadband radio frequency application of high-speed data transmission can be met.
In addition, the device is provided with an FPGA module, so that the device can directly use an own FPGA processing unit to perform the I/O operation of the disk during data reading and writing; therefore, the device does not need to intervene in a CPU of an external system to carry out data read-write scheduling, and can avoid the problem that the CPU becomes the bottleneck limit of the data read-write capability.
Through the design, the PCIe bus interface or the PCIe-based instrument expansion bus interface is used as a management control interface of the high-performance data access device, and a set of high-speed data transmission interface based on the FPGA is used as a high-speed data transmission channel between the high-performance data access device and other I/O modules or among a plurality of cascade or parallel high-performance data access devices, so that the high-speed data access device can strengthen the data transmission capacity and the data access capacity of the modules and the expansion coordination capacity with other I/O modules while considering the usability and the compatibility of the modules, and can enable the high-speed data access, PCIe bus system support, modularized expansion and topological connection variable characteristics to be suitable for large-scale application and popularization in the field of high-speed data access while needing CPU intervention scheduling.
In one possible design, the high performance data access device further comprises: and the interface IP module comprises at least one MGT transceiver, and the FPGA module is electrically connected with each uplink data transmission interface and each downlink data transmission interface through the interface IP module so as to control the at least one MGT transceiver to realize the data transmission function of the uplink data transmission interface and the downlink data transmission interface through the interface IP module.
In one possible design, the high performance data access device further comprises: at least one DRAM module, wherein the FPGA module is electrically connected with each DRAM module respectively;
the FPGA module is used for splitting and encoding the high-speed data stream when receiving the high-speed data stream transmitted from the local uplink data transmission interface or the local downlink data transmission interface to obtain processed data, and writing the processed data into each storage module in parallel based on each DRAM module;
the FPGA module is also used for reading data from each storage module based on each DRAM module, carrying out data decoding and merging processing on the read data to obtain decoded and merged data, and sending the decoded and merged data to external data equipment and/or the signal receiving and transmitting equipment through an uplink data transmission interface or a downlink data transmission interface of the FPGA module.
In one possible design, the uplink data transmission interface and the downlink data transmission interface each use multiple full duplex serial links to realize data transmission, and the data communication protocol used by the uplink data transmission interface and the downlink data transmission interface includes Aurora protocol.
In one possible design, both the upstream data transmission interface and the downstream data transmission interface employ Nano-Pitch connectors.
In one possible design, the high performance data access device further comprises: and the control bus interface connector is used for connecting the high-performance data access device with a backboard bus interface of the data transmission equipment based on the PCIe bus through the control bus interface connector so as to realize data communication between the high-performance data access device and the data transmission equipment based on the PCIe bus.
In one possible design, any one of the plurality of storage modules employs a solid state disk with SATA or NVMe interface.
In one possible design, the PCIe-based instrument expansion bus interface includes: a PXIe bus interface, a CPCIe bus interface, or a VPX bus interface.
In one possible design, the high-performance data access device performs data transmission with an external data device, the signal transceiver device, or a target high-performance data access device in the following manner;
The high-performance data access device acquires a data transmission mode, wherein the data transmission mode comprises a cascade data transmission mode, a point-to-point data transmission mode, a parallel data transmission mode, a star data transmission mode or a composite data transmission mode combining any transmission modes;
if the data transmission mode is a cascade data transmission mode, the high-performance data access device acquires a destination equipment address of a target high-performance data access device;
the high-performance data access device acquires data to be transmitted from external data equipment, the signal receiving and transmitting equipment or corresponding storage modules, and generates a data packet based on the data to be transmitted and the destination equipment address;
the high-performance data access device utilizes a corresponding uplink data transmission interface or a corresponding downlink data transmission interface to transmit the data packet to a higher-level high-performance data access device or a lower-level high-performance data access device connected with the high-performance data access device, so that the higher-level high-performance data access device or the lower-level high-performance data access device judges whether a destination equipment address in the data packet is consistent with a local equipment address, and when the destination equipment address is inconsistent with the local equipment address, the data packet is transmitted again until the destination equipment address is transmitted to the target high-performance data access device;
If the data transmission mode is a point-to-point data transmission mode, the high-performance data access device reads data to be transmitted from each corresponding storage module and directly transmits the data to be transmitted to the external data equipment or the signal receiving and transmitting equipment through a corresponding uplink data transmission interface or downlink data transmission interface; or (b)
The high-performance data access device acquires data to be stored from external data equipment or the signal receiving and transmitting equipment through a corresponding uplink data transmission interface or a corresponding downlink data transmission interface, and stores the data to be stored into each storage module corresponding to the high-performance data access device;
if the data transmission mode is a parallel data transmission mode, the high-performance data access device reads data to be transmitted from each corresponding storage module, and directly transmits the data to be transmitted to the external data equipment or the signal receiving and transmitting equipment in a multi-channel data transmission mode through a corresponding uplink data transmission interface and downlink data transmission interface; or (b)
The high-performance data access device acquires data to be stored from external data equipment or the signal receiving and transmitting equipment in a multi-channel data transmission mode through the corresponding uplink data transmission interface and the corresponding downlink data transmission interface, and stores the data to be stored into each storage module corresponding to the high-performance data access device.
In one possible design, the high performance data access device determines the data transfer mode as follows;
the high-performance data access device receives an equipment address addressing instruction sent by the system controller, and sends equipment address inquiry information to a designated high-performance data access device through a corresponding uplink data transmission interface or downlink data transmission interface so as to receive a target equipment address sent by the designated high-performance data access device, wherein the designated high-performance data access device is all high-performance data access devices with a connection relation with the high-performance data access device;
the high-performance data access device sends the self device address and the target device address to the system controller through the communication and control bus interface, so that the system controller determines the connection relation and the data transmission mode between the high-performance data access device and the appointed high-performance data access device according to the uplink data transmission interface and the downlink data transmission interface which are connected with the appointed high-performance data access device, the target device address and the self device address.
The beneficial effects are that:
(1) The invention takes a PCIe bus interface or an instrument expansion bus interface based on PCIe as a management control interface of a high-performance data access device, takes a set of high-speed data transmission interface based on FPGA as a high-speed data transmission channel between the high-performance data access device and other I/O modules or between a plurality of cascade or parallel high-performance data access devices, and can strengthen the data transmission capacity and the data access capacity of the modules and the expansion coordination capacity with other I/O modules while considering the usability and compatibility of the modules.
Drawings
FIG. 1 is a schematic diagram of a high performance data access device according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a first portion of an FPGA module provided in an embodiment of the present invention;
FIG. 3 is a circuit diagram of a second portion of the FPGA module provided by an embodiment of the present invention;
fig. 4 is a circuit diagram of a high-speed data transmission interface according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a first application structure of a high performance data access device according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a second application structure of a high performance data access device according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a third application structure of a high performance data access device according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a fourth application structure of a high performance data access device according to an embodiment of the present invention;
fig. 9 is a specific circuit diagram of a communication and control bus interface according to an embodiment of the present invention.
Detailed Description
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the present invention will be briefly described below with reference to the accompanying drawings and the description of the embodiments or the prior art, and it is obvious that the following description of the structure of the drawings is only some embodiments of the present invention, and other drawings can be obtained according to these drawings without inventive effort to a person skilled in the art. It should be noted that the description of these examples is for aiding in understanding the present invention, but is not intended to limit the present invention.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments of the present invention.
It should be understood that for the term "and/or" that may appear herein, it is merely one association relationship that describes an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: a alone, B alone, and both a and B; for the term "/and" that may appear herein, which is descriptive of another associative object relationship, it means that there may be two relationships, e.g., a/and B, it may be expressed that: a alone, a alone and B alone; in addition, for the character "/" that may appear herein, it is generally indicated that the context associated object is an "or" relationship.
Examples:
referring to fig. 1 to 9, the high performance data access device provided in this embodiment may include, but is not limited to: the system comprises an FPGA module, a communication and control bus interface, a plurality of high-speed data transmission interfaces based on the FPGA module and a plurality of storage modules, wherein the FPGA module is in communication connection with a system controller through the communication and control bus interface so as to perform data communication with the system controller based on the communication and control bus interface; based on the method, the device can not only accept the control and management of a system controller, but also enable the PCIe bus interface and the PCIe-based instrument expansion bus interface to have mature and complete hardware and software ecosystems, so that a user can easily add various I/O modules based on the bus platform, and control and manage the device by using mature system and data management software; in addition, the bus platform also provides a modularized architecture, so that users can easily utilize different types and numbers of modules to expand functions and capabilities of the system; therefore, the compatibility and expansibility of the device can be greatly improved.
In specific implementation, the device is constructed by taking the FPAG as a core, namely comprises an FPGA module and a plurality of high-speed data transmission interfaces based on the FPGA module, wherein a FPGA (Field Programmable Gate Array) device belongs to a semi-custom circuit in an application specific integrated circuit, is a programmable logic array, has high-speed data throughput capacity, high-speed logic and time sequence control capacity, and is suitable for being used for realizing functions such as a high-speed serial bus, real-time signal processing, time sequence logic, trigger timing and the like; meanwhile, the high-performance FPGA chip usually has multiple MGTs (Multi-Gigabit Transceiver), namely a high-speed Serial transceiver, multiple PCIe resources, and a large number of digital I/O channels, where the MGTs, PCIe resources, and digital I/O channels can implement high-speed communication protocols (such as Aurora, PCIe, NVMe, SATA, serial RapidIO, JESD204, USB protocols, etc.) of the FPGA and external data devices; therefore, the high-performance data access device adopts the high-speed data transmission interface based on the FPGA to carry out data transmission, so that the transmission efficiency can be greatly improved; in this embodiment, the circuit diagram of the FPGA processing unit is shown in fig. 2 and 3, and the specific circuit diagram of the high-speed data transmission interface is shown in fig. 4.
When the method is applied specifically, the FPGA module is electrically connected with each storage module and each high-speed data transmission interface respectively so as to transmit the data stored in one or more storage modules to external data equipment and/or post-signal receiving and transmitting equipment based on each high-speed data transmission interface; and storing the received data in one or more storage modules by receiving data transmitted by each high-speed data transmission interface (i.e., data transmitted to the device by the external data device and/or the signal transceiver device).
Further, the plurality of high-speed data transmission interfaces include an uplink data transmission interface and a downlink data transmission interface, so that based on the data transmission structure, different connection modes between the high-performance data access device and other I/O devices (such as external data devices or signal transceiver devices) and other high-performance data access devices can be realized.
In this embodiment, the uplink data transmission interface is configured to be communicatively connected to a downlink data transmission interface of a signal transceiver or a previous stage high performance data access device having a cascade relationship with the high performance data access device, where the downlink data transmission interface is configured to be communicatively connected to an uplink data transmission interface of the signal transceiver or a subsequent stage high performance data access device having a cascade relationship with the high performance data access device; for example, the high-performance data access device can be in communication connection with the signal transceiver or the downstream data transmission interface of the former-stage high-performance data access device with cascade connection with the host through the upstream data transmission interface, and is in communication connection with the upstream data transmission interface of the latter-stage high-performance data access device with cascade connection with the host through the downstream data transmission interface of the host; thus, cascade connection between the local machine and the signal receiving and transmitting equipment and between the local machine and the rest high-performance data access devices can be realized; for example, the high-performance data access device may be further configured to connect, through the local uplink data transmission interface and the local downlink data transmission interface, the signal transmission interface of the signal transceiver device, that is, the local high-speed data transmission interface, to be correspondingly connected to the signal transmission interface of the signal transceiver device, so that the high-performance data access device may be connected in parallel with the signal transceiver device based on the local uplink data transmission interface and the local downlink data transmission interface; furthermore, in addition to the above two connection structures, connection expansion can be performed based on the above connection structures, so that the local device forms a point-to-point connection mode, a star connection mode or a composite connection mode combining any of the above connection modes with each signal transceiver and the rest high-performance data access device based on its corresponding uplink data transmission interface and/or downlink data transmission interface.
In a specific implementation, the following describes the above more connection modes respectively, that is, if a point-to-point connection mode is to be formed in the case that there are multiple high-performance data access devices, each high-performance data access device is connected to the signal transceiver device through its own high-speed data transmission interface (i.e., uplink or downlink data transmission interface), so that each high-performance data access device and the corresponding signal transceiver device are connected in a one-to-one connection mode.
Meanwhile, if a star connection mode is to be formed, each signal transmission interface of one signal transceiver device may be used to connect a plurality of high-performance data access devices (i.e., one signal transmission interface is connected with one high-performance data access device); similarly, on the basis of the star connection, cascade connection is performed, that is, one signal transceiver uses a corresponding signal transmission interface to connect a plurality of high-performance data access devices, each high-performance data access device is connected with a next-stage high-performance data access device in cascade through a corresponding uplink or downlink data transmission interface, so that the plurality of high-performance data access devices and the signal transceiver can be in a composite connection mode of star connection and cascade connection to realize communication connection; of course, the other composite connection modes are not described in detail.
In addition, in this embodiment, if there are multiple signal transceiving devices, the multiple signal transceiving devices may be connected in cascade, and the last signal transceiving device or the first signal transceiving device in cascade may be communicatively connected to the high-speed data transmission interface of the high-performance data access device, so that cascade data transmission between the multiple signal transceiving devices may be implemented based on the high-performance access device; of course, different connection modes can be realized based on the device according to actual use, so as to meet the data access requirements under different use scenes.
Based on the above hardware structure, the device can realize a composite connection mode (such as a composite connection mode combining star and cascade) combined with cascade connection, opposite connection, parallel connection and star connection or any connection mode between other I/O modules and other high-performance data access devices, so that a very flexible topological connection structure can be realized between a plurality of high-performance data access devices and between the high-performance data access devices and other I/O modules, and each high-performance data access device can provide 24GB/s data transmission bandwidth, thereby enabling the device to obtain high-performance data transmission capability far higher than that of a traditional system after expansion.
In this embodiment, an example PCIe-based instrument expansion bus interface may include, but is not limited to: a PXIe bus interface, a CPCIe bus interface, or a VPX bus interface is preferably used in a specific application, and a circuit diagram thereof can be seen in fig. 9.
Optionally, for example, the uplink data transmission interface and the downlink data transmission interface each use multiple full duplex serial links to realize data transmission, for example, the data transmission interface and the downlink data transmission interface may be set as 4-6 full duplex serial links; meanwhile, the data communication protocol adopted by the uplink data transmission interface and the downlink data transmission interface includes Aurora protocol to realize data communication, and of course, other protocols can be adopted, which is not limited to the foregoing examples; still further, the uplink data transmission interface and the downlink data transmission interface may be, but are not limited to, employing Nano-Pitch standard 42 pin (not limited to this standard) connectors as compact and high rate connection interfaces, wherein each Nano-Pitch interface may provide up to 6 full duplex Aurora links at rates up to 16 Gbps; thus, through the design, on one hand, the Nano-Pitch connector has a compact size of 5.0x15.0x9.0mm and an assembly height of 12.0mm connector to the cable, and the size of the device can be controlled to be very compact, so that the size of the device is reduced, and the portability is improved; on the other hand, the device also has extremely high data transmission performance and a convenient plugging mode, for example, on the basis of the 6 full duplex Aurora links, the device can provide bidirectional data transmission capability of 96Gbps or 12GB/s in each direction; if two Nano-Pitch interfaces are connected in parallel between two high-performance data access devices, a bi-directional data transmission channel of 192Gbps or 24GB/s in each direction can be established, so that high-speed data transmission is realized; of course, the foregoing data is merely illustrative and is not limited to this number of links and total rate.
Therefore, through the design, the device uses the PCIe bus interface or the PCIe-based instrument expansion bus interface as a management control interface of the high-performance data access device, and uses a set of high-speed data transmission interface based on the FPGA as a high-speed data transmission channel between the high-performance data access device and other I/O modules or among a plurality of cascade or parallel high-performance data access devices, so that the device has the characteristics of high-speed data access, PCIe bus system support, modularization expansion and variable topological connection without CPU intervention scheduling, thereby meeting the requirements of high-bandwidth signal data access and high-speed data access of more channels at the same time.
To further illustrate the high performance data access device provided in this embodiment, the following provides a more detailed circuit structure of the high performance data access device:
in one aspect, referring to fig. 1, in this embodiment, the high performance data access device may further include, but is not limited to: an interface IP module, where the interface IP module (MGT IP in fig. 1 represents an interface IP module) includes at least one MGT transceiver, and the FPGA module is electrically connected to each of the uplink data transmission interface and the downlink data transmission interface through the interface IP module, so as to control, by using the interface IP module, the at least one MGT transceiver to implement a data transmission function of the uplink data transmission interface and the downlink data transmission interface; based on the above, the high-speed transmission characteristic of the high-speed data transmission interface can be realized based on the MGT transceiver, so that the FPGA module can be responsible for providing the multi-port high-speed data transmission interface and transmitting data with the high-speed data transmission characteristic.
In another aspect, the high performance data access device may further include, but is not limited to: and the FPGA module is electrically connected with each DRAM module respectively, and the transmission process of the FPGA module is specifically described by taking the data communication between the high-performance data access device and the signal receiving and transmitting equipment and the external data equipment as an example.
In this embodiment, when data is stored, the FPGA module is configured to split and encode a high-speed data stream transmitted from an uplink data transmission interface or a downlink data transmission interface of the local device to obtain processed data, and write the processed data into each storage module in parallel based on each DRAM module; and similarly, when data is transmitted, the FPGA module is used for reading data from each storage module based on each DRAM module, and carrying out data decoding and merging processing on the read data to obtain decoded and merged data, so that the decoded and merged data is transmitted to external data equipment and/or the signal transceiving equipment through an uplink data transmission interface or a downlink data transmission interface of the FPGA module.
In specific implementation, any storage module (which may be, but is not limited to, a solid state disk with SATA or NVMe interface) is used for storing data, a DRAM (dynamic random access memory) unit is mainly used for buffering data, and multiple storage modules and DRAM units cooperate to realize parallel data storage and reading; referring to fig. 1, in this embodiment, the FPGA processes IP for SATA/NVMe SSD control and communication on the eudipleural, and IP for DRAM (DRAM in fig. 3 represents a DRAM processing unit) control and communication on the FPGA module is identified by IP4, where the FPGA module obtains a high-speed data stream through MGT IP (i.e., the aforementioned interface IP module), splits and encodes the data stream, and writes multiple sets of SATA/NVMe SSDs in parallel, and the writing process uses DRAM units to buffer data, so as to implement smooth data writing; similarly, the reading process is the same, the FPGA module reads data from multiple groups of SATA/NVMe SSDs, and in the reading process, the data is buffered by using a DRAM unit, then the original data stream is decoded and restored, and the data stream is sent out through the MGT IP; based on the design, the high-performance data access device can directly carry out management scheduling of the FPGA by an external system controller through using PCIe resources, digital I/O channels and corresponding communication and control bus interfaces of the FPGA, namely, corresponding scheduling instructions are sent to the FPGA module, so that the FPGA module carries out data reading and mode based on the instructions, and the convenient data access and management on a plurality of groups of SATA/NVMe SSDs are realized according to standard disk objects; meanwhile, when data access and management are carried out, the scheduling of the data can be realized according to the FPGA of the system controller without CPU access of the system controller; based on this, the problem that the CPU becomes a bottleneck restriction of the data reading and writing capability can be avoided.
In addition, in the present embodiment, the high performance data access device further includes: a control bus interface connector (e.g., a PXIe connector), wherein the high-performance data access device is connected with a backplane bus interface of the PCIe bus-based data transmission device through the control bus interface connector, so as to implement data communication between the high-performance data access device and the PCIe bus-based data transmission device; in this embodiment, the FPGA module (i.e., FPGA chip) also connects to the board and carries FLASH, which is used to store the FPGA firmware program, so as to implement the corresponding control function.
In summary, the high performance data access device can operate in different data modes, which are respectively a cascade data transmission mode, a point-to-point data transmission mode, a parallel data transmission mode, a star data transmission mode or a composite data transmission mode combining any of the above transmission modes (e.g. a composite data transmission mode combining a star and a cascade), and the working process is as follows:
firstly, address allocation and data transmission relation determination are carried out firstly; in this embodiment, the high-performance data access device determines the data transmission mode by way of example as follows;
The high-performance data access device receives an equipment address addressing instruction sent by the system controller, and sends equipment address inquiry information to a designated high-performance data access device through a corresponding uplink data transmission interface or downlink data transmission interface so as to receive a target equipment address sent by the designated high-performance data access device, wherein the designated high-performance data access device is all high-performance data access devices with a connection relation with the high-performance data access device; and then, the high-performance data access device sends the self device address and the target device address to the system controller through the communication and control bus interface, so that the system controller determines the connection relation and the data transmission mode between the high-performance data access device and the appointed high-performance data access device according to the uplink data transmission interface and the downlink data transmission interface which are connected with the appointed high-performance data access device, the target device address and the self device address.
Thus, the foregoing determination process is interpreted as: the system controller distributes unique equipment addresses for each high-performance data access device through a communication and control bus interface, then controls each high-performance data access device to carry out equipment address inquiry on the connected previous high-performance data access device and the connected next high-performance data access device (and all other connected high-performance data access devices) through an uplink data transmission interface and a downlink data transmission interface (and all other interfaces), and transmits the inquired equipment addresses (namely target equipment addresses) of the uplink high-performance data access device and the downlink high-performance data access device (and all other connected high-performance data access devices) back to the system controller through a bus controller circuit; the system controller obtains the connection relation of all the high-speed data access devices by obtaining the device address of each high-performance data access device, the address of the connected uplink device and the address of the connected downlink device, so that the specific working mode of the high-speed data transmission interface is set through the communication and control bus interface according to the connection relation.
Based on this, after obtaining the connection relationship corresponding to the high performance data access device, data transmission can be performed:
in this embodiment, the high-performance data access device performs data transmission with an external data device, a signal transceiver device, or a target high-performance data access device in the following manner.
Firstly, a high-performance data access device acquires a data transmission mode, wherein the data transmission mode comprises a cascade data transmission mode, a point-to-point data transmission mode, a parallel data transmission mode, a star data transmission mode and a composite data transmission mode combining any transmission modes; the high performance data access device may then perform data transmission in different manners according to the data transmission mode, as follows.
If the data transmission mode is a cascade data transmission mode, the high-performance data access device firstly acquires a target equipment address of the target performance data access device; then, the high-performance data access device acquires data to be transmitted from external data equipment, the signal receiving and transmitting equipment or corresponding storage modules, and generates a data packet based on the data to be transmitted and the destination equipment address; and then, the high-performance data access device utilizes a corresponding uplink data transmission interface or a corresponding downlink data transmission interface to transmit the data packet to a higher-level high-performance data access device or a lower-level high-performance data access device connected with the high-performance data access device, so that the higher-level high-performance data access device or the lower-level high-performance data access device judges whether the destination equipment address in the data packet is consistent with the local equipment address, and when the destination equipment address is inconsistent with the local equipment address, the data packet is transmitted again until the destination equipment address is transmitted to the target high-performance data access device.
Thus, when the high-performance data access device is in the cascade data transmission mode, if a certain high-performance data access device needs to perform data communication with another high-performance data access device through the high-speed data transmission interface, the high-performance data access device can determine whether to perform data communication from the uplink data transmission interface or the downlink data transmission interface through the device connection relationship and the device address of the target high-speed data access device; meanwhile, when communication is carried out, all data are packed through a unified frame structure, and each frame of data comprises equipment addresses and data; thus, when the high-performance data access device receives a frame of data through the uplink or downlink data transmission interface, the device address contained in the high-performance data access device is judged whether to be the same as the self address, so that the data is received and forwarded, namely if the device address is the same, the data is received, and if the device address is not the same, the data is forwarded through the downlink or uplink interface until the data is received by the target high-speed data access device; thus, by the foregoing design, data communication between all cascaded high performance data access devices is possible at a data rate of up to 96Gbps or 12 GB/s.
Secondly, if the data transmission mode is a point-to-point data transmission mode, the high-performance data access device reads data to be transmitted from each corresponding storage module and directly transmits the data to be transmitted to the external data equipment or the signal receiving and transmitting equipment through a corresponding uplink data transmission interface or downlink data transmission interface; or the high-performance data access device acquires the data to be stored from the external data equipment or the signal receiving and transmitting equipment through the corresponding uplink data transmission interface or the corresponding downlink data transmission interface, and stores the data to be stored into each storage module corresponding to the high-performance data access device.
Based on this, when two high performance data access apparatuses are in a point-to-point connection relationship (i.e., the apparatuses are in a point-to-point data transmission mode), the upstream data transmission interface and the downstream data transmission interface (and all other interfaces) of each high performance data access apparatus can be connected in parallel exclusively with the external data device, the signal transceiving apparatus, and the upstream data transmission interface and the downstream data transmission interface (and all other interfaces) of the other high performance data access apparatus can be connected in parallel, at which time data communication can be directly completed without a packet by a frame structure, and a data communication rate of 192Gbps or 24GB/s or more can be achieved through the parallel high speed data transmission interfaces.
Similarly, if the data transmission mode is a parallel data transmission mode, the high-performance data access device reads data to be transmitted from each corresponding storage module, and directly transmits the data to be transmitted to the external data equipment or the signal receiving and transmitting equipment in a multi-channel data transmission mode through the corresponding uplink data transmission interface and the corresponding downlink data transmission interface; or the high-performance data access device acquires data to be stored from external data equipment or the signal receiving and transmitting equipment in a multi-channel data transmission mode through a corresponding uplink data transmission interface and a corresponding downlink data transmission interface, and stores the data to be stored into each storage module corresponding to the high-performance data access device; if the high-performance data access device is provided with two high-speed data transmission interfaces, the high-performance data access device and external data equipment can realize parallel transmission of data through two channels; of course, when the number of the high-speed data transmission interfaces is the rest, the data transmission process is the same as the foregoing example, and will not be repeated here.
Finally, when all the high-performance data access devices are in a star connection relationship or a star and cascade composite connection relationship, high-speed data communication between the high-performance data access devices can be realized by adopting a frame structure data group package or a composite data transmission mode of direct data transmission according to specific application requirements.
In one possible design, referring to fig. 5, a second aspect of the present embodiment provides a first application structure of the high performance data access device according to the first aspect of the foregoing embodiment, and the specific description is given by taking a PXIe bus interface as an example of the communication and control bus interface, which is described below.
Referring to fig. 5, a PXIe system controller connects a PXIe signaling device and a plurality of PXIe high-performance data access apparatuses through a PXIe bus to control and manage all the PXIe signaling devices and the high-performance data access apparatuses.
The PXIe signal transceiver is an I/O module based on a PXIe bus, and also has a set of multi-port high-speed data transmission interface, which is used for transmitting the collected data to the high-performance data access device at a high speed by utilizing the high-speed data transmission interface after receiving and collecting signals from the outside.
The PXIe signal receiving and transmitting equipment is connected with an uplink data transmission interface of one high-performance data access device through a downlink data transmission interface of the PXIe signal receiving and transmitting equipment, and the downlink data transmission interface of the high-performance data access device is further connected with an uplink data transmission interface of the next high-performance data access device in a cascade mode; in this way, the PXIe signal transceiver device can transmit and store the collected signal data to each high-performance data access device in a cascade transmission manner, and the workflow of data reading and corresponding signal generation is similar in principle, except that the transmission directions of signals are opposite, and will not be described herein.
Based on this, this connection method can complete the task that the original PXIe system cannot do: 1. data transmission between PXIe modules is achieved at a higher single module transmission rate (> 8 GB/s) than the PXIe bus; 2. after the storage capacity of one high-performance data access device is full, the cascade connected high-speed data transmission interface can be used for transmitting data to the next high-performance data access device and continuously storing the data, so that the purpose of capacity expansion is achieved.
In one possible design, referring to fig. 6, a third aspect of the present embodiment provides a third application structure of the high performance data access device according to the first aspect of the foregoing embodiment, which is also specifically described by taking a PXIe bus interface as an example of the communication and control bus interface, as follows.
Referring to fig. 6, a plurality of PXIe signal transceiving devices are respectively connected with a plurality of high-performance data access devices through a downlink data transmission interface of the PXIe signal transceiving device in a one-to-one manner to an uplink data transmission interface of the corresponding high-performance data access device; in this way, each PXIe signaling device will have an independent high performance data access device that works in concert with it.
Based on this, this connection method can complete the task that the original PXIe system cannot do: 1. data transmission between PXIe modules is achieved at a higher single module transmission rate (> 8 GB/s) than the PXIe bus; 2. the sum of the data rates generated by the multi-channel signal acquisition, storage and reading can greatly exceed the total bandwidth (24 GB/s) of the PXIe bus system.
In one possible design, referring to fig. 7, a fourth aspect of the present embodiment provides a third application structure of the high performance data access device according to the first aspect of the foregoing embodiment, which is also specifically described by taking a PXIe bus interface as an example of the communication and control bus interface, as follows.
Referring to fig. 7, a PXIe signal transceiver is connected in parallel with a high-performance data access device through multiple pairs of high-speed data transmission interfaces, so that each PXIe signal transceiver can simultaneously utilize multiple groups of parallel high-speed data transmission interfaces to perform data transmission with the high-performance data access device, thereby achieving the effect of doubling the data transmission rate.
Thus, the connection mode can complete tasks which cannot be achieved by the original PXIe system: 1. continuous data transmission of signals with particularly high bandwidth (such as instantaneous bandwidth of more than or equal to 4GHz and data rate of more than or equal to 20 GB/s) is realized; 2. multiple high-bandwidth signal channels (e.g., 4-channel 1GHz instantaneous bandwidth, totaling 20GB/s data rates) on a single signal transceiver device are enabled for continuous data transmission with a high-performance data access device simultaneously.
In one possible design, referring to fig. 8, a fifth aspect of the present embodiment provides a fourth application structure of the high performance data access device in the first aspect of the foregoing embodiment, which is also specifically described below by taking a PXIe bus interface as an example of the communication and control bus interface.
Referring to fig. 8, a PXIe signal transceiver is connected to the uplink data transmission interfaces of the high-performance data access devices respectively by a star connection manner with a plurality of high-speed data transmission interfaces thereof, and the downlink data transmission interface of each high-performance data access device may be further connected to the uplink data transmission interface of the next high-performance data access device in a cascade manner, so that a composite connection manner combining a star connection and a cascade connection may be formed, and thus each PXIe signal transceiver may transmit data to the high-performance data access devices simultaneously.
Based on this, this connection method can complete the task that the original PXIe system cannot do: 1. data transmission between PXIe modules is achieved at a higher single module transmission rate (> 8 GB/s) than the PXIe bus; 2. realizing continuous data transmission between a plurality of high-bandwidth signal channels (such as 4-channel 1GHz instantaneous bandwidth and total 20GB/s data rate) on a single signal transceiver and a plurality of high-performance data access devices at the same time, so that the continuous storage and reading rate of system total data are not limited by the continuous reading and writing rate of the single high-performance data access device; 3. the high performance data access device can increase the storage capacity through a cascade connection mode.
Of course, the foregoing application structure is merely an example, and in a specific application process, different data expansion access systems can be constructed based on different application scenarios according to the high-performance data access device provided in this embodiment.
In summary, the high-performance data access device provided by the invention has the following beneficial effects:
(1) The compatibility is good. The invention can realize a high-performance data access device by using commercial PCIe, CPCIe, PXIe or VPX standard, thereby utilizing the mature hardware and software ecosystems of the bus platforms to combine and construct a complete signal acquisition, storage, reading and generation system.
(2) High performance. The high-performance data access device can be connected with the system controller by adopting a PCIe bus interface or an instrument expansion bus interface based on PCIe, and has 8GB/s module interface bandwidth; the high-performance data access device is connected with external data equipment by adopting a high-speed data transmission interface of the high-performance data access device, and can provide 24GB/s data transmission bandwidth in total; thus, the back board bus interface and the front board high-speed data transmission interface can meet the requirements of most high-speed data access applications.
(3) Flexible topology connections. Through the cascade connection, opposite connection, parallel connection, star connection and other topological connection modes of the high-speed data transmission interface and the connection modes of different topological connection combinations, a plurality of high-performance data access devices can realize very flexible and high-performance data transmission capability between the high-performance data access devices and other I/O modules in the system, and the multi-channel broadband radio frequency application which depends on high-speed data transmission is greatly assisted.
(4) Is convenient and easy to use. Custom high-speed data storage systems typically employ dedicated high-speed data interface buses, such as Aurora, rapidIO, LVDS, which are custom-dedicated, so that storage device drivers and application management are relatively weak; on the basis of the customized high-speed data transmission interface, the invention synchronously realizes the standard PCIe protocol, thereby utilizing the standard disk equipment management drive and application software of the operating system, and enabling the system controller to conveniently and effectively manage the system by utilizing the management software of the standard disk equipment.
(5) And the integration level is high. In order to realize the function of the high-performance data access device, the conventional data access product in the market needs a separately customized data transmission module to be connected with the signal receiving and transmitting equipment through a high-speed data transmission interface, and is usually connected with a separate disk array storage device containing a high-speed optical fiber interface module through a high-speed optical fiber interface; the invention integrates the data transmission module, the high-speed optical fiber interface module and the disk array storage device into a device so as to replace the traditional disk array storage device and the high-speed optical fiber interface module by utilizing the FPGA, the FPGA MGT interface based on the interface IP module and the high-speed data transmission interface in the device, thereby realizing the corresponding high-speed data access function. Based on the above, the custom data transmission module and the high-speed optical fiber interface module are not needed, so that the volume of the device can be greatly reduced, and the cost of the device can be greatly reduced.
Finally, it should be noted that: the foregoing description is only of the preferred embodiments of the invention and is not intended to limit the scope of the invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A high performance data access apparatus, comprising:
the FPGA module is in communication connection with the system controller through the communication and control bus interface so as to perform data communication with the system controller based on the communication and control bus interface, and the communication and control bus interface comprises a PCIe bus interface or an instrument expansion bus interface based on PCIe;
the high performance data access device further includes:
the system comprises a plurality of high-speed data transmission interfaces based on FPGA modules and a plurality of storage modules, wherein the FPGA modules are respectively and electrically connected with each storage module and each high-speed data transmission interface;
the plurality of high-speed data transmission interfaces comprise an uplink data transmission interface and a downlink data transmission interface, the uplink data transmission interface and the downlink data transmission interface realize data transmission by adopting a plurality of full duplex serial links, and a data communication protocol adopted by the uplink data transmission interface and the downlink data transmission interface comprises an Aurora protocol;
the uplink data transmission interface is used for being in communication connection with a signal receiving and transmitting device or a downlink data transmission interface of a previous-stage high-performance data access device with a cascade relation with the high-performance data access device, and the downlink data transmission interface is used for being in communication connection with the signal receiving and transmitting device or an uplink data transmission interface of a subsequent-stage high-performance data access device with a cascade relation with the high-performance data access device, so that the high-performance data access device forms a cascade connection mode, a parallel connection mode, a point-to-point connection mode, a star connection mode or a composite connection mode combined with any connection mode between the signal receiving and transmitting device and the other high-performance data access devices based on the uplink data transmission interface and/or the downlink data transmission interface of the high-performance data access device;
The high performance data access device further includes: and the interface IP module comprises at least one MGT transceiver, and the FPGA module is electrically connected with each uplink data transmission interface and each downlink data transmission interface through the interface IP module so as to control the at least one MGT transceiver to realize the data transmission function of the uplink data transmission interface and the downlink data transmission interface through the interface IP module.
2. The high performance data access device of claim 1, further comprising: at least one DRAM module, wherein the FPGA module is electrically connected with each DRAM module respectively;
the FPGA module is used for splitting and encoding the high-speed data stream when receiving the high-speed data stream transmitted from the local uplink data transmission interface or the local downlink data transmission interface to obtain processed data, and writing the processed data into each storage module in parallel based on each DRAM module;
the FPGA module is also used for reading data from each storage module based on each DRAM module, carrying out data decoding and merging processing on the read data to obtain decoded and merged data, and sending the decoded and merged data to external data equipment and/or the signal receiving and transmitting equipment through an uplink data transmission interface or a downlink data transmission interface of the FPGA module.
3. The high performance data access device of claim 1, wherein the upstream data transmission interface and the downstream data transmission interface each employ a Nano-Pitch connector.
4. The high performance data access device of claim 1, further comprising: and the control bus interface connector is used for connecting the high-performance data access device with a backboard bus interface of the data transmission equipment based on the PCIe bus through the control bus interface connector so as to realize data communication between the high-performance data access device and the data transmission equipment based on the PCIe bus.
5. The high performance data access device of claim 1, wherein any one of the plurality of storage modules is a solid state disk with SATA or NVMe interface.
6. The high performance data access device of claim 1, wherein the PCIe-based instrument expansion bus interface comprises: a PXIe bus interface, a CPCIe bus interface, or a VPX bus interface.
7. The high-performance data access device according to claim 1, wherein the high-performance data access device performs data transmission with an external data apparatus, the signal transceiver apparatus, or a target high-performance data access device in the following manner;
The high-performance data access device acquires a data transmission mode, wherein the data transmission mode comprises a cascade data transmission mode, a point-to-point data transmission mode, a parallel data transmission mode, a star data transmission mode or a composite data transmission mode combining any transmission modes;
if the data transmission mode is a cascade data transmission mode, the high-performance data access device acquires a destination equipment address of a target high-performance data access device;
the high-performance data access device acquires data to be transmitted from external data equipment, the signal receiving and transmitting equipment or corresponding storage modules, and generates a data packet based on the data to be transmitted and the destination equipment address;
the high-performance data access device utilizes a corresponding uplink data transmission interface or a corresponding downlink data transmission interface to transmit the data packet to a higher-level high-performance data access device or a lower-level high-performance data access device connected with the high-performance data access device, so that the higher-level high-performance data access device or the lower-level high-performance data access device judges whether a destination equipment address in the data packet is consistent with a local equipment address, and when the destination equipment address is inconsistent with the local equipment address, the data packet is transmitted again until the destination equipment address is transmitted to the target high-performance data access device;
If the data transmission mode is a point-to-point data transmission mode, the high-performance data access device reads data to be transmitted from each corresponding storage module and directly transmits the data to be transmitted to the external data equipment or the signal receiving and transmitting equipment through a corresponding uplink data transmission interface or downlink data transmission interface; or (b)
The high-performance data access device acquires data to be stored from external data equipment or the signal receiving and transmitting equipment through a corresponding uplink data transmission interface or a corresponding downlink data transmission interface, and stores the data to be stored into each storage module corresponding to the high-performance data access device;
if the data transmission mode is a parallel data transmission mode, the high-performance data access device reads data to be transmitted from each corresponding storage module, and directly transmits the data to be transmitted to the external data equipment or the signal receiving and transmitting equipment in a multi-channel data transmission mode through a corresponding uplink data transmission interface and downlink data transmission interface; or (b)
The high-performance data access device acquires data to be stored from external data equipment or the signal receiving and transmitting equipment in a multi-channel data transmission mode through the corresponding uplink data transmission interface and the corresponding downlink data transmission interface, and stores the data to be stored into each storage module corresponding to the high-performance data access device.
8. A high performance data access device according to claim 1, wherein the high performance data access device determines the data transmission mode by;
the high-performance data access device receives an equipment address addressing instruction sent by the system controller, and sends equipment address inquiry information to a designated high-performance data access device through a corresponding uplink data transmission interface or downlink data transmission interface so as to receive a target equipment address sent by the designated high-performance data access device, wherein the designated high-performance data access device is all high-performance data access devices with a connection relation with the high-performance data access device;
the high-performance data access device sends the self device address and the target device address to the system controller through the communication and control bus interface, so that the system controller determines the connection relation and the data transmission mode between the high-performance data access device and the appointed high-performance data access device according to the uplink data transmission interface and the downlink data transmission interface which are connected with the appointed high-performance data access device, the target device address and the self device address.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310669039.1A CN116737624B (en) | 2023-06-06 | 2023-06-06 | High-performance data access device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310669039.1A CN116737624B (en) | 2023-06-06 | 2023-06-06 | High-performance data access device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116737624A CN116737624A (en) | 2023-09-12 |
| CN116737624B true CN116737624B (en) | 2024-03-12 |
Family
ID=87907389
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310669039.1A Active CN116737624B (en) | 2023-06-06 | 2023-06-06 | High-performance data access device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116737624B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116955258B (en) * | 2023-09-19 | 2023-11-28 | 成都立思方信息技术有限公司 | Flexibly-connectable trigger connector, signal acquisition control equipment and system |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2791752Y (en) * | 2005-04-04 | 2006-06-28 | 苏州鹞鹰数据技术有限公司 | High-speed data storage apparatus |
| CN102521182A (en) * | 2011-11-23 | 2012-06-27 | 华南师范大学 | Extensible multichannel parallel real-time data acquisition device and method |
| CN103543961A (en) * | 2013-10-12 | 2014-01-29 | 浙江宇视科技有限公司 | PCIe-based storage extension system and method |
| CN107167174A (en) * | 2017-04-05 | 2017-09-15 | 中北大学 | Distributed type minisize data collecting system |
| CN109190276A (en) * | 2018-09-14 | 2019-01-11 | 天津市滨海新区信息技术创新中心 | FPGA prototype verification system |
| CN111913906A (en) * | 2020-06-24 | 2020-11-10 | 济南浪潮高新科技投资发展有限公司 | Cascading board card for 3U PXIe measurement and control cabinet expansion and method for expanding measurement and control cabinet |
| CN113360444A (en) * | 2021-06-24 | 2021-09-07 | 成都能通科技有限公司 | Data synchronous generation method based on daisy chain cascade data generation system |
| CN113626351A (en) * | 2021-08-11 | 2021-11-09 | 成都博宇利华科技有限公司 | Cascade method of PCIe signal processing cards |
| CN113742270A (en) * | 2020-05-27 | 2021-12-03 | 合肥君正科技有限公司 | Chip cascade and parallel computing system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20220382944A1 (en) * | 2021-05-21 | 2022-12-01 | Intel Corporation | Extended inter-kernel communication protocol for the register space access of the entire fpga pool in non-star mode |
-
2023
- 2023-06-06 CN CN202310669039.1A patent/CN116737624B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2791752Y (en) * | 2005-04-04 | 2006-06-28 | 苏州鹞鹰数据技术有限公司 | High-speed data storage apparatus |
| CN102521182A (en) * | 2011-11-23 | 2012-06-27 | 华南师范大学 | Extensible multichannel parallel real-time data acquisition device and method |
| CN103543961A (en) * | 2013-10-12 | 2014-01-29 | 浙江宇视科技有限公司 | PCIe-based storage extension system and method |
| CN107167174A (en) * | 2017-04-05 | 2017-09-15 | 中北大学 | Distributed type minisize data collecting system |
| CN109190276A (en) * | 2018-09-14 | 2019-01-11 | 天津市滨海新区信息技术创新中心 | FPGA prototype verification system |
| CN113742270A (en) * | 2020-05-27 | 2021-12-03 | 合肥君正科技有限公司 | Chip cascade and parallel computing system |
| CN111913906A (en) * | 2020-06-24 | 2020-11-10 | 济南浪潮高新科技投资发展有限公司 | Cascading board card for 3U PXIe measurement and control cabinet expansion and method for expanding measurement and control cabinet |
| CN113360444A (en) * | 2021-06-24 | 2021-09-07 | 成都能通科技有限公司 | Data synchronous generation method based on daisy chain cascade data generation system |
| CN113626351A (en) * | 2021-08-11 | 2021-11-09 | 成都博宇利华科技有限公司 | Cascade method of PCIe signal processing cards |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116737624A (en) | 2023-09-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108776647B (en) | AXI bus-based multi-DDR (double data Rate) controller management system | |
| US6301637B1 (en) | High performance data paths | |
| CN1552028B (en) | Method and apparatus for distributed direct memory access for systems on chip | |
| CN116841932B (en) | Flexibly-connectable portable high-speed data access equipment and working method thereof | |
| CN111581153A (en) | Radar signal processing device based on Open VPX | |
| CN106095334B (en) | A kind of high-speed data acquisition storage system based on FPGA | |
| CN116737624B (en) | High-performance data access device | |
| CN111338996B (en) | Composite bus controller supporting multiple protocols | |
| CN105549916A (en) | Peripheral component interconnect express (PCIe) solid state hard disk controller, PCIe based storage system and data read and write method thereof | |
| CN102520892A (en) | Multifunctional solid state data storage playback instrument | |
| CN113590528A (en) | Multi-channel data acquisition, storage and playback card, system and method based on HP interface | |
| CN105007307A (en) | Storage control method and system | |
| CN114168520A (en) | Optical fiber communication bus device, equipment and system | |
| CN101004674A (en) | Processor architecture | |
| Kwon et al. | Gen-z memory pool system architecture | |
| CN111147522A (en) | Multi-channel RocktIO protocol and FC protocol real-time conversion method | |
| WO2007092271A2 (en) | Multi-stream interface for parallel test processing | |
| CN114721983B (en) | DDR4 accelerating read-write device | |
| CN108055460B (en) | High speed image processing and acquisition system | |
| CN216014252U (en) | Multi-channel data acquisition, storage and playback card and system based on HP interface | |
| CN215376139U (en) | Efficient data acquisition system based on ARM and FPGA | |
| US20090177832A1 (en) | Parallel computer system and method for parallel processing of data | |
| US20110090924A1 (en) | System to connect a serial scsi array controller to a storage area network | |
| US6611895B1 (en) | High bandwidth cache system | |
| JPH0969030A (en) | Disk array system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |